src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/types.hh"
  43 #include "base/statistics.hh"
  44 #include "base/timebuf.hh"
  45 #include "base/types.hh"
  46 #include "config/full_system.hh"
  47 #include "cpu/activity.hh"
  48 #include "cpu/base.hh"
  49 #include "cpu/simple_thread.hh"
  50 #include "cpu/inorder/inorder_dyn_inst.hh"
  51 #include "cpu/inorder/pipeline_traits.hh"
  52 #include "cpu/inorder/pipeline_stage.hh"
  53 #include "cpu/inorder/thread_state.hh"
  54 #include "cpu/inorder/reg_dep_map.hh"
  55 #include "cpu/o3/dep_graph.hh"
  56 #include "cpu/o3/rename_map.hh"
  57 #include "mem/packet.hh"
  58 #include "mem/port.hh"
  59 #include "mem/request.hh"
  60 #include "sim/eventq.hh"
  61 #include "sim/process.hh"
  62
  63 class ThreadContext;
  64 class MemInterface;
  65 class MemObject;
  66 class Process;
  67 class ResourcePool;
  68
  69 class InOrderCPU : public BaseCPU
  70 {
  71
  72   protected:
  73     typedef ThePipeline::Params Params;
  74     typedef InOrderThreadState Thread;
  75
  76    //ISA TypeDefs
  77     typedef TheISA::IntReg IntReg;
  78     typedef TheISA::FloatReg FloatReg;
  79     typedef TheISA::FloatRegBits FloatRegBits;
  80     typedef TheISA::MiscReg MiscReg;
  81
  82     //DynInstPtr TypeDefs
  83     typedef ThePipeline::DynInstPtr DynInstPtr;
  84     typedef std::list<DynInstPtr>::iterator ListIt;
  85
  86     //TimeBuffer TypeDefs
  87     typedef TimeBuffer<InterStageStruct> StageQueue;
  88
  89     friend class Resource;
  90
  91   public:
  92     /** Constructs a CPU with the given parameters. */
  93     InOrderCPU(Params *params);
  94
  95     /** CPU ID */
  96     int cpu_id;
  97
  98     /** Type of core that this is */
  99     std::string coreType;
 100
 101     int readCpuId() { return cpu_id; }
 102
 103     void setCpuId(int val) { cpu_id = val; }
 104
 105     Params *cpu_params;
 106
 107   public:
 108     enum Status {
 109         Running,
 110         Idle,
 111         Halted,
 112         Blocked,
 113         SwitchedOut
 114     };
 115
 116     /** Overall CPU status. */
 117     Status _status;
 118
 119   private:
 120     /** Define TickEvent for the CPU */
 121     class TickEvent : public Event
 122     {
 123       private:
 124         /** Pointer to the CPU. */
 125         InOrderCPU *cpu;
 126
 127       public:
 128         /** Constructs a tick event. */
 129         TickEvent(InOrderCPU *c);
 130
 131         /** Processes a tick event, calling tick() on the CPU. */
 132         void process();
 133
 134         /** Returns the description of the tick event. */
 135         const char *description();
 136     };
 137
 138     /** The tick event used for scheduling CPU ticks. */
 139     TickEvent tickEvent;
 140
 141     /** Schedule tick event, regardless of its current state. */
 142     void scheduleTickEvent(int delay)
 143     {
 144         if (tickEvent.squashed())
 145           mainEventQueue.reschedule(&tickEvent, nextCycle(curTick + ticks(delay)));
 146         else if (!tickEvent.scheduled())
 147           mainEventQueue.schedule(&tickEvent, nextCycle(curTick + ticks(delay)));
 148     }
 149
 150     /** Unschedule tick event, regardless of its current state. */
 151     void unscheduleTickEvent()
 152     {
 153         if (tickEvent.scheduled())
 154             tickEvent.squash();
 155     }
 156
 157   public:
 158     // List of Events That can be scheduled from
 159     // within the CPU.
 160     // NOTE(1): The Resource Pool also uses this event list
 161     // to schedule events broadcast to all resources interfaces
 162     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 163     // pool event.
 164     enum CPUEventType {
 165         ActivateThread,
 166         DeallocateThread,
 167         SuspendThread,
 168         DisableThreads,
 169         EnableThreads,
 170         DisableVPEs,
 171         EnableVPEs,
 172         Trap,
 173         InstGraduated,
 174         SquashAll,
 175         UpdatePCs,
 176         NumCPUEvents
 177     };
 178
 179     static std::string eventNames[NumCPUEvents];
 180
 181     /** Define CPU Event */
 182     class CPUEvent : public Event
 183     {
 184       protected:
 185         InOrderCPU *cpu;
 186
 187       public:
 188         CPUEventType cpuEventType;
 189         ThreadID tid;
 190         unsigned vpe;
 191         Fault fault;
 192
 193       public:
 194         /** Constructs a CPU event. */
 195         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 196                  ThreadID _tid, unsigned _vpe);
 197
 198         /** Set Type of Event To Be Scheduled */
 199         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 200                       unsigned _vpe)
 201         {
 202             fault = _fault;
 203             cpuEventType = e_type;
 204             tid = _tid;
 205             vpe = _vpe;
 206         }
 207
 208         /** Processes a resource event. */
 209         virtual void process();
 210
 211         /** Returns the description of the resource event. */
 212         const char *description();
 213
 214         /** Schedule Event */
 215         void scheduleEvent(int delay);
 216
 217         /** Unschedule This Event */
 218         void unscheduleEvent();
 219     };
 220
 221     /** Schedule a CPU Event */
 222     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 223                           unsigned vpe, unsigned delay = 0);
 224
 225   public:
 226     /** Interface between the CPU and CPU resources. */
 227     ResourcePool *resPool;
 228
 229     /** Instruction used to signify that there is no *real* instruction in buffer slot */
 230     DynInstPtr dummyBufferInst;
 231
 232     /** Used by resources to signify a denied access to a resource. */
 233     ResourceRequest *dummyReq;
 234
 235     /** Identifies the resource id that identifies a fetch
 236      * access unit.
 237      */
 238     unsigned fetchPortIdx;
 239
 240     /** Identifies the resource id that identifies a ITB       */
 241     unsigned itbIdx;
 242
 243     /** Identifies the resource id that identifies a data
 244      * access unit.
 245      */
 246     unsigned dataPortIdx;
 247
 248     /** Identifies the resource id that identifies a DTB       */
 249     unsigned dtbIdx;
 250
 251     /** The Pipeline Stages for the CPU */
 252     PipelineStage *pipelineStage[ThePipeline::NumStages];
 253
 254     /** Program Counters */
 255     TheISA::IntReg PC[ThePipeline::MaxThreads];
 256     TheISA::IntReg nextPC[ThePipeline::MaxThreads];
 257     TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
 258
 259     /** The Register File for the CPU */
 260     union {
 261         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 262         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 263     } floatRegs;
 264     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 265
 266     /** ISA state */
 267     TheISA::ISA isa[ThePipeline::MaxThreads];
 268
 269     /** Dependency Tracker for Integer & Floating Point Regs */
 270     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 271
 272     /** Global communication structure */
 273     TimeBuffer<TimeStruct> timeBuffer;
 274
 275     /** Communication structure that sits in between pipeline stages */
 276     StageQueue *stageQueue[ThePipeline::NumStages-1];
 277
 278     TheISA::TLB *getITBPtr();
 279     TheISA::TLB *getDTBPtr();
 280
 281   public:
 282
 283     /** Registers statistics. */
 284     void regStats();
 285
 286     /** Ticks CPU, calling tick() on each stage, and checking the overall
 287      *  activity to see if the CPU should deschedule itself.
 288      */
 289     void tick();
 290
 291     /** Initialize the CPU */
 292     void init();
 293
 294     /** Reset State in the CPU */
 295     void reset();
 296
 297     /** Get a Memory Port */
 298     Port* getPort(const std::string &if_name, int idx = 0);
 299
 300     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 301      *  trapCPU() - Traps to handle given fault
 302      */
 303     void trap(Fault fault, ThreadID tid, int delay = 0);
 304     void trapCPU(Fault fault, ThreadID tid);
 305
 306     /** Setup CPU to insert a thread's context */
 307     void insertThread(ThreadID tid);
 308
 309     /** Remove all of a thread's context from CPU */
 310     void removeThread(ThreadID tid);
 311
 312     /** Add Thread to Active Threads List. */
 313     void activateContext(ThreadID tid, int delay = 0);
 314     void activateThread(ThreadID tid);
 315
 316     /** Remove Thread from Active Threads List */
 317     void suspendContext(ThreadID tid, int delay = 0);
 318     void suspendThread(ThreadID tid);
 319
 320     /** Remove Thread from Active Threads List &&
 321      *  Remove Thread Context from CPU.
 322      */
 323     void deallocateContext(ThreadID tid, int delay = 0);
 324     void deallocateThread(ThreadID tid);
 325     void deactivateThread(ThreadID tid);
 326
 327     PipelineStage* getPipeStage(int stage_num);
 328
 329     int
 330     contextId()
 331     {
 332         hack_once("return a bogus context id");
 333         return 0;
 334     }
 335
 336     /** Remove Thread from Active Threads List &&
 337      *  Remove Thread Context from CPU.
 338      */
 339     void haltContext(ThreadID tid, int delay = 0);
 340
 341     void removePipelineStalls(ThreadID tid);
 342
 343     void squashThreadInPipeline(ThreadID tid);
 344
 345     /// Notify the CPU to enable a virtual processor element.
 346     virtual void enableVirtProcElement(unsigned vpe);
 347     void enableVPEs(unsigned vpe);
 348
 349     /// Notify the CPU to disable a virtual processor element.
 350     virtual void disableVirtProcElement(ThreadID tid, unsigned vpe);
 351     void disableVPEs(ThreadID tid, unsigned vpe);
 352
 353     /// Notify the CPU that multithreading is enabled.
 354     virtual void enableMultiThreading(unsigned vpe);
 355     void enableThreads(unsigned vpe);
 356
 357     /// Notify the CPU that multithreading is disabled.
 358     virtual void disableMultiThreading(ThreadID tid, unsigned vpe);
 359     void disableThreads(ThreadID tid, unsigned vpe);
 360
 361     /** Activate a Thread When CPU Resources are Available. */
 362     void activateWhenReady(ThreadID tid);
 363
 364     /** Add or Remove a Thread Context in the CPU. */
 365     void doContextSwitch();
 366
 367     /** Update The Order In Which We Process Threads. */
 368     void updateThreadPriority();
 369
 370     /** Switches a Pipeline Stage to Active. (Unused currently) */
 371     void switchToActive(int stage_idx)
 372     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 373
 374     /** Get the current instruction sequence number, and increment it. */
 375     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 376     { return globalSeqNum[tid]++; }
 377
 378     /** Get the current instruction sequence number, and increment it. */
 379     InstSeqNum nextInstSeqNum(ThreadID tid)
 380     { return globalSeqNum[tid]; }
 381
 382     /** Increment Instruction Sequence Number */
 383     void incrInstSeqNum(ThreadID tid)
 384     { globalSeqNum[tid]++; }
 385
 386     /** Set Instruction Sequence Number */
 387     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 388     {
 389         globalSeqNum[tid] = seq_num;
 390     }
 391
 392     /** Get & Update Next Event Number */
 393     InstSeqNum getNextEventNum()
 394     {
 395         return cpuEventNum++;
 396     }
 397
 398     /** Get instruction asid. */
 399     int getInstAsid(ThreadID tid)
 400     { return thread[tid]->getInstAsid(); }
 401
 402     /** Get data asid. */
 403     int getDataAsid(ThreadID tid)
 404     { return thread[tid]->getDataAsid(); }
 405
 406     /** Register file accessors  */
 407     uint64_t readIntReg(int reg_idx, ThreadID tid);
 408
 409     FloatReg readFloatReg(int reg_idx, ThreadID tid);
 410
 411     FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
 412
 413     void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 414
 415     void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
 416
 417     void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid);
 418
 419     /** Reads a miscellaneous register. */
 420     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 421
 422     /** Reads a misc. register, including any side effects the read
 423      * might have as defined by the architecture.
 424      */
 425     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 426
 427     /** Sets a miscellaneous register. */
 428     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 429                             ThreadID tid = 0);
 430
 431     /** Sets a misc. register, including any side effects the write
 432      * might have as defined by the architecture.
 433      */
 434     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 435
 436     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 437      *  target thread
 438      */
 439     uint64_t readRegOtherThread(unsigned misc_reg,
 440                                 ThreadID tid = InvalidThreadID);
 441
 442     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 443      * target thread
 444      */
 445     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 446                            ThreadID tid);
 447
 448     /** Reads the commit PC of a specific thread. */
 449     uint64_t readPC(ThreadID tid);
 450
 451     /** Sets the commit PC of a specific thread. */
 452     void setPC(Addr new_PC, ThreadID tid);
 453
 454     /** Reads the next PC of a specific thread. */
 455     uint64_t readNextPC(ThreadID tid);
 456
 457     /** Sets the next PC of a specific thread. */
 458     void setNextPC(uint64_t val, ThreadID tid);
 459
 460     /** Reads the next NPC of a specific thread. */
 461     uint64_t readNextNPC(ThreadID tid);
 462
 463     /** Sets the next NPC of a specific thread. */
 464     void setNextNPC(uint64_t val, ThreadID tid);
 465
 466     /** Function to add instruction onto the head of the list of the
 467      *  instructions.  Used when new instructions are fetched.
 468      */
 469     ListIt addInst(DynInstPtr &inst);
 470
 471     /** Function to tell the CPU that an instruction has completed. */
 472     void instDone(DynInstPtr inst, ThreadID tid);
 473
 474     /** Add Instructions to the CPU Remove List*/
 475     void addToRemoveList(DynInstPtr &inst);
 476
 477     /** Remove an instruction from CPU */
 478     void removeInst(DynInstPtr &inst);
 479
 480     /** Remove all instructions younger than the given sequence number. */
 481     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 482
 483     /** Removes the instruction pointed to by the iterator. */
 484     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 485
 486     /** Cleans up all instructions on the instruction remove list. */
 487     void cleanUpRemovedInsts();
 488
 489     /** Cleans up all instructions on the request remove list. */
 490     void cleanUpRemovedReqs();
 491
 492     /** Cleans up all instructions on the CPU event remove list. */
 493     void cleanUpRemovedEvents();
 494
 495     /** Debug function to print all instructions on the list. */
 496     void dumpInsts();
 497
 498     /** Forwards an instruction read to the appropriate data
 499      *  resource (indexes into Resource Pool thru "dataPortIdx")
 500      */
 501     template <class T>
 502     Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
 503
 504     /** Forwards an instruction write. to the appropriate data
 505      *  resource (indexes into Resource Pool thru "dataPortIdx")
 506      */
 507     template <class T>
 508     Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
 509                 uint64_t *write_res = NULL);
 510
 511     /** Forwards an instruction prefetch to the appropriate data
 512      *  resource (indexes into Resource Pool thru "dataPortIdx")
 513      */
 514     void prefetch(DynInstPtr inst);
 515
 516     /** Forwards an instruction writeHint to the appropriate data
 517      *  resource (indexes into Resource Pool thru "dataPortIdx")
 518      */
 519     void writeHint(DynInstPtr inst);
 520
 521     /** Executes a syscall.*/
 522     void syscall(int64_t callnum, ThreadID tid);
 523
 524   public:
 525     /** Per-Thread List of all the instructions in flight. */
 526     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 527
 528     /** List of all the instructions that will be removed at the end of this
 529      *  cycle.
 530      */
 531     std::queue<ListIt> removeList;
 532
 533     /** List of all the resource requests that will be removed at the end of this
 534      *  cycle.
 535      */
 536     std::queue<ResourceRequest*> reqRemoveList;
 537
 538     /** List of all the cpu event requests that will be removed at the end of
 539      *  the current cycle.
 540      */
 541     std::queue<Event*> cpuEventRemoveList;
 542
 543     /** Records if instructions need to be removed this cycle due to
 544      *  being retired or squashed.
 545      */
 546     bool removeInstsThisCycle;
 547
 548     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 549      * execution unit know, NOT to execute while the instruction is active.
 550      */
 551     bool nonSpecInstActive[ThePipeline::MaxThreads];
 552
 553     /** Instruction Seq. Num of current non-speculative instruction. */
 554     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 555
 556     /** Instruction Seq. Num of last instruction squashed in pipeline */
 557     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 558
 559     /** Last Cycle that the CPU squashed instruction end. */
 560     Tick lastSquashCycle[ThePipeline::MaxThreads];
 561
 562     std::list<ThreadID> fetchPriorityList;
 563
 564   protected:
 565     /** Active Threads List */
 566     std::list<ThreadID> activeThreads;
 567
 568     /** Current Threads List */
 569     std::list<ThreadID> currentThreads;
 570
 571     /** Suspended Threads List */
 572     std::list<ThreadID> suspendedThreads;
 573
 574     /** Thread Status Functions (Unused Currently) */
 575     bool isThreadInCPU(ThreadID tid);
 576     bool isThreadActive(ThreadID tid);
 577     bool isThreadSuspended(ThreadID tid);
 578     void addToCurrentThreads(ThreadID tid);
 579     void removeFromCurrentThreads(ThreadID tid);
 580
 581   private:
 582     /** The activity recorder; used to tell if the CPU has any
 583      * activity remaining or if it can go to idle and deschedule
 584      * itself.
 585      */
 586     ActivityRecorder activityRec;
 587
 588   public:
 589     void readFunctional(Addr addr, uint32_t &buffer);
 590
 591     /** Number of Active Threads in the CPU */
 592     ThreadID numActiveThreads() { return activeThreads.size(); }
 593
 594     /** Records that there was time buffer activity this cycle. */
 595     void activityThisCycle() { activityRec.activity(); }
 596
 597     /** Changes a stage's status to active within the activity recorder. */
 598     void activateStage(const int idx)
 599     { activityRec.activateStage(idx); }
 600
 601     /** Changes a stage's status to inactive within the activity recorder. */
 602     void deactivateStage(const int idx)
 603     { activityRec.deactivateStage(idx); }
 604
 605     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 606     void wakeCPU();
 607
 608     /** Gets a free thread id. Use if thread ids change across system. */
 609     ThreadID getFreeTid();
 610
 611     // LL/SC debug functionality
 612     unsigned stCondFails;
 613     unsigned readStCondFailures() { return stCondFails; }
 614     unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
 615
 616     /** Returns a pointer to a thread context. */
 617     ThreadContext *tcBase(ThreadID tid = 0)
 618     {
 619         return thread[tid]->getTC();
 620     }
 621
 622     /** Count the Total Instructions Committed in the CPU. */
 623     virtual Counter totalInstructions() const
 624     {
 625         Counter total(0);
 626
 627         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 628             total += thread[tid]->numInst;
 629
 630         return total;
 631     }
 632
 633     /** The global sequence number counter. */
 634     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 635
 636     /** The global event number counter. */
 637     InstSeqNum cpuEventNum;
 638
 639     /** Counter of how many stages have completed switching out. */
 640     int switchCount;
 641
 642     /** Pointers to all of the threads in the CPU. */
 643     std::vector<Thread *> thread;
 644
 645     /** Pointer to the icache interface. */
 646     MemInterface *icacheInterface;
 647
 648     /** Pointer to the dcache interface. */
 649     MemInterface *dcacheInterface;
 650
 651     /** Whether or not the CPU should defer its registration. */
 652     bool deferRegistration;
 653
 654     /** Per-Stage Instruction Tracing */
 655     bool stageTracing;
 656
 657     /** Is there a context switch pending? */
 658     bool contextSwitch;
 659
 660     /** Threads Scheduled to Enter CPU */
 661     std::list<int> cpuWaitList;
 662
 663     /** The cycle that the CPU was last running, used for statistics. */
 664     Tick lastRunningCycle;
 665
 666     /** Number of Virtual Processors the CPU can process */
 667     unsigned numVirtProcs;
 668
 669     /** Update Thread , used for statistic purposes*/
 670     inline void tickThreadStats();
 671
 672     /** Per-Thread Tick */
 673     Stats::Vector threadCycles;
 674
 675     /** Tick for SMT */
 676     Stats::Scalar smtCycles;
 677
 678     /** Stat for total number of times the CPU is descheduled. */
 679     Stats::Scalar timesIdled;
 680
 681     /** Stat for total number of cycles the CPU spends descheduled. */
 682     Stats::Scalar idleCycles;
 683
 684     /** Stat for the number of committed instructions per thread. */
 685     Stats::Vector committedInsts;
 686
 687     /** Stat for the number of committed instructions per thread. */
 688     Stats::Vector smtCommittedInsts;
 689
 690     /** Stat for the total number of committed instructions. */
 691     Stats::Scalar totalCommittedInsts;
 692
 693     /** Stat for the CPI per thread. */
 694     Stats::Formula cpi;
 695
 696     /** Stat for the SMT-CPI per thread. */
 697     Stats::Formula smtCpi;
 698
 699     /** Stat for the total CPI. */
 700     Stats::Formula totalCpi;
 701
 702     /** Stat for the IPC per thread. */
 703     Stats::Formula ipc;
 704
 705     /** Stat for the total IPC. */
 706     Stats::Formula smtIpc;
 707
 708     /** Stat for the total IPC. */
 709     Stats::Formula totalIpc;
 710 };
 711
 712 #endif // __CPU_O3_CPU_HH__