src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/types.hh"
  43 #include "arch/registers.hh"
  44 #include "base/statistics.hh"
  45 #include "base/timebuf.hh"
  46 #include "base/types.hh"
  47 #include "config/full_system.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/activity.hh"
  50 #include "cpu/base.hh"
  51 #include "cpu/simple_thread.hh"
  52 #include "cpu/inorder/inorder_dyn_inst.hh"
  53 #include "cpu/inorder/pipeline_traits.hh"
  54 #include "cpu/inorder/pipeline_stage.hh"
  55 #include "cpu/inorder/thread_state.hh"
  56 #include "cpu/inorder/reg_dep_map.hh"
  57 #include "cpu/o3/dep_graph.hh"
  58 #include "cpu/o3/rename_map.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83
  84     //DynInstPtr TypeDefs
  85     typedef ThePipeline::DynInstPtr DynInstPtr;
  86     typedef std::list<DynInstPtr>::iterator ListIt;
  87
  88     //TimeBuffer TypeDefs
  89     typedef TimeBuffer<InterStageStruct> StageQueue;
  90
  91     friend class Resource;
  92
  93   public:
  94     /** Constructs a CPU with the given parameters. */
  95     InOrderCPU(Params *params);
  96     /* Destructor */
  97     ~InOrderCPU();
  98
  99     /** CPU ID */
 100     int cpu_id;
 101
 102     // SE Mode ASIDs
 103     ThreadID asid[ThePipeline::MaxThreads];
 104
 105     /** Type of core that this is */
 106     std::string coreType;
 107
 108     // Only need for SE MODE
 109     enum ThreadModel {
 110         Single,
 111         SMT,
 112         SwitchOnCacheMiss
 113     };
 114
 115     ThreadModel threadModel;
 116
 117     int readCpuId() { return cpu_id; }
 118
 119     void setCpuId(int val) { cpu_id = val; }
 120
 121     Params *cpu_params;
 122
 123   public:
 124     enum Status {
 125         Running,
 126         Idle,
 127         Halted,
 128         Blocked,
 129         SwitchedOut
 130     };
 131
 132     /** Overall CPU status. */
 133     Status _status;
 134   private:
 135     /** Define TickEvent for the CPU */
 136     class TickEvent : public Event
 137     {
 138       private:
 139         /** Pointer to the CPU. */
 140         InOrderCPU *cpu;
 141
 142       public:
 143         /** Constructs a tick event. */
 144         TickEvent(InOrderCPU *c);
 145
 146         /** Processes a tick event, calling tick() on the CPU. */
 147         void process();
 148
 149         /** Returns the description of the tick event. */
 150         const char *description();
 151     };
 152
 153     /** The tick event used for scheduling CPU ticks. */
 154     TickEvent tickEvent;
 155
 156     /** Schedule tick event, regardless of its current state. */
 157     void scheduleTickEvent(int delay)
 158     {
 159         if (tickEvent.squashed())
 160           mainEventQueue.reschedule(&tickEvent,
 161                                     nextCycle(curTick + ticks(delay)));
 162         else if (!tickEvent.scheduled())
 163           mainEventQueue.schedule(&tickEvent,
 164                                   nextCycle(curTick + ticks(delay)));
 165     }
 166
 167     /** Unschedule tick event, regardless of its current state. */
 168     void unscheduleTickEvent()
 169     {
 170         if (tickEvent.scheduled())
 171             tickEvent.squash();
 172     }
 173
 174   public:
 175     // List of Events That can be scheduled from
 176     // within the CPU.
 177     // NOTE(1): The Resource Pool also uses this event list
 178     // to schedule events broadcast to all resources interfaces
 179     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 180     // pool event.
 181     enum CPUEventType {
 182         ActivateThread,
 183         ActivateNextReadyThread,
 184         DeactivateThread,
 185         HaltThread,
 186         SuspendThread,
 187         Trap,
 188         InstGraduated,
 189         SquashFromMemStall,
 190         UpdatePCs,
 191         NumCPUEvents
 192     };
 193
 194     static std::string eventNames[NumCPUEvents];
 195
 196     /** Define CPU Event */
 197     class CPUEvent : public Event
 198     {
 199       protected:
 200         InOrderCPU *cpu;
 201
 202       public:
 203         CPUEventType cpuEventType;
 204         ThreadID tid;
 205         DynInstPtr inst;
 206         Fault fault;
 207         unsigned vpe;
 208
 209       public:
 210         /** Constructs a CPU event. */
 211         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 212                  ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
 213
 214         /** Set Type of Event To Be Scheduled */
 215         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 216                       DynInstPtr _inst)
 217         {
 218             fault = _fault;
 219             cpuEventType = e_type;
 220             tid = _tid;
 221             inst = _inst;
 222             vpe = 0;
 223         }
 224
 225         /** Processes a CPU event. */
 226         void process();
 227
 228         /** Returns the description of the CPU event. */
 229         const char *description();
 230
 231         /** Schedule Event */
 232         void scheduleEvent(int delay);
 233
 234         /** Unschedule This Event */
 235         void unscheduleEvent();
 236     };
 237
 238     /** Schedule a CPU Event */
 239     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 240                           DynInstPtr inst, unsigned delay = 0,
 241                           unsigned event_pri_offset = 0);
 242
 243   public:
 244     /** Interface between the CPU and CPU resources. */
 245     ResourcePool *resPool;
 246
 247     /** Instruction used to signify that there is no *real* instruction in
 248         buffer slot */
 249     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 250     DynInstPtr dummyBufferInst;
 251     DynInstPtr dummyReqInst;
 252
 253     /** Used by resources to signify a denied access to a resource. */
 254     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 255
 256     /** Identifies the resource id that identifies a fetch
 257      * access unit.
 258      */
 259     unsigned fetchPortIdx;
 260
 261     /** Identifies the resource id that identifies a ITB       */
 262     unsigned itbIdx;
 263
 264     /** Identifies the resource id that identifies a data
 265      * access unit.
 266      */
 267     unsigned dataPortIdx;
 268
 269     /** Identifies the resource id that identifies a DTB       */
 270     unsigned dtbIdx;
 271
 272     /** The Pipeline Stages for the CPU */
 273     PipelineStage *pipelineStage[ThePipeline::NumStages];
 274
 275     /** Program Counters */
 276     TheISA::PCState pc[ThePipeline::MaxThreads];
 277
 278     /** The Register File for the CPU */
 279     union {
 280         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 281         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 282     } floatRegs;
 283     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 284
 285     /** ISA state */
 286     TheISA::ISA isa[ThePipeline::MaxThreads];
 287
 288     /** Dependency Tracker for Integer & Floating Point Regs */
 289     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 290
 291     /** Global communication structure */
 292     TimeBuffer<TimeStruct> timeBuffer;
 293
 294     /** Communication structure that sits in between pipeline stages */
 295     StageQueue *stageQueue[ThePipeline::NumStages-1];
 296
 297     TheISA::TLB *getITBPtr();
 298     TheISA::TLB *getDTBPtr();
 299
 300   public:
 301
 302     /** Registers statistics. */
 303     void regStats();
 304
 305     /** Ticks CPU, calling tick() on each stage, and checking the overall
 306      *  activity to see if the CPU should deschedule itself.
 307      */
 308     void tick();
 309
 310     /** Initialize the CPU */
 311     void init();
 312
 313     /** Reset State in the CPU */
 314     void reset();
 315
 316     /** Get a Memory Port */
 317     Port* getPort(const std::string &if_name, int idx = 0);
 318
 319 #if FULL_SYSTEM
 320     /** HW return from error interrupt. */
 321     Fault hwrei(ThreadID tid);
 322
 323     bool simPalCheck(int palFunc, ThreadID tid);
 324
 325     /** Returns the Fault for any valid interrupt. */
 326     Fault getInterrupts();
 327
 328     /** Processes any an interrupt fault. */
 329     void processInterrupts(Fault interrupt);
 330
 331     /** Halts the CPU. */
 332     void halt() { panic("Halt not implemented!\n"); }
 333
 334     /** Update the Virt and Phys ports of all ThreadContexts to
 335      * reflect change in memory connections. */
 336     void updateMemPorts();
 337
 338     /** Check if this address is a valid instruction address. */
 339     bool validInstAddr(Addr addr) { return true; }
 340
 341     /** Check if this address is a valid data address. */
 342     bool validDataAddr(Addr addr) { return true; }
 343 #endif
 344
 345     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 346      *  trapCPU() - Traps to handle given fault
 347      */
 348     void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 349     void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
 350
 351     /** Add Thread to Active Threads List. */
 352     void activateContext(ThreadID tid, int delay = 0);
 353     void activateThread(ThreadID tid);
 354     void activateThreadInPipeline(ThreadID tid);
 355
 356     /** Add Thread to Active Threads List. */
 357     void activateNextReadyContext(int delay = 0);
 358     void activateNextReadyThread();
 359
 360     /** Remove from Active Thread List */
 361     void deactivateContext(ThreadID tid, int delay = 0);
 362     void deactivateThread(ThreadID tid);
 363
 364     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 365     void suspendContext(ThreadID tid, int delay = 0);
 366     void suspendThread(ThreadID tid);
 367
 368     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 369      *  Threads List
 370      */
 371     void haltContext(ThreadID tid, int delay = 0);
 372     void haltThread(ThreadID tid);
 373
 374     /** squashFromMemStall() - sets up a squash event
 375      *  squashDueToMemStall() - squashes pipeline
 376      *  @note: maybe squashContext/squashThread would be better?
 377      */
 378     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 379     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 380
 381     void removePipelineStalls(ThreadID tid);
 382     void squashThreadInPipeline(ThreadID tid);
 383     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 384
 385     PipelineStage* getPipeStage(int stage_num);
 386
 387     int
 388     contextId()
 389     {
 390         hack_once("return a bogus context id");
 391         return 0;
 392     }
 393
 394     /** Update The Order In Which We Process Threads. */
 395     void updateThreadPriority();
 396
 397     /** Switches a Pipeline Stage to Active. (Unused currently) */
 398     void switchToActive(int stage_idx)
 399     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 400
 401     /** Get the current instruction sequence number, and increment it. */
 402     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 403     { return globalSeqNum[tid]++; }
 404
 405     /** Get the current instruction sequence number, and increment it. */
 406     InstSeqNum nextInstSeqNum(ThreadID tid)
 407     { return globalSeqNum[tid]; }
 408
 409     /** Increment Instruction Sequence Number */
 410     void incrInstSeqNum(ThreadID tid)
 411     { globalSeqNum[tid]++; }
 412
 413     /** Set Instruction Sequence Number */
 414     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 415     {
 416         globalSeqNum[tid] = seq_num;
 417     }
 418
 419     /** Get & Update Next Event Number */
 420     InstSeqNum getNextEventNum()
 421     {
 422 #ifdef DEBUG
 423         return cpuEventNum++;
 424 #else
 425         return 0;
 426 #endif
 427     }
 428
 429     /** Register file accessors  */
 430     uint64_t readIntReg(int reg_idx, ThreadID tid);
 431
 432     FloatReg readFloatReg(int reg_idx, ThreadID tid);
 433
 434     FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
 435
 436     void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 437
 438     void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
 439
 440     void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid);
 441
 442     /** Reads a miscellaneous register. */
 443     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 444
 445     /** Reads a misc. register, including any side effects the read
 446      * might have as defined by the architecture.
 447      */
 448     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 449
 450     /** Sets a miscellaneous register. */
 451     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 452                             ThreadID tid = 0);
 453
 454     /** Sets a misc. register, including any side effects the write
 455      * might have as defined by the architecture.
 456      */
 457     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 458
 459     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 460      *  target thread
 461      */
 462     uint64_t readRegOtherThread(unsigned misc_reg,
 463                                 ThreadID tid = InvalidThreadID);
 464
 465     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 466      * target thread
 467      */
 468     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 469                            ThreadID tid);
 470
 471     /** Reads the commit PC of a specific thread. */
 472     TheISA::PCState
 473     pcState(ThreadID tid)
 474     {
 475         return pc[tid];
 476     }
 477
 478     /** Sets the commit PC of a specific thread. */
 479     void
 480     pcState(const TheISA::PCState &newPC, ThreadID tid)
 481     {
 482         pc[tid] = newPC;
 483     }
 484
 485     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 486     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 487     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 488
 489     /** Function to add instruction onto the head of the list of the
 490      *  instructions.  Used when new instructions are fetched.
 491      */
 492     ListIt addInst(DynInstPtr &inst);
 493
 494     /** Function to tell the CPU that an instruction has completed. */
 495     void instDone(DynInstPtr inst, ThreadID tid);
 496
 497     /** Add Instructions to the CPU Remove List*/
 498     void addToRemoveList(DynInstPtr &inst);
 499
 500     /** Remove an instruction from CPU */
 501     void removeInst(DynInstPtr &inst);
 502
 503     /** Remove all instructions younger than the given sequence number. */
 504     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 505
 506     /** Removes the instruction pointed to by the iterator. */
 507     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 508
 509     /** Cleans up all instructions on the instruction remove list. */
 510     void cleanUpRemovedInsts();
 511
 512     /** Cleans up all instructions on the request remove list. */
 513     void cleanUpRemovedReqs();
 514
 515     /** Cleans up all instructions on the CPU event remove list. */
 516     void cleanUpRemovedEvents();
 517
 518     /** Debug function to print all instructions on the list. */
 519     void dumpInsts();
 520
 521     /** Forwards an instruction read to the appropriate data
 522      *  resource (indexes into Resource Pool thru "dataPortIdx")
 523      */
 524     Fault read(DynInstPtr inst, Addr addr,
 525                uint8_t *data, unsigned size, unsigned flags);
 526
 527     /** Forwards an instruction write. to the appropriate data
 528      *  resource (indexes into Resource Pool thru "dataPortIdx")
 529      */
 530     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 531                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 532
 533     /** Forwards an instruction prefetch to the appropriate data
 534      *  resource (indexes into Resource Pool thru "dataPortIdx")
 535      */
 536     void prefetch(DynInstPtr inst);
 537
 538     /** Forwards an instruction writeHint to the appropriate data
 539      *  resource (indexes into Resource Pool thru "dataPortIdx")
 540      */
 541     void writeHint(DynInstPtr inst);
 542
 543     /** Executes a syscall.*/
 544     void syscall(int64_t callnum, ThreadID tid);
 545
 546   public:
 547     /** Per-Thread List of all the instructions in flight. */
 548     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 549
 550     /** List of all the instructions that will be removed at the end of this
 551      *  cycle.
 552      */
 553     std::queue<ListIt> removeList;
 554
 555     /** List of all the resource requests that will be removed at the end
 556      *  of this cycle.
 557      */
 558     std::queue<ResourceRequest*> reqRemoveList;
 559
 560     /** List of all the cpu event requests that will be removed at the end of
 561      *  the current cycle.
 562      */
 563     std::queue<Event*> cpuEventRemoveList;
 564
 565     /** Records if instructions need to be removed this cycle due to
 566      *  being retired or squashed.
 567      */
 568     bool removeInstsThisCycle;
 569
 570     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 571      * execution unit know, NOT to execute while the instruction is active.
 572      */
 573     bool nonSpecInstActive[ThePipeline::MaxThreads];
 574
 575     /** Instruction Seq. Num of current non-speculative instruction. */
 576     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 577
 578     /** Instruction Seq. Num of last instruction squashed in pipeline */
 579     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 580
 581     /** Last Cycle that the CPU squashed instruction end. */
 582     Tick lastSquashCycle[ThePipeline::MaxThreads];
 583
 584     std::list<ThreadID> fetchPriorityList;
 585
 586   protected:
 587     /** Active Threads List */
 588     std::list<ThreadID> activeThreads;
 589
 590     /** Ready Threads List */
 591     std::list<ThreadID> readyThreads;
 592
 593     /** Suspended Threads List */
 594     std::list<ThreadID> suspendedThreads;
 595
 596     /** Halted Threads List */
 597     std::list<ThreadID> haltedThreads;
 598
 599     /** Thread Status Functions */
 600     bool isThreadActive(ThreadID tid);
 601     bool isThreadReady(ThreadID tid);
 602     bool isThreadSuspended(ThreadID tid);
 603
 604   private:
 605     /** The activity recorder; used to tell if the CPU has any
 606      * activity remaining or if it can go to idle and deschedule
 607      * itself.
 608      */
 609     ActivityRecorder activityRec;
 610
 611   public:
 612     /** Number of Active Threads in the CPU */
 613     ThreadID numActiveThreads() { return activeThreads.size(); }
 614
 615     /** Thread id of active thread
 616      *  Only used for SwitchOnCacheMiss model.
 617      *  Assumes only 1 thread active
 618      */
 619     ThreadID activeThreadId()
 620     {
 621         if (numActiveThreads() > 0)
 622             return activeThreads.front();
 623         else
 624             return InvalidThreadID;
 625     }
 626
 627
 628     /** Records that there was time buffer activity this cycle. */
 629     void activityThisCycle() { activityRec.activity(); }
 630
 631     /** Changes a stage's status to active within the activity recorder. */
 632     void activateStage(const int idx)
 633     { activityRec.activateStage(idx); }
 634
 635     /** Changes a stage's status to inactive within the activity recorder. */
 636     void deactivateStage(const int idx)
 637     { activityRec.deactivateStage(idx); }
 638
 639     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 640     void wakeCPU();
 641
 642 #if FULL_SYSTEM
 643     virtual void wakeup();
 644 #endif
 645
 646     // LL/SC debug functionality
 647     unsigned stCondFails;
 648
 649     unsigned readStCondFailures()
 650     { return stCondFails; }
 651
 652     unsigned setStCondFailures(unsigned st_fails)
 653     { return stCondFails = st_fails; }
 654
 655     /** Returns a pointer to a thread context. */
 656     ThreadContext *tcBase(ThreadID tid = 0)
 657     {
 658         return thread[tid]->getTC();
 659     }
 660
 661     /** Count the Total Instructions Committed in the CPU. */
 662     virtual Counter totalInstructions() const
 663     {
 664         Counter total(0);
 665
 666         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 667             total += thread[tid]->numInst;
 668
 669         return total;
 670     }
 671
 672 #if FULL_SYSTEM
 673     /** Pointer to the system. */
 674     System *system;
 675
 676     /** Pointer to physical memory. */
 677     PhysicalMemory *physmem;
 678 #endif
 679
 680     /** The global sequence number counter. */
 681     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 682
 683 #ifdef DEBUG
 684     /** The global event number counter. */
 685     InstSeqNum cpuEventNum;
 686
 687     /** Number of resource requests active in CPU **/
 688     unsigned resReqCount;
 689 #endif
 690
 691     /** Counter of how many stages have completed switching out. */
 692     int switchCount;
 693
 694     /** Pointers to all of the threads in the CPU. */
 695     std::vector<Thread *> thread;
 696
 697     /** Pointer to the icache interface. */
 698     MemInterface *icacheInterface;
 699
 700     /** Pointer to the dcache interface. */
 701     MemInterface *dcacheInterface;
 702
 703     /** Whether or not the CPU should defer its registration. */
 704     bool deferRegistration;
 705
 706     /** Per-Stage Instruction Tracing */
 707     bool stageTracing;
 708
 709     /** The cycle that the CPU was last running, used for statistics. */
 710     Tick lastRunningCycle;
 711
 712     void updateContextSwitchStats();
 713     unsigned instsPerSwitch;
 714     Stats::Average instsPerCtxtSwitch;
 715     Stats::Scalar numCtxtSwitches;
 716
 717     /** Update Thread , used for statistic purposes*/
 718     inline void tickThreadStats();
 719
 720     /** Per-Thread Tick */
 721     Stats::Vector threadCycles;
 722
 723     /** Tick for SMT */
 724     Stats::Scalar smtCycles;
 725
 726     /** Stat for total number of times the CPU is descheduled. */
 727     Stats::Scalar timesIdled;
 728
 729     /** Stat for total number of cycles the CPU spends descheduled or no
 730      *  stages active.
 731      */
 732     Stats::Scalar idleCycles;
 733
 734     /** Stat for total number of cycles the CPU is active. */
 735     Stats::Scalar runCycles;
 736
 737     /** Percentage of cycles a stage was active */
 738     Stats::Formula activity;
 739
 740     /** Instruction Mix Stats */
 741     Stats::Scalar comLoads;
 742     Stats::Scalar comStores;
 743     Stats::Scalar comBranches;
 744     Stats::Scalar comNops;
 745     Stats::Scalar comNonSpec;
 746     Stats::Scalar comInts;
 747     Stats::Scalar comFloats;
 748
 749     /** Stat for the number of committed instructions per thread. */
 750     Stats::Vector committedInsts;
 751
 752     /** Stat for the number of committed instructions per thread. */
 753     Stats::Vector smtCommittedInsts;
 754
 755     /** Stat for the total number of committed instructions. */
 756     Stats::Scalar totalCommittedInsts;
 757
 758     /** Stat for the CPI per thread. */
 759     Stats::Formula cpi;
 760
 761     /** Stat for the SMT-CPI per thread. */
 762     Stats::Formula smtCpi;
 763
 764     /** Stat for the total CPI. */
 765     Stats::Formula totalCpi;
 766
 767     /** Stat for the IPC per thread. */
 768     Stats::Formula ipc;
 769
 770     /** Stat for the total IPC. */
 771     Stats::Formula smtIpc;
 772
 773     /** Stat for the total IPC. */
 774     Stats::Formula totalIpc;
 775 };
 776
 777 #endif // __CPU_O3_CPU_HH__