src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2007 MIPS Technologies, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Korey Sewell
  42  *
  43  */
  44
  45 #ifndef __CPU_INORDER_CPU_HH__
  46 #define __CPU_INORDER_CPU_HH__
  47
  48 #include <iostream>
  49 #include <list>
  50 #include <queue>
  51 #include <set>
  52 #include <vector>
  53
  54 #include "arch/isa_traits.hh"
  55 #include "arch/registers.hh"
  56 #include "arch/types.hh"
  57 #include "base/statistics.hh"
  58 #include "base/types.hh"
  59 #include "config/the_isa.hh"
  60 #include "cpu/inorder/inorder_dyn_inst.hh"
  61 #include "cpu/inorder/pipeline_stage.hh"
  62 #include "cpu/inorder/pipeline_traits.hh"
  63 #include "cpu/inorder/reg_dep_map.hh"
  64 #include "cpu/inorder/thread_state.hh"
  65 #include "cpu/o3/dep_graph.hh"
  66 #include "cpu/o3/rename_map.hh"
  67 #include "cpu/activity.hh"
  68 #include "cpu/base.hh"
  69 #include "cpu/reg_class.hh"
  70 #include "cpu/simple_thread.hh"
  71 #include "cpu/timebuf.hh"
  72 #include "mem/packet.hh"
  73 #include "mem/port.hh"
  74 #include "mem/request.hh"
  75 #include "sim/eventq.hh"
  76 #include "sim/process.hh"
  77
  78 class CacheUnit;
  79 class ThreadContext;
  80 class MemInterface;
  81 class MemObject;
  82 class Process;
  83 class ResourcePool;
  84
  85 class InOrderCPU : public BaseCPU
  86 {
  87
  88   protected:
  89     typedef ThePipeline::Params Params;
  90     typedef InOrderThreadState Thread;
  91
  92    //ISA TypeDefs
  93     typedef TheISA::IntReg IntReg;
  94     typedef TheISA::FloatReg FloatReg;
  95     typedef TheISA::FloatRegBits FloatRegBits;
  96     typedef TheISA::MiscReg MiscReg;
  97     typedef TheISA::RegIndex RegIndex;
  98
  99     //DynInstPtr TypeDefs
 100     typedef ThePipeline::DynInstPtr DynInstPtr;
 101     typedef std::list<DynInstPtr>::iterator ListIt;
 102
 103     //TimeBuffer TypeDefs
 104     typedef TimeBuffer<InterStageStruct> StageQueue;
 105
 106     friend class Resource;
 107
 108   public:
 109     /** Constructs a CPU with the given parameters. */
 110     InOrderCPU(Params *params);
 111     /* Destructor */
 112     ~InOrderCPU();
 113
 114     void verifyMemoryMode() const;
 115
 116     /** Return a reference to the data port. */
 117     virtual MasterPort &getDataPort() { return dataPort; }
 118
 119     /** Return a reference to the instruction port. */
 120     virtual MasterPort &getInstPort() { return instPort; }
 121
 122     /** CPU ID */
 123     int cpu_id;
 124
 125     // SE Mode ASIDs
 126     ThreadID asid[ThePipeline::MaxThreads];
 127
 128     /** Type of core that this is */
 129     std::string coreType;
 130
 131     // Only need for SE MODE
 132     enum ThreadModel {
 133         Single,
 134         SMT,
 135         SwitchOnCacheMiss
 136     };
 137
 138     ThreadModel threadModel;
 139
 140     int readCpuId() { return cpu_id; }
 141
 142     void setCpuId(int val) { cpu_id = val; }
 143
 144     Params *cpu_params;
 145
 146   public:
 147     enum Status {
 148         Running,
 149         Idle,
 150         Halted,
 151         Blocked,
 152         SwitchedOut
 153     };
 154
 155     /** Overall CPU status. */
 156     Status _status;
 157   private:
 158
 159     /**
 160      * CachePort class for the in-order CPU, interacting with a
 161      * specific CacheUnit in the pipeline.
 162      */
 163     class CachePort : public MasterPort
 164     {
 165
 166       private:
 167         /** Pointer to cache unit */
 168         CacheUnit *cacheUnit;
 169
 170       public:
 171         /** Default constructor. */
 172         CachePort(CacheUnit *_cacheUnit, const std::string& name);
 173
 174       protected:
 175
 176         /** Timing version of receive */
 177         bool recvTimingResp(PacketPtr pkt);
 178
 179         /** Handles doing a retry of a failed timing request. */
 180         void recvRetry();
 181
 182         /** Ignoring snoops for now. */
 183         void recvTimingSnoopReq(PacketPtr pkt) { }
 184     };
 185
 186     /** Define TickEvent for the CPU */
 187     class TickEvent : public Event
 188     {
 189       private:
 190         /** Pointer to the CPU. */
 191         InOrderCPU *cpu;
 192
 193       public:
 194         /** Constructs a tick event. */
 195         TickEvent(InOrderCPU *c);
 196
 197         /** Processes a tick event, calling tick() on the CPU. */
 198         void process();
 199
 200         /** Returns the description of the tick event. */
 201         const char *description() const;
 202     };
 203
 204     /** The tick event used for scheduling CPU ticks. */
 205     TickEvent tickEvent;
 206
 207     /** Schedule tick event, regardless of its current state. */
 208     void scheduleTickEvent(Cycles delay)
 209     {
 210         assert(!tickEvent.scheduled() || tickEvent.squashed());
 211         reschedule(&tickEvent, clockEdge(delay), true);
 212     }
 213
 214     /** Unschedule tick event, regardless of its current state. */
 215     void unscheduleTickEvent()
 216     {
 217         if (tickEvent.scheduled())
 218             tickEvent.squash();
 219     }
 220
 221   public:
 222     // List of Events That can be scheduled from
 223     // within the CPU.
 224     // NOTE(1): The Resource Pool also uses this event list
 225     // to schedule events broadcast to all resources interfaces
 226     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 227     // pool event.
 228     enum CPUEventType {
 229         ActivateThread,
 230         ActivateNextReadyThread,
 231         DeactivateThread,
 232         HaltThread,
 233         SuspendThread,
 234         Trap,
 235         Syscall,
 236         SquashFromMemStall,
 237         UpdatePCs,
 238         NumCPUEvents
 239     };
 240
 241     static std::string eventNames[NumCPUEvents];
 242
 243     enum CPUEventPri {
 244         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 245         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 246         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 247     };
 248
 249     /** Define CPU Event */
 250     class CPUEvent : public Event
 251     {
 252       protected:
 253         InOrderCPU *cpu;
 254
 255       public:
 256         CPUEventType cpuEventType;
 257         ThreadID tid;
 258         DynInstPtr inst;
 259         Fault fault;
 260         unsigned vpe;
 261         short syscall_num;
 262
 263       public:
 264         /** Constructs a CPU event. */
 265         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 266                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 267
 268         /** Set Type of Event To Be Scheduled */
 269         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 270                       DynInstPtr _inst)
 271         {
 272             fault = _fault;
 273             cpuEventType = e_type;
 274             tid = _tid;
 275             inst = _inst;
 276             vpe = 0;
 277         }
 278
 279         /** Processes a CPU event. */
 280         void process();
 281
 282         /** Returns the description of the CPU event. */
 283         const char *description() const;
 284
 285         /** Schedule Event */
 286         void scheduleEvent(Cycles delay);
 287
 288         /** Unschedule This Event */
 289         void unscheduleEvent();
 290     };
 291
 292     /** Schedule a CPU Event */
 293     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 294                           DynInstPtr inst, Cycles delay = Cycles(0),
 295                           CPUEventPri event_pri = InOrderCPU_Pri);
 296
 297   public:
 298
 299     /** Width (processing bandwidth) of each stage */
 300     int stageWidth;
 301
 302     /** Interface between the CPU and CPU resources. */
 303     ResourcePool *resPool;
 304
 305     /** Instruction used to signify that there is no *real* instruction in
 306         buffer slot */
 307     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 308     DynInstPtr dummyBufferInst;
 309     DynInstPtr dummyReqInst;
 310     DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
 311
 312     /** Used by resources to signify a denied access to a resource. */
 313     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 314
 315     /** The Pipeline Stages for the CPU */
 316     PipelineStage *pipelineStage[ThePipeline::NumStages];
 317
 318     /** Program Counters */
 319     TheISA::PCState pc[ThePipeline::MaxThreads];
 320
 321     /** Last Committed PC */
 322     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 323
 324     /** The Register File for the CPU */
 325     union {
 326         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 327         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 328     } floatRegs;
 329     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 330
 331     /** ISA state */
 332     std::vector<TheISA::ISA *> isa;
 333
 334     /** Dependency Tracker for Integer & Floating Point Regs */
 335     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 336
 337     /** Register Types Used in Dependency Tracking */
 338     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 339
 340     /** Global communication structure */
 341     TimeBuffer<TimeStruct> timeBuffer;
 342
 343     /** Communication structure that sits in between pipeline stages */
 344     StageQueue *stageQueue[ThePipeline::NumStages-1];
 345
 346     TheISA::TLB *getITBPtr();
 347     TheISA::TLB *getDTBPtr();
 348
 349     TheISA::Decoder *getDecoderPtr(unsigned tid);
 350
 351     /** Accessor Type for the SkedCache */
 352     typedef uint32_t SkedID;
 353
 354     /** Cache of Instruction Schedule using the instruction's name as a key */
 355     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 356
 357     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 358
 359     /** Initialized to last iterator in map, signifying a invalid entry
 360         on map searches
 361     */
 362     SkedCacheIt endOfSkedIt;
 363
 364     ThePipeline::RSkedPtr frontEndSked;
 365     ThePipeline::RSkedPtr faultSked;
 366
 367     /** Add a new instruction schedule to the schedule cache */
 368     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 369     {
 370         SkedID sked_id = genSkedID(inst);
 371         assert(skedCache.find(sked_id) == skedCache.end());
 372         skedCache[sked_id] = inst_sked;
 373     }
 374
 375
 376     /** Find a instruction schedule */
 377     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 378     {
 379         SkedID sked_id = genSkedID(inst);
 380         SkedCacheIt lookup_it = skedCache.find(sked_id);
 381
 382         if (lookup_it != endOfSkedIt) {
 383             return (*lookup_it).second;
 384         } else {
 385             return NULL;
 386         }
 387     }
 388
 389     static const uint8_t INST_OPCLASS                       = 26;
 390     static const uint8_t INST_LOAD                          = 25;
 391     static const uint8_t INST_STORE                         = 24;
 392     static const uint8_t INST_CONTROL                       = 23;
 393     static const uint8_t INST_NONSPEC                       = 22;
 394     static const uint8_t INST_DEST_REGS                     = 18;
 395     static const uint8_t INST_SRC_REGS                      = 14;
 396     static const uint8_t INST_SPLIT_DATA                    = 13;
 397
 398     inline SkedID genSkedID(DynInstPtr inst)
 399     {
 400         SkedID id = 0;
 401         id = (inst->opClass() << INST_OPCLASS) |
 402             (inst->isLoad() << INST_LOAD) |
 403             (inst->isStore() << INST_STORE) |
 404             (inst->isControl() << INST_CONTROL) |
 405             (inst->isNonSpeculative() << INST_NONSPEC) |
 406             (inst->numDestRegs() << INST_DEST_REGS) |
 407             (inst->numSrcRegs() << INST_SRC_REGS) |
 408             (inst->splitInst << INST_SPLIT_DATA);
 409         return id;
 410     }
 411
 412     ThePipeline::RSkedPtr createFrontEndSked();
 413     ThePipeline::RSkedPtr createFaultSked();
 414     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 415
 416     class StageScheduler {
 417       private:
 418         ThePipeline::RSkedPtr rsked;
 419         int stageNum;
 420         int nextTaskPriority;
 421
 422       public:
 423         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 424             : rsked(_rsked), stageNum(stage_num),
 425               nextTaskPriority(0)
 426         { }
 427
 428         void needs(int unit, int request) {
 429             rsked->push(new ScheduleEntry(
 430                             stageNum, nextTaskPriority++, unit, request
 431                             ));
 432         }
 433
 434         void needs(int unit, int request, int param) {
 435             rsked->push(new ScheduleEntry(
 436                             stageNum, nextTaskPriority++, unit, request, param
 437                             ));
 438         }
 439     };
 440
 441   private:
 442
 443     /** Data port. Note that it has to appear after the resPool. */
 444     CachePort dataPort;
 445
 446     /** Instruction port. Note that it has to appear after the resPool. */
 447     CachePort instPort;
 448
 449   public:
 450
 451     /** Registers statistics. */
 452     void regStats();
 453
 454     /** Ticks CPU, calling tick() on each stage, and checking the overall
 455      *  activity to see if the CPU should deschedule itself.
 456      */
 457     void tick();
 458
 459     /** Initialize the CPU */
 460     void init();
 461
 462     /** HW return from error interrupt. */
 463     Fault hwrei(ThreadID tid);
 464
 465     bool simPalCheck(int palFunc, ThreadID tid);
 466
 467     void checkForInterrupts();
 468
 469     /** Returns the Fault for any valid interrupt. */
 470     Fault getInterrupts();
 471
 472     /** Processes any an interrupt fault. */
 473     void processInterrupts(Fault interrupt);
 474
 475     /** Halts the CPU. */
 476     void halt() { panic("Halt not implemented!\n"); }
 477
 478     /** Check if this address is a valid instruction address. */
 479     bool validInstAddr(Addr addr) { return true; }
 480
 481     /** Check if this address is a valid data address. */
 482     bool validDataAddr(Addr addr) { return true; }
 483
 484     /** Schedule a syscall on the CPU */
 485     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 486                         Cycles delay = Cycles(0));
 487
 488     /** Executes a syscall.*/
 489     void syscall(int64_t callnum, ThreadID tid);
 490
 491     /** Schedule a trap on the CPU */
 492     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
 493                      Cycles delay = Cycles(0));
 494
 495     /** Perform trap to Handle Given Fault */
 496     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 497
 498     /** Schedule thread activation on the CPU */
 499     void activateContext(ThreadID tid, Cycles delay = Cycles(0));
 500
 501     /** Add Thread to Active Threads List. */
 502     void activateThread(ThreadID tid);
 503
 504     /** Activate Thread In Each Pipeline Stage */
 505     void activateThreadInPipeline(ThreadID tid);
 506
 507     /** Schedule Thread Activation from Ready List */
 508     void activateNextReadyContext(Cycles delay = Cycles(0));
 509
 510     /** Add Thread From Ready List to Active Threads List. */
 511     void activateNextReadyThread();
 512
 513     /** Schedule a thread deactivation on the CPU */
 514     void deactivateContext(ThreadID tid, Cycles delay = Cycles(0));
 515
 516     /** Remove from Active Thread List */
 517     void deactivateThread(ThreadID tid);
 518
 519     /** Schedule a thread suspension on the CPU */
 520   void suspendContext(ThreadID tid);
 521
 522     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 523     void suspendThread(ThreadID tid);
 524
 525     /** Schedule a thread halt on the CPU */
 526     void haltContext(ThreadID tid);
 527
 528     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 529      *  Threads List
 530      */
 531     void haltThread(ThreadID tid);
 532
 533     /** squashFromMemStall() - sets up a squash event
 534      *  squashDueToMemStall() - squashes pipeline
 535      *  @note: maybe squashContext/squashThread would be better?
 536      */
 537     void squashFromMemStall(DynInstPtr inst, ThreadID tid,
 538                             Cycles delay = Cycles(0));
 539     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 540
 541     void removePipelineStalls(ThreadID tid);
 542     void squashThreadInPipeline(ThreadID tid);
 543     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 544
 545     PipelineStage* getPipeStage(int stage_num);
 546
 547     int
 548     contextId()
 549     {
 550         hack_once("return a bogus context id");
 551         return 0;
 552     }
 553
 554     /** Update The Order In Which We Process Threads. */
 555     void updateThreadPriority();
 556
 557     /** Switches a Pipeline Stage to Active. (Unused currently) */
 558     void switchToActive(int stage_idx)
 559     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 560
 561     /** Get the current instruction sequence number, and increment it. */
 562     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 563     { return globalSeqNum[tid]++; }
 564
 565     /** Get the current instruction sequence number, and increment it. */
 566     InstSeqNum nextInstSeqNum(ThreadID tid)
 567     { return globalSeqNum[tid]; }
 568
 569     /** Increment Instruction Sequence Number */
 570     void incrInstSeqNum(ThreadID tid)
 571     { globalSeqNum[tid]++; }
 572
 573     /** Set Instruction Sequence Number */
 574     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 575     {
 576         globalSeqNum[tid] = seq_num;
 577     }
 578
 579     /** Get & Update Next Event Number */
 580     InstSeqNum getNextEventNum()
 581     {
 582 #ifdef DEBUG
 583         return cpuEventNum++;
 584 #else
 585         return 0;
 586 #endif
 587     }
 588
 589     /** Register file accessors  */
 590     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 591
 592     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 593
 594     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 595
 596     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 597
 598     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 599
 600     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 601
 602     RegType inline getRegType(RegIndex reg_idx)
 603     {
 604         switch (regIdxToClass(reg_idx)) {
 605           case IntRegClass:
 606             return IntType;
 607
 608           case FloatRegClass:
 609             return FloatType;
 610
 611           case MiscRegClass:
 612             return MiscType;
 613
 614           default:
 615             panic("register %d out of range\n", reg_idx);
 616         }
 617     }
 618
 619     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 620
 621     /** Reads a miscellaneous register. */
 622     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 623
 624     /** Reads a misc. register, including any side effects the read
 625      * might have as defined by the architecture.
 626      */
 627     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 628
 629     /** Sets a miscellaneous register. */
 630     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 631                             ThreadID tid = 0);
 632
 633     /** Sets a misc. register, including any side effects the write
 634      * might have as defined by the architecture.
 635      */
 636     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 637
 638     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 639      *  target thread
 640      */
 641     uint64_t readRegOtherThread(unsigned misc_reg,
 642                                 ThreadID tid = InvalidThreadID);
 643
 644     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 645      * target thread
 646      */
 647     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 648                            ThreadID tid);
 649
 650     /** Reads the commit PC of a specific thread. */
 651     TheISA::PCState
 652     pcState(ThreadID tid)
 653     {
 654         return pc[tid];
 655     }
 656
 657     /** Sets the commit PC of a specific thread. */
 658     void
 659     pcState(const TheISA::PCState &newPC, ThreadID tid)
 660     {
 661         pc[tid] = newPC;
 662     }
 663
 664     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 665     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 666     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 667
 668     /** Function to add instruction onto the head of the list of the
 669      *  instructions.  Used when new instructions are fetched.
 670      */
 671     ListIt addInst(DynInstPtr inst);
 672
 673     /** Find instruction on instruction list */
 674     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 675
 676     /** Function to tell the CPU that an instruction has completed. */
 677     void instDone(DynInstPtr inst, ThreadID tid);
 678
 679     /** Add Instructions to the CPU Remove List*/
 680     void addToRemoveList(DynInstPtr inst);
 681
 682     /** Remove an instruction from CPU */
 683     void removeInst(DynInstPtr inst);
 684
 685     /** Remove all instructions younger than the given sequence number. */
 686     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 687
 688     /** Removes the instruction pointed to by the iterator. */
 689     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 690
 691     /** Cleans up all instructions on the instruction remove list. */
 692     void cleanUpRemovedInsts();
 693
 694     /** Cleans up all events on the CPU event remove list. */
 695     void cleanUpRemovedEvents();
 696
 697     /** Debug function to print all instructions on the list. */
 698     void dumpInsts();
 699
 700     /** Forwards an instruction read to the appropriate data
 701      *  resource (indexes into Resource Pool thru "dataPortIdx")
 702      */
 703     Fault read(DynInstPtr inst, Addr addr,
 704                uint8_t *data, unsigned size, unsigned flags);
 705
 706     /** Forwards an instruction write. to the appropriate data
 707      *  resource (indexes into Resource Pool thru "dataPortIdx")
 708      */
 709     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 710                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 711
 712   public:
 713     /** Per-Thread List of all the instructions in flight. */
 714     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 715
 716     /** List of all the instructions that will be removed at the end of this
 717      *  cycle.
 718      */
 719     std::queue<ListIt> removeList;
 720
 721     bool trapPending[ThePipeline::MaxThreads];
 722
 723     /** List of all the cpu event requests that will be removed at the end of
 724      *  the current cycle.
 725      */
 726     std::queue<Event*> cpuEventRemoveList;
 727
 728     /** Records if instructions need to be removed this cycle due to
 729      *  being retired or squashed.
 730      */
 731     bool removeInstsThisCycle;
 732
 733     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 734      * execution unit know, NOT to execute while the instruction is active.
 735      */
 736     bool nonSpecInstActive[ThePipeline::MaxThreads];
 737
 738     /** Instruction Seq. Num of current non-speculative instruction. */
 739     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 740
 741     /** Instruction Seq. Num of last instruction squashed in pipeline */
 742     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 743
 744     /** Last Cycle that the CPU squashed instruction end. */
 745     Tick lastSquashCycle[ThePipeline::MaxThreads];
 746
 747     std::list<ThreadID> fetchPriorityList;
 748
 749   protected:
 750     /** Active Threads List */
 751     std::list<ThreadID> activeThreads;
 752
 753     /** Ready Threads List */
 754     std::list<ThreadID> readyThreads;
 755
 756     /** Suspended Threads List */
 757     std::list<ThreadID> suspendedThreads;
 758
 759     /** Halted Threads List */
 760     std::list<ThreadID> haltedThreads;
 761
 762     /** Thread Status Functions */
 763     bool isThreadActive(ThreadID tid);
 764     bool isThreadReady(ThreadID tid);
 765     bool isThreadSuspended(ThreadID tid);
 766
 767   private:
 768     /** The activity recorder; used to tell if the CPU has any
 769      * activity remaining or if it can go to idle and deschedule
 770      * itself.
 771      */
 772     ActivityRecorder activityRec;
 773
 774   public:
 775     /** Number of Active Threads in the CPU */
 776     ThreadID numActiveThreads() { return activeThreads.size(); }
 777
 778     /** Thread id of active thread
 779      *  Only used for SwitchOnCacheMiss model.
 780      *  Assumes only 1 thread active
 781      */
 782     ThreadID activeThreadId()
 783     {
 784         if (numActiveThreads() > 0)
 785             return activeThreads.front();
 786         else
 787             return InvalidThreadID;
 788     }
 789
 790
 791     /** Records that there was time buffer activity this cycle. */
 792     void activityThisCycle() { activityRec.activity(); }
 793
 794     /** Changes a stage's status to active within the activity recorder. */
 795     void activateStage(const int idx)
 796     { activityRec.activateStage(idx); }
 797
 798     /** Changes a stage's status to inactive within the activity recorder. */
 799     void deactivateStage(const int idx)
 800     { activityRec.deactivateStage(idx); }
 801
 802     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 803     void wakeCPU();
 804
 805     virtual void wakeup();
 806
 807     /* LL/SC debug functionality
 808     unsigned stCondFails;
 809
 810     unsigned readStCondFailures()
 811     { return stCondFails; }
 812
 813     unsigned setStCondFailures(unsigned st_fails)
 814     { return stCondFails = st_fails; }
 815     */
 816
 817     /** Returns a pointer to a thread context. */
 818     ThreadContext *tcBase(ThreadID tid = 0)
 819     {
 820         return thread[tid]->getTC();
 821     }
 822
 823     /** Count the Total Instructions Committed in the CPU. */
 824     virtual Counter totalInsts() const
 825     {
 826         Counter total(0);
 827
 828         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 829             total += thread[tid]->numInst;
 830
 831         return total;
 832     }
 833
 834     /** Count the Total Ops Committed in the CPU. */
 835     virtual Counter totalOps() const
 836     {
 837         Counter total(0);
 838
 839         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 840             total += thread[tid]->numOp;
 841
 842         return total;
 843     }
 844
 845     /** Pointer to the system. */
 846     System *system;
 847
 848     /** The global sequence number counter. */
 849     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 850
 851 #ifdef DEBUG
 852     /** The global event number counter. */
 853     InstSeqNum cpuEventNum;
 854
 855     /** Number of resource requests active in CPU **/
 856     unsigned resReqCount;
 857 #endif
 858
 859     Addr lockAddr;
 860
 861     /** Temporary fix for the lock flag, works in the UP case. */
 862     bool lockFlag;
 863
 864     /** Counter of how many stages have completed draining */
 865     int drainCount;
 866
 867     /** Pointers to all of the threads in the CPU. */
 868     std::vector<Thread *> thread;
 869
 870     /** Per-Stage Instruction Tracing */
 871     bool stageTracing;
 872
 873     /** The cycle that the CPU was last running, used for statistics. */
 874     Tick lastRunningCycle;
 875
 876     void updateContextSwitchStats();
 877     unsigned instsPerSwitch;
 878     Stats::Average instsPerCtxtSwitch;
 879     Stats::Scalar numCtxtSwitches;
 880
 881     /** Update Thread , used for statistic purposes*/
 882     inline void tickThreadStats();
 883
 884     /** Per-Thread Tick */
 885     Stats::Vector threadCycles;
 886
 887     /** Tick for SMT */
 888     Stats::Scalar smtCycles;
 889
 890     /** Stat for total number of times the CPU is descheduled. */
 891     Stats::Scalar timesIdled;
 892
 893     /** Stat for total number of cycles the CPU spends descheduled or no
 894      *  stages active.
 895      */
 896     Stats::Scalar idleCycles;
 897
 898     /** Stat for total number of cycles the CPU is active. */
 899     Stats::Scalar runCycles;
 900
 901     /** Percentage of cycles a stage was active */
 902     Stats::Formula activity;
 903
 904     /** Instruction Mix Stats */
 905     Stats::Scalar comLoads;
 906     Stats::Scalar comStores;
 907     Stats::Scalar comBranches;
 908     Stats::Scalar comNops;
 909     Stats::Scalar comNonSpec;
 910     Stats::Scalar comInts;
 911     Stats::Scalar comFloats;
 912
 913     /** Stat for the number of committed instructions per thread. */
 914     Stats::Vector committedInsts;
 915
 916     /** Stat for the number of committed ops per thread. */
 917     Stats::Vector committedOps;
 918
 919     /** Stat for the number of committed instructions per thread. */
 920     Stats::Vector smtCommittedInsts;
 921
 922     /** Stat for the total number of committed instructions. */
 923     Stats::Scalar totalCommittedInsts;
 924
 925     /** Stat for the CPI per thread. */
 926     Stats::Formula cpi;
 927
 928     /** Stat for the SMT-CPI per thread. */
 929     Stats::Formula smtCpi;
 930
 931     /** Stat for the total CPI. */
 932     Stats::Formula totalCpi;
 933
 934     /** Stat for the IPC per thread. */
 935     Stats::Formula ipc;
 936
 937     /** Stat for the total IPC. */
 938     Stats::Formula smtIpc;
 939
 940     /** Stat for the total IPC. */
 941     Stats::Formula totalIpc;
 942 };
 943
 944 #endif // __CPU_O3_CPU_HH__