src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/registers.hh"
  43 #include "arch/types.hh"
  44 #include "base/statistics.hh"
  45 #include "base/types.hh"
  46 #include "config/full_system.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/inorder/inorder_dyn_inst.hh"
  49 #include "cpu/inorder/pipeline_stage.hh"
  50 #include "cpu/inorder/pipeline_traits.hh"
  51 #include "cpu/inorder/reg_dep_map.hh"
  52 #include "cpu/inorder/thread_state.hh"
  53 #include "cpu/o3/dep_graph.hh"
  54 #include "cpu/o3/rename_map.hh"
  55 #include "cpu/activity.hh"
  56 #include "cpu/base.hh"
  57 #include "cpu/simple_thread.hh"
  58 #include "cpu/timebuf.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83     typedef TheISA::RegIndex RegIndex;
  84
  85     //DynInstPtr TypeDefs
  86     typedef ThePipeline::DynInstPtr DynInstPtr;
  87     typedef std::list<DynInstPtr>::iterator ListIt;
  88
  89     //TimeBuffer TypeDefs
  90     typedef TimeBuffer<InterStageStruct> StageQueue;
  91
  92     friend class Resource;
  93
  94   public:
  95     /** Constructs a CPU with the given parameters. */
  96     InOrderCPU(Params *params);
  97     /* Destructor */
  98     ~InOrderCPU();
  99
 100     /** CPU ID */
 101     int cpu_id;
 102
 103     // SE Mode ASIDs
 104     ThreadID asid[ThePipeline::MaxThreads];
 105
 106     /** Type of core that this is */
 107     std::string coreType;
 108
 109     // Only need for SE MODE
 110     enum ThreadModel {
 111         Single,
 112         SMT,
 113         SwitchOnCacheMiss
 114     };
 115
 116     ThreadModel threadModel;
 117
 118     int readCpuId() { return cpu_id; }
 119
 120     void setCpuId(int val) { cpu_id = val; }
 121
 122     Params *cpu_params;
 123
 124   public:
 125     enum Status {
 126         Running,
 127         Idle,
 128         Halted,
 129         Blocked,
 130         SwitchedOut
 131     };
 132
 133     /** Overall CPU status. */
 134     Status _status;
 135   private:
 136     /** Define TickEvent for the CPU */
 137     class TickEvent : public Event
 138     {
 139       private:
 140         /** Pointer to the CPU. */
 141         InOrderCPU *cpu;
 142
 143       public:
 144         /** Constructs a tick event. */
 145         TickEvent(InOrderCPU *c);
 146
 147         /** Processes a tick event, calling tick() on the CPU. */
 148         void process();
 149
 150         /** Returns the description of the tick event. */
 151         const char *description();
 152     };
 153
 154     /** The tick event used for scheduling CPU ticks. */
 155     TickEvent tickEvent;
 156
 157     /** Schedule tick event, regardless of its current state. */
 158     void scheduleTickEvent(int delay)
 159     {
 160         assert(!tickEvent.scheduled() || tickEvent.squashed());
 161         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 162     }
 163
 164     /** Unschedule tick event, regardless of its current state. */
 165     void unscheduleTickEvent()
 166     {
 167         if (tickEvent.scheduled())
 168             tickEvent.squash();
 169     }
 170
 171   public:
 172     // List of Events That can be scheduled from
 173     // within the CPU.
 174     // NOTE(1): The Resource Pool also uses this event list
 175     // to schedule events broadcast to all resources interfaces
 176     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 177     // pool event.
 178     enum CPUEventType {
 179         ActivateThread,
 180         ActivateNextReadyThread,
 181         DeactivateThread,
 182         HaltThread,
 183         SuspendThread,
 184         Trap,
 185         InstGraduated,
 186         SquashFromMemStall,
 187         UpdatePCs,
 188         NumCPUEvents
 189     };
 190
 191     static std::string eventNames[NumCPUEvents];
 192
 193     /** Define CPU Event */
 194     class CPUEvent : public Event
 195     {
 196       protected:
 197         InOrderCPU *cpu;
 198
 199       public:
 200         CPUEventType cpuEventType;
 201         ThreadID tid;
 202         DynInstPtr inst;
 203         Fault fault;
 204         unsigned vpe;
 205
 206       public:
 207         /** Constructs a CPU event. */
 208         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 209                  ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
 210
 211         /** Set Type of Event To Be Scheduled */
 212         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 213                       DynInstPtr _inst)
 214         {
 215             fault = _fault;
 216             cpuEventType = e_type;
 217             tid = _tid;
 218             inst = _inst;
 219             vpe = 0;
 220         }
 221
 222         /** Processes a CPU event. */
 223         void process();
 224
 225         /** Returns the description of the CPU event. */
 226         const char *description();
 227
 228         /** Schedule Event */
 229         void scheduleEvent(int delay);
 230
 231         /** Unschedule This Event */
 232         void unscheduleEvent();
 233     };
 234
 235     /** Schedule a CPU Event */
 236     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 237                           DynInstPtr inst, unsigned delay = 0,
 238                           unsigned event_pri_offset = 0);
 239
 240   public:
 241     /** Interface between the CPU and CPU resources. */
 242     ResourcePool *resPool;
 243
 244     /** Instruction used to signify that there is no *real* instruction in
 245         buffer slot */
 246     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 247     DynInstPtr dummyBufferInst;
 248     DynInstPtr dummyReqInst;
 249
 250     /** Used by resources to signify a denied access to a resource. */
 251     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 252
 253     /** Identifies the resource id that identifies a fetch
 254      * access unit.
 255      */
 256     unsigned fetchPortIdx;
 257
 258     /** Identifies the resource id that identifies a ITB       */
 259     unsigned itbIdx;
 260
 261     /** Identifies the resource id that identifies a data
 262      * access unit.
 263      */
 264     unsigned dataPortIdx;
 265
 266     /** Identifies the resource id that identifies a DTB       */
 267     unsigned dtbIdx;
 268
 269     /** The Pipeline Stages for the CPU */
 270     PipelineStage *pipelineStage[ThePipeline::NumStages];
 271
 272     /** Width (processing bandwidth) of each stage */
 273     int stageWidth;
 274
 275     /** Program Counters */
 276     TheISA::PCState pc[ThePipeline::MaxThreads];
 277
 278     /** Last Committed PC */
 279     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 280
 281     /** The Register File for the CPU */
 282     union {
 283         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 284         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 285     } floatRegs;
 286     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 287
 288     /** ISA state */
 289     TheISA::ISA isa[ThePipeline::MaxThreads];
 290
 291     /** Dependency Tracker for Integer & Floating Point Regs */
 292     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 293
 294     /** Register Types Used in Dependency Tracking */
 295     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 296
 297     /** Global communication structure */
 298     TimeBuffer<TimeStruct> timeBuffer;
 299
 300     /** Communication structure that sits in between pipeline stages */
 301     StageQueue *stageQueue[ThePipeline::NumStages-1];
 302
 303     TheISA::TLB *getITBPtr();
 304     TheISA::TLB *getDTBPtr();
 305
 306     /** Accessor Type for the SkedCache */
 307     typedef uint32_t SkedID;
 308
 309     /** Cache of Instruction Schedule using the instruction's name as a key */
 310     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 311
 312     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 313
 314     /** Initialized to last iterator in map, signifying a invalid entry
 315         on map searches
 316     */
 317     SkedCacheIt endOfSkedIt;
 318
 319     ThePipeline::RSkedPtr frontEndSked;
 320
 321     /** Add a new instruction schedule to the schedule cache */
 322     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 323     {
 324         SkedID sked_id = genSkedID(inst);
 325         assert(skedCache.find(sked_id) == skedCache.end());
 326         skedCache[sked_id] = inst_sked;
 327     }
 328
 329
 330     /** Find a instruction schedule */
 331     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 332     {
 333         SkedID sked_id = genSkedID(inst);
 334         SkedCacheIt lookup_it = skedCache.find(sked_id);
 335
 336         if (lookup_it != endOfSkedIt) {
 337             return (*lookup_it).second;
 338         } else {
 339             return NULL;
 340         }
 341     }
 342
 343     static const uint8_t INST_OPCLASS                       = 26;
 344     static const uint8_t INST_LOAD                          = 25;
 345     static const uint8_t INST_STORE                         = 24;
 346     static const uint8_t INST_CONTROL                       = 23;
 347     static const uint8_t INST_NONSPEC                       = 22;
 348     static const uint8_t INST_DEST_REGS                     = 18;
 349     static const uint8_t INST_SRC_REGS                      = 14;
 350     static const uint8_t INST_SPLIT_DATA                    = 13;
 351
 352     inline SkedID genSkedID(DynInstPtr inst)
 353     {
 354         SkedID id = 0;
 355         id = (inst->opClass() << INST_OPCLASS) |
 356             (inst->isLoad() << INST_LOAD) |
 357             (inst->isStore() << INST_STORE) |
 358             (inst->isControl() << INST_CONTROL) |
 359             (inst->isNonSpeculative() << INST_NONSPEC) |
 360             (inst->numDestRegs() << INST_DEST_REGS) |
 361             (inst->numSrcRegs() << INST_SRC_REGS) |
 362             (inst->splitInst << INST_SPLIT_DATA);
 363         return id;
 364     }
 365
 366     ThePipeline::RSkedPtr createFrontEndSked();
 367     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 368
 369     class StageScheduler {
 370       private:
 371         ThePipeline::RSkedPtr rsked;
 372         int stageNum;
 373         int nextTaskPriority;
 374
 375       public:
 376         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 377             : rsked(_rsked), stageNum(stage_num),
 378               nextTaskPriority(0)
 379         { }
 380
 381         void needs(int unit, int request) {
 382             rsked->push(new ScheduleEntry(
 383                             stageNum, nextTaskPriority++, unit, request
 384                             ));
 385         }
 386
 387         void needs(int unit, int request, int param) {
 388             rsked->push(new ScheduleEntry(
 389                             stageNum, nextTaskPriority++, unit, request, param
 390                             ));
 391         }
 392     };
 393
 394   public:
 395
 396     /** Registers statistics. */
 397     void regStats();
 398
 399     /** Ticks CPU, calling tick() on each stage, and checking the overall
 400      *  activity to see if the CPU should deschedule itself.
 401      */
 402     void tick();
 403
 404     /** Initialize the CPU */
 405     void init();
 406
 407     /** Get a Memory Port */
 408     Port* getPort(const std::string &if_name, int idx = 0);
 409
 410 #if FULL_SYSTEM
 411     /** HW return from error interrupt. */
 412     Fault hwrei(ThreadID tid);
 413
 414     bool simPalCheck(int palFunc, ThreadID tid);
 415
 416     /** Returns the Fault for any valid interrupt. */
 417     Fault getInterrupts();
 418
 419     /** Processes any an interrupt fault. */
 420     void processInterrupts(Fault interrupt);
 421
 422     /** Halts the CPU. */
 423     void halt() { panic("Halt not implemented!\n"); }
 424
 425     /** Update the Virt and Phys ports of all ThreadContexts to
 426      * reflect change in memory connections. */
 427     void updateMemPorts();
 428
 429     /** Check if this address is a valid instruction address. */
 430     bool validInstAddr(Addr addr) { return true; }
 431
 432     /** Check if this address is a valid data address. */
 433     bool validDataAddr(Addr addr) { return true; }
 434 #endif
 435
 436     /** Schedule a trap on the CPU */
 437     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 438
 439     /** Perform trap to Handle Given Fault */
 440     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 441
 442     /** Schedule thread activation on the CPU */
 443     void activateContext(ThreadID tid, int delay = 0);
 444
 445     /** Add Thread to Active Threads List. */
 446     void activateThread(ThreadID tid);
 447
 448     /** Activate Thread In Each Pipeline Stage */
 449     void activateThreadInPipeline(ThreadID tid);
 450
 451     /** Schedule Thread Activation from Ready List */
 452     void activateNextReadyContext(int delay = 0);
 453
 454     /** Add Thread From Ready List to Active Threads List. */
 455     void activateNextReadyThread();
 456
 457     /** Schedule a thread deactivation on the CPU */
 458     void deactivateContext(ThreadID tid, int delay = 0);
 459
 460     /** Remove from Active Thread List */
 461     void deactivateThread(ThreadID tid);
 462
 463     /** Schedule a thread suspension on the CPU */
 464     void suspendContext(ThreadID tid, int delay = 0);
 465
 466     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 467     void suspendThread(ThreadID tid);
 468
 469     /** Schedule a thread halt on the CPU */
 470     void haltContext(ThreadID tid, int delay = 0);
 471
 472     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 473      *  Threads List
 474      */
 475     void haltThread(ThreadID tid);
 476
 477     /** squashFromMemStall() - sets up a squash event
 478      *  squashDueToMemStall() - squashes pipeline
 479      *  @note: maybe squashContext/squashThread would be better?
 480      */
 481     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 482     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 483
 484     void removePipelineStalls(ThreadID tid);
 485     void squashThreadInPipeline(ThreadID tid);
 486     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 487
 488     PipelineStage* getPipeStage(int stage_num);
 489
 490     int
 491     contextId()
 492     {
 493         hack_once("return a bogus context id");
 494         return 0;
 495     }
 496
 497     /** Update The Order In Which We Process Threads. */
 498     void updateThreadPriority();
 499
 500     /** Switches a Pipeline Stage to Active. (Unused currently) */
 501     void switchToActive(int stage_idx)
 502     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 503
 504     /** Get the current instruction sequence number, and increment it. */
 505     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 506     { return globalSeqNum[tid]++; }
 507
 508     /** Get the current instruction sequence number, and increment it. */
 509     InstSeqNum nextInstSeqNum(ThreadID tid)
 510     { return globalSeqNum[tid]; }
 511
 512     /** Increment Instruction Sequence Number */
 513     void incrInstSeqNum(ThreadID tid)
 514     { globalSeqNum[tid]++; }
 515
 516     /** Set Instruction Sequence Number */
 517     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 518     {
 519         globalSeqNum[tid] = seq_num;
 520     }
 521
 522     /** Get & Update Next Event Number */
 523     InstSeqNum getNextEventNum()
 524     {
 525 #ifdef DEBUG
 526         return cpuEventNum++;
 527 #else
 528         return 0;
 529 #endif
 530     }
 531
 532     /** Register file accessors  */
 533     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 534
 535     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 536
 537     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 538
 539     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 540
 541     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 542
 543     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 544
 545     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 546
 547     /** Reads a miscellaneous register. */
 548     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 549
 550     /** Reads a misc. register, including any side effects the read
 551      * might have as defined by the architecture.
 552      */
 553     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 554
 555     /** Sets a miscellaneous register. */
 556     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 557                             ThreadID tid = 0);
 558
 559     /** Sets a misc. register, including any side effects the write
 560      * might have as defined by the architecture.
 561      */
 562     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 563
 564     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 565      *  target thread
 566      */
 567     uint64_t readRegOtherThread(unsigned misc_reg,
 568                                 ThreadID tid = InvalidThreadID);
 569
 570     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 571      * target thread
 572      */
 573     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 574                            ThreadID tid);
 575
 576     /** Reads the commit PC of a specific thread. */
 577     TheISA::PCState
 578     pcState(ThreadID tid)
 579     {
 580         return pc[tid];
 581     }
 582
 583     /** Sets the commit PC of a specific thread. */
 584     void
 585     pcState(const TheISA::PCState &newPC, ThreadID tid)
 586     {
 587         pc[tid] = newPC;
 588     }
 589
 590     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 591     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 592     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 593
 594     /** Function to add instruction onto the head of the list of the
 595      *  instructions.  Used when new instructions are fetched.
 596      */
 597     ListIt addInst(DynInstPtr inst);
 598
 599     /** Find instruction on instruction list */
 600     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 601
 602     /** Function to tell the CPU that an instruction has completed. */
 603     void instDone(DynInstPtr inst, ThreadID tid);
 604
 605     /** Add Instructions to the CPU Remove List*/
 606     void addToRemoveList(DynInstPtr inst);
 607
 608     /** Remove an instruction from CPU */
 609     void removeInst(DynInstPtr inst);
 610
 611     /** Remove all instructions younger than the given sequence number. */
 612     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 613
 614     /** Removes the instruction pointed to by the iterator. */
 615     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 616
 617     /** Cleans up all instructions on the instruction remove list. */
 618     void cleanUpRemovedInsts();
 619
 620     /** Cleans up all events on the CPU event remove list. */
 621     void cleanUpRemovedEvents();
 622
 623     /** Debug function to print all instructions on the list. */
 624     void dumpInsts();
 625
 626     /** Forwards an instruction read to the appropriate data
 627      *  resource (indexes into Resource Pool thru "dataPortIdx")
 628      */
 629     Fault read(DynInstPtr inst, Addr addr,
 630                uint8_t *data, unsigned size, unsigned flags);
 631
 632     /** Forwards an instruction write. to the appropriate data
 633      *  resource (indexes into Resource Pool thru "dataPortIdx")
 634      */
 635     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 636                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 637
 638     /** Executes a syscall.*/
 639     void syscall(int64_t callnum, ThreadID tid);
 640
 641   public:
 642     /** Per-Thread List of all the instructions in flight. */
 643     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 644
 645     /** List of all the instructions that will be removed at the end of this
 646      *  cycle.
 647      */
 648     std::queue<ListIt> removeList;
 649
 650     /** List of all the cpu event requests that will be removed at the end of
 651      *  the current cycle.
 652      */
 653     std::queue<Event*> cpuEventRemoveList;
 654
 655     /** Records if instructions need to be removed this cycle due to
 656      *  being retired or squashed.
 657      */
 658     bool removeInstsThisCycle;
 659
 660     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 661      * execution unit know, NOT to execute while the instruction is active.
 662      */
 663     bool nonSpecInstActive[ThePipeline::MaxThreads];
 664
 665     /** Instruction Seq. Num of current non-speculative instruction. */
 666     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 667
 668     /** Instruction Seq. Num of last instruction squashed in pipeline */
 669     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 670
 671     /** Last Cycle that the CPU squashed instruction end. */
 672     Tick lastSquashCycle[ThePipeline::MaxThreads];
 673
 674     std::list<ThreadID> fetchPriorityList;
 675
 676   protected:
 677     /** Active Threads List */
 678     std::list<ThreadID> activeThreads;
 679
 680     /** Ready Threads List */
 681     std::list<ThreadID> readyThreads;
 682
 683     /** Suspended Threads List */
 684     std::list<ThreadID> suspendedThreads;
 685
 686     /** Halted Threads List */
 687     std::list<ThreadID> haltedThreads;
 688
 689     /** Thread Status Functions */
 690     bool isThreadActive(ThreadID tid);
 691     bool isThreadReady(ThreadID tid);
 692     bool isThreadSuspended(ThreadID tid);
 693
 694   private:
 695     /** The activity recorder; used to tell if the CPU has any
 696      * activity remaining or if it can go to idle and deschedule
 697      * itself.
 698      */
 699     ActivityRecorder activityRec;
 700
 701   public:
 702     /** Number of Active Threads in the CPU */
 703     ThreadID numActiveThreads() { return activeThreads.size(); }
 704
 705     /** Thread id of active thread
 706      *  Only used for SwitchOnCacheMiss model.
 707      *  Assumes only 1 thread active
 708      */
 709     ThreadID activeThreadId()
 710     {
 711         if (numActiveThreads() > 0)
 712             return activeThreads.front();
 713         else
 714             return InvalidThreadID;
 715     }
 716
 717
 718     /** Records that there was time buffer activity this cycle. */
 719     void activityThisCycle() { activityRec.activity(); }
 720
 721     /** Changes a stage's status to active within the activity recorder. */
 722     void activateStage(const int idx)
 723     { activityRec.activateStage(idx); }
 724
 725     /** Changes a stage's status to inactive within the activity recorder. */
 726     void deactivateStage(const int idx)
 727     { activityRec.deactivateStage(idx); }
 728
 729     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 730     void wakeCPU();
 731
 732 #if FULL_SYSTEM
 733     virtual void wakeup();
 734 #endif
 735
 736     // LL/SC debug functionality
 737     unsigned stCondFails;
 738
 739     unsigned readStCondFailures()
 740     { return stCondFails; }
 741
 742     unsigned setStCondFailures(unsigned st_fails)
 743     { return stCondFails = st_fails; }
 744
 745     /** Returns a pointer to a thread context. */
 746     ThreadContext *tcBase(ThreadID tid = 0)
 747     {
 748         return thread[tid]->getTC();
 749     }
 750
 751     /** Count the Total Instructions Committed in the CPU. */
 752     virtual Counter totalInstructions() const
 753     {
 754         Counter total(0);
 755
 756         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 757             total += thread[tid]->numInst;
 758
 759         return total;
 760     }
 761
 762 #if FULL_SYSTEM
 763     /** Pointer to the system. */
 764     System *system;
 765
 766     /** Pointer to physical memory. */
 767     PhysicalMemory *physmem;
 768 #endif
 769
 770     /** The global sequence number counter. */
 771     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 772
 773 #ifdef DEBUG
 774     /** The global event number counter. */
 775     InstSeqNum cpuEventNum;
 776
 777     /** Number of resource requests active in CPU **/
 778     unsigned resReqCount;
 779 #endif
 780
 781     /** Counter of how many stages have completed switching out. */
 782     int switchCount;
 783
 784     /** Pointers to all of the threads in the CPU. */
 785     std::vector<Thread *> thread;
 786
 787     /** Pointer to the icache interface. */
 788     MemInterface *icacheInterface;
 789
 790     /** Pointer to the dcache interface. */
 791     MemInterface *dcacheInterface;
 792
 793     /** Whether or not the CPU should defer its registration. */
 794     bool deferRegistration;
 795
 796     /** Per-Stage Instruction Tracing */
 797     bool stageTracing;
 798
 799     /** The cycle that the CPU was last running, used for statistics. */
 800     Tick lastRunningCycle;
 801
 802     void updateContextSwitchStats();
 803     unsigned instsPerSwitch;
 804     Stats::Average instsPerCtxtSwitch;
 805     Stats::Scalar numCtxtSwitches;
 806
 807     /** Update Thread , used for statistic purposes*/
 808     inline void tickThreadStats();
 809
 810     /** Per-Thread Tick */
 811     Stats::Vector threadCycles;
 812
 813     /** Tick for SMT */
 814     Stats::Scalar smtCycles;
 815
 816     /** Stat for total number of times the CPU is descheduled. */
 817     Stats::Scalar timesIdled;
 818
 819     /** Stat for total number of cycles the CPU spends descheduled or no
 820      *  stages active.
 821      */
 822     Stats::Scalar idleCycles;
 823
 824     /** Stat for total number of cycles the CPU is active. */
 825     Stats::Scalar runCycles;
 826
 827     /** Percentage of cycles a stage was active */
 828     Stats::Formula activity;
 829
 830     /** Instruction Mix Stats */
 831     Stats::Scalar comLoads;
 832     Stats::Scalar comStores;
 833     Stats::Scalar comBranches;
 834     Stats::Scalar comNops;
 835     Stats::Scalar comNonSpec;
 836     Stats::Scalar comInts;
 837     Stats::Scalar comFloats;
 838
 839     /** Stat for the number of committed instructions per thread. */
 840     Stats::Vector committedInsts;
 841
 842     /** Stat for the number of committed instructions per thread. */
 843     Stats::Vector smtCommittedInsts;
 844
 845     /** Stat for the total number of committed instructions. */
 846     Stats::Scalar totalCommittedInsts;
 847
 848     /** Stat for the CPI per thread. */
 849     Stats::Formula cpi;
 850
 851     /** Stat for the SMT-CPI per thread. */
 852     Stats::Formula smtCpi;
 853
 854     /** Stat for the total CPI. */
 855     Stats::Formula totalCpi;
 856
 857     /** Stat for the IPC per thread. */
 858     Stats::Formula ipc;
 859
 860     /** Stat for the total IPC. */
 861     Stats::Formula smtIpc;
 862
 863     /** Stat for the total IPC. */
 864     Stats::Formula totalIpc;
 865 };
 866
 867 #endif // __CPU_O3_CPU_HH__