src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/registers.hh"
  43 #include "arch/types.hh"
  44 #include "base/statistics.hh"
  45 #include "base/types.hh"
  46 #include "config/full_system.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/inorder/inorder_dyn_inst.hh"
  49 #include "cpu/inorder/pipeline_stage.hh"
  50 #include "cpu/inorder/pipeline_traits.hh"
  51 #include "cpu/inorder/reg_dep_map.hh"
  52 #include "cpu/inorder/thread_state.hh"
  53 #include "cpu/o3/dep_graph.hh"
  54 #include "cpu/o3/rename_map.hh"
  55 #include "cpu/activity.hh"
  56 #include "cpu/base.hh"
  57 #include "cpu/simple_thread.hh"
  58 #include "cpu/timebuf.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83     typedef TheISA::RegIndex RegIndex;
  84
  85     //DynInstPtr TypeDefs
  86     typedef ThePipeline::DynInstPtr DynInstPtr;
  87     typedef std::list<DynInstPtr>::iterator ListIt;
  88
  89     //TimeBuffer TypeDefs
  90     typedef TimeBuffer<InterStageStruct> StageQueue;
  91
  92     friend class Resource;
  93
  94   public:
  95     /** Constructs a CPU with the given parameters. */
  96     InOrderCPU(Params *params);
  97     /* Destructor */
  98     ~InOrderCPU();
  99
 100     /** CPU ID */
 101     int cpu_id;
 102
 103     // SE Mode ASIDs
 104     ThreadID asid[ThePipeline::MaxThreads];
 105
 106     /** Type of core that this is */
 107     std::string coreType;
 108
 109     // Only need for SE MODE
 110     enum ThreadModel {
 111         Single,
 112         SMT,
 113         SwitchOnCacheMiss
 114     };
 115
 116     ThreadModel threadModel;
 117
 118     int readCpuId() { return cpu_id; }
 119
 120     void setCpuId(int val) { cpu_id = val; }
 121
 122     Params *cpu_params;
 123
 124   public:
 125     enum Status {
 126         Running,
 127         Idle,
 128         Halted,
 129         Blocked,
 130         SwitchedOut
 131     };
 132
 133     /** Overall CPU status. */
 134     Status _status;
 135   private:
 136     /** Define TickEvent for the CPU */
 137     class TickEvent : public Event
 138     {
 139       private:
 140         /** Pointer to the CPU. */
 141         InOrderCPU *cpu;
 142
 143       public:
 144         /** Constructs a tick event. */
 145         TickEvent(InOrderCPU *c);
 146
 147         /** Processes a tick event, calling tick() on the CPU. */
 148         void process();
 149
 150         /** Returns the description of the tick event. */
 151         const char *description();
 152     };
 153
 154     /** The tick event used for scheduling CPU ticks. */
 155     TickEvent tickEvent;
 156
 157     /** Schedule tick event, regardless of its current state. */
 158     void scheduleTickEvent(int delay)
 159     {
 160         assert(!tickEvent.scheduled() || tickEvent.squashed());
 161         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 162     }
 163
 164     /** Unschedule tick event, regardless of its current state. */
 165     void unscheduleTickEvent()
 166     {
 167         if (tickEvent.scheduled())
 168             tickEvent.squash();
 169     }
 170
 171   public:
 172     // List of Events That can be scheduled from
 173     // within the CPU.
 174     // NOTE(1): The Resource Pool also uses this event list
 175     // to schedule events broadcast to all resources interfaces
 176     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 177     // pool event.
 178     enum CPUEventType {
 179         ActivateThread,
 180         ActivateNextReadyThread,
 181         DeactivateThread,
 182         HaltThread,
 183         SuspendThread,
 184         Trap,
 185         InstGraduated,
 186         SquashFromMemStall,
 187         UpdatePCs,
 188         NumCPUEvents
 189     };
 190
 191     static std::string eventNames[NumCPUEvents];
 192
 193     /** Define CPU Event */
 194     class CPUEvent : public Event
 195     {
 196       protected:
 197         InOrderCPU *cpu;
 198
 199       public:
 200         CPUEventType cpuEventType;
 201         ThreadID tid;
 202         DynInstPtr inst;
 203         Fault fault;
 204         unsigned vpe;
 205
 206       public:
 207         /** Constructs a CPU event. */
 208         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 209                  ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
 210
 211         /** Set Type of Event To Be Scheduled */
 212         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 213                       DynInstPtr _inst)
 214         {
 215             fault = _fault;
 216             cpuEventType = e_type;
 217             tid = _tid;
 218             inst = _inst;
 219             vpe = 0;
 220         }
 221
 222         /** Processes a CPU event. */
 223         void process();
 224
 225         /** Returns the description of the CPU event. */
 226         const char *description();
 227
 228         /** Schedule Event */
 229         void scheduleEvent(int delay);
 230
 231         /** Unschedule This Event */
 232         void unscheduleEvent();
 233     };
 234
 235     /** Schedule a CPU Event */
 236     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 237                           DynInstPtr inst, unsigned delay = 0,
 238                           unsigned event_pri_offset = 0);
 239
 240   public:
 241     /** Interface between the CPU and CPU resources. */
 242     ResourcePool *resPool;
 243
 244     /** Instruction used to signify that there is no *real* instruction in
 245         buffer slot */
 246     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 247     DynInstPtr dummyBufferInst;
 248     DynInstPtr dummyReqInst;
 249
 250     /** Used by resources to signify a denied access to a resource. */
 251     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 252
 253     /** Identifies the resource id that identifies a fetch
 254      * access unit.
 255      */
 256     unsigned fetchPortIdx;
 257
 258     /** Identifies the resource id that identifies a ITB       */
 259     unsigned itbIdx;
 260
 261     /** Identifies the resource id that identifies a data
 262      * access unit.
 263      */
 264     unsigned dataPortIdx;
 265
 266     /** Identifies the resource id that identifies a DTB       */
 267     unsigned dtbIdx;
 268
 269     /** The Pipeline Stages for the CPU */
 270     PipelineStage *pipelineStage[ThePipeline::NumStages];
 271
 272     /** Width (processing bandwidth) of each stage */
 273     int stageWidth;
 274
 275     /** Program Counters */
 276     TheISA::PCState pc[ThePipeline::MaxThreads];
 277
 278     /** The Register File for the CPU */
 279     union {
 280         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 281         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 282     } floatRegs;
 283     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 284
 285     /** ISA state */
 286     TheISA::ISA isa[ThePipeline::MaxThreads];
 287
 288     /** Dependency Tracker for Integer & Floating Point Regs */
 289     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 290
 291     /** Register Types Used in Dependency Tracking */
 292     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 293
 294     /** Global communication structure */
 295     TimeBuffer<TimeStruct> timeBuffer;
 296
 297     /** Communication structure that sits in between pipeline stages */
 298     StageQueue *stageQueue[ThePipeline::NumStages-1];
 299
 300     TheISA::TLB *getITBPtr();
 301     TheISA::TLB *getDTBPtr();
 302
 303     /** Accessor Type for the SkedCache */
 304     typedef uint32_t SkedID;
 305
 306     /** Cache of Instruction Schedule using the instruction's name as a key */
 307     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 308
 309     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 310
 311     /** Initialized to last iterator in map, signifying a invalid entry
 312         on map searches
 313     */
 314     SkedCacheIt endOfSkedIt;
 315
 316     ThePipeline::RSkedPtr frontEndSked;
 317
 318     /** Add a new instruction schedule to the schedule cache */
 319     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 320     {
 321         SkedID sked_id = genSkedID(inst);
 322         assert(skedCache.find(sked_id) == skedCache.end());
 323         skedCache[sked_id] = inst_sked;
 324     }
 325
 326
 327     /** Find a instruction schedule */
 328     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 329     {
 330         SkedID sked_id = genSkedID(inst);
 331         SkedCacheIt lookup_it = skedCache.find(sked_id);
 332
 333         if (lookup_it != endOfSkedIt) {
 334             return (*lookup_it).second;
 335         } else {
 336             return NULL;
 337         }
 338     }
 339
 340     static const uint8_t INST_OPCLASS                       = 26;
 341     static const uint8_t INST_LOAD                          = 25;
 342     static const uint8_t INST_STORE                         = 24;
 343     static const uint8_t INST_CONTROL                       = 23;
 344     static const uint8_t INST_NONSPEC                       = 22;
 345     static const uint8_t INST_DEST_REGS                     = 18;
 346     static const uint8_t INST_SRC_REGS                      = 14;
 347     static const uint8_t INST_SPLIT_DATA                    = 13;
 348
 349     inline SkedID genSkedID(DynInstPtr inst)
 350     {
 351         SkedID id = 0;
 352         id = (inst->opClass() << INST_OPCLASS) |
 353             (inst->isLoad() << INST_LOAD) |
 354             (inst->isStore() << INST_STORE) |
 355             (inst->isControl() << INST_CONTROL) |
 356             (inst->isNonSpeculative() << INST_NONSPEC) |
 357             (inst->numDestRegs() << INST_DEST_REGS) |
 358             (inst->numSrcRegs() << INST_SRC_REGS) |
 359             (inst->splitInst << INST_SPLIT_DATA);
 360         return id;
 361     }
 362
 363     ThePipeline::RSkedPtr createFrontEndSked();
 364     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 365
 366     class StageScheduler {
 367       private:
 368         ThePipeline::RSkedPtr rsked;
 369         int stageNum;
 370         int nextTaskPriority;
 371
 372       public:
 373         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 374             : rsked(_rsked), stageNum(stage_num),
 375               nextTaskPriority(0)
 376         { }
 377
 378         void needs(int unit, int request) {
 379             rsked->push(new ScheduleEntry(
 380                             stageNum, nextTaskPriority++, unit, request
 381                             ));
 382         }
 383
 384         void needs(int unit, int request, int param) {
 385             rsked->push(new ScheduleEntry(
 386                             stageNum, nextTaskPriority++, unit, request, param
 387                             ));
 388         }
 389     };
 390
 391   public:
 392
 393     /** Registers statistics. */
 394     void regStats();
 395
 396     /** Ticks CPU, calling tick() on each stage, and checking the overall
 397      *  activity to see if the CPU should deschedule itself.
 398      */
 399     void tick();
 400
 401     /** Initialize the CPU */
 402     void init();
 403
 404     /** Get a Memory Port */
 405     Port* getPort(const std::string &if_name, int idx = 0);
 406
 407 #if FULL_SYSTEM
 408     /** HW return from error interrupt. */
 409     Fault hwrei(ThreadID tid);
 410
 411     bool simPalCheck(int palFunc, ThreadID tid);
 412
 413     /** Returns the Fault for any valid interrupt. */
 414     Fault getInterrupts();
 415
 416     /** Processes any an interrupt fault. */
 417     void processInterrupts(Fault interrupt);
 418
 419     /** Halts the CPU. */
 420     void halt() { panic("Halt not implemented!\n"); }
 421
 422     /** Update the Virt and Phys ports of all ThreadContexts to
 423      * reflect change in memory connections. */
 424     void updateMemPorts();
 425
 426     /** Check if this address is a valid instruction address. */
 427     bool validInstAddr(Addr addr) { return true; }
 428
 429     /** Check if this address is a valid data address. */
 430     bool validDataAddr(Addr addr) { return true; }
 431 #endif
 432
 433     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 434      *  trapCPU() - Traps to handle given fault
 435      */
 436     void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 437     void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
 438
 439     /** Add Thread to Active Threads List. */
 440     void activateContext(ThreadID tid, int delay = 0);
 441     void activateThread(ThreadID tid);
 442     void activateThreadInPipeline(ThreadID tid);
 443
 444     /** Add Thread to Active Threads List. */
 445     void activateNextReadyContext(int delay = 0);
 446     void activateNextReadyThread();
 447
 448     /** Remove from Active Thread List */
 449     void deactivateContext(ThreadID tid, int delay = 0);
 450     void deactivateThread(ThreadID tid);
 451
 452     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 453     void suspendContext(ThreadID tid, int delay = 0);
 454     void suspendThread(ThreadID tid);
 455
 456     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 457      *  Threads List
 458      */
 459     void haltContext(ThreadID tid, int delay = 0);
 460     void haltThread(ThreadID tid);
 461
 462     /** squashFromMemStall() - sets up a squash event
 463      *  squashDueToMemStall() - squashes pipeline
 464      *  @note: maybe squashContext/squashThread would be better?
 465      */
 466     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 467     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 468
 469     void removePipelineStalls(ThreadID tid);
 470     void squashThreadInPipeline(ThreadID tid);
 471     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 472
 473     PipelineStage* getPipeStage(int stage_num);
 474
 475     int
 476     contextId()
 477     {
 478         hack_once("return a bogus context id");
 479         return 0;
 480     }
 481
 482     /** Update The Order In Which We Process Threads. */
 483     void updateThreadPriority();
 484
 485     /** Switches a Pipeline Stage to Active. (Unused currently) */
 486     void switchToActive(int stage_idx)
 487     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 488
 489     /** Get the current instruction sequence number, and increment it. */
 490     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 491     { return globalSeqNum[tid]++; }
 492
 493     /** Get the current instruction sequence number, and increment it. */
 494     InstSeqNum nextInstSeqNum(ThreadID tid)
 495     { return globalSeqNum[tid]; }
 496
 497     /** Increment Instruction Sequence Number */
 498     void incrInstSeqNum(ThreadID tid)
 499     { globalSeqNum[tid]++; }
 500
 501     /** Set Instruction Sequence Number */
 502     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 503     {
 504         globalSeqNum[tid] = seq_num;
 505     }
 506
 507     /** Get & Update Next Event Number */
 508     InstSeqNum getNextEventNum()
 509     {
 510 #ifdef DEBUG
 511         return cpuEventNum++;
 512 #else
 513         return 0;
 514 #endif
 515     }
 516
 517     /** Register file accessors  */
 518     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 519
 520     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 521
 522     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 523
 524     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 525
 526     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 527
 528     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 529
 530     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 531
 532     /** Reads a miscellaneous register. */
 533     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 534
 535     /** Reads a misc. register, including any side effects the read
 536      * might have as defined by the architecture.
 537      */
 538     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 539
 540     /** Sets a miscellaneous register. */
 541     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 542                             ThreadID tid = 0);
 543
 544     /** Sets a misc. register, including any side effects the write
 545      * might have as defined by the architecture.
 546      */
 547     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 548
 549     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 550      *  target thread
 551      */
 552     uint64_t readRegOtherThread(unsigned misc_reg,
 553                                 ThreadID tid = InvalidThreadID);
 554
 555     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 556      * target thread
 557      */
 558     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 559                            ThreadID tid);
 560
 561     /** Reads the commit PC of a specific thread. */
 562     TheISA::PCState
 563     pcState(ThreadID tid)
 564     {
 565         return pc[tid];
 566     }
 567
 568     /** Sets the commit PC of a specific thread. */
 569     void
 570     pcState(const TheISA::PCState &newPC, ThreadID tid)
 571     {
 572         pc[tid] = newPC;
 573     }
 574
 575     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 576     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 577     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 578
 579     /** Function to add instruction onto the head of the list of the
 580      *  instructions.  Used when new instructions are fetched.
 581      */
 582     ListIt addInst(DynInstPtr inst);
 583
 584     /** Function to tell the CPU that an instruction has completed. */
 585     void instDone(DynInstPtr inst, ThreadID tid);
 586
 587     /** Add Instructions to the CPU Remove List*/
 588     void addToRemoveList(DynInstPtr inst);
 589
 590     /** Remove an instruction from CPU */
 591     void removeInst(DynInstPtr inst);
 592
 593     /** Remove all instructions younger than the given sequence number. */
 594     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 595
 596     /** Removes the instruction pointed to by the iterator. */
 597     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 598
 599     /** Cleans up all instructions on the instruction remove list. */
 600     void cleanUpRemovedInsts();
 601
 602     /** Cleans up all events on the CPU event remove list. */
 603     void cleanUpRemovedEvents();
 604
 605     /** Debug function to print all instructions on the list. */
 606     void dumpInsts();
 607
 608     /** Forwards an instruction read to the appropriate data
 609      *  resource (indexes into Resource Pool thru "dataPortIdx")
 610      */
 611     Fault read(DynInstPtr inst, Addr addr,
 612                uint8_t *data, unsigned size, unsigned flags);
 613
 614     /** Forwards an instruction write. to the appropriate data
 615      *  resource (indexes into Resource Pool thru "dataPortIdx")
 616      */
 617     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 618                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 619
 620     /** Executes a syscall.*/
 621     void syscall(int64_t callnum, ThreadID tid);
 622
 623   public:
 624     /** Per-Thread List of all the instructions in flight. */
 625     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 626
 627     /** List of all the instructions that will be removed at the end of this
 628      *  cycle.
 629      */
 630     std::queue<ListIt> removeList;
 631
 632     /** List of all the cpu event requests that will be removed at the end of
 633      *  the current cycle.
 634      */
 635     std::queue<Event*> cpuEventRemoveList;
 636
 637     /** Records if instructions need to be removed this cycle due to
 638      *  being retired or squashed.
 639      */
 640     bool removeInstsThisCycle;
 641
 642     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 643      * execution unit know, NOT to execute while the instruction is active.
 644      */
 645     bool nonSpecInstActive[ThePipeline::MaxThreads];
 646
 647     /** Instruction Seq. Num of current non-speculative instruction. */
 648     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 649
 650     /** Instruction Seq. Num of last instruction squashed in pipeline */
 651     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 652
 653     /** Last Cycle that the CPU squashed instruction end. */
 654     Tick lastSquashCycle[ThePipeline::MaxThreads];
 655
 656     std::list<ThreadID> fetchPriorityList;
 657
 658   protected:
 659     /** Active Threads List */
 660     std::list<ThreadID> activeThreads;
 661
 662     /** Ready Threads List */
 663     std::list<ThreadID> readyThreads;
 664
 665     /** Suspended Threads List */
 666     std::list<ThreadID> suspendedThreads;
 667
 668     /** Halted Threads List */
 669     std::list<ThreadID> haltedThreads;
 670
 671     /** Thread Status Functions */
 672     bool isThreadActive(ThreadID tid);
 673     bool isThreadReady(ThreadID tid);
 674     bool isThreadSuspended(ThreadID tid);
 675
 676   private:
 677     /** The activity recorder; used to tell if the CPU has any
 678      * activity remaining or if it can go to idle and deschedule
 679      * itself.
 680      */
 681     ActivityRecorder activityRec;
 682
 683   public:
 684     /** Number of Active Threads in the CPU */
 685     ThreadID numActiveThreads() { return activeThreads.size(); }
 686
 687     /** Thread id of active thread
 688      *  Only used for SwitchOnCacheMiss model.
 689      *  Assumes only 1 thread active
 690      */
 691     ThreadID activeThreadId()
 692     {
 693         if (numActiveThreads() > 0)
 694             return activeThreads.front();
 695         else
 696             return InvalidThreadID;
 697     }
 698
 699
 700     /** Records that there was time buffer activity this cycle. */
 701     void activityThisCycle() { activityRec.activity(); }
 702
 703     /** Changes a stage's status to active within the activity recorder. */
 704     void activateStage(const int idx)
 705     { activityRec.activateStage(idx); }
 706
 707     /** Changes a stage's status to inactive within the activity recorder. */
 708     void deactivateStage(const int idx)
 709     { activityRec.deactivateStage(idx); }
 710
 711     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 712     void wakeCPU();
 713
 714 #if FULL_SYSTEM
 715     virtual void wakeup();
 716 #endif
 717
 718     // LL/SC debug functionality
 719     unsigned stCondFails;
 720
 721     unsigned readStCondFailures()
 722     { return stCondFails; }
 723
 724     unsigned setStCondFailures(unsigned st_fails)
 725     { return stCondFails = st_fails; }
 726
 727     /** Returns a pointer to a thread context. */
 728     ThreadContext *tcBase(ThreadID tid = 0)
 729     {
 730         return thread[tid]->getTC();
 731     }
 732
 733     /** Count the Total Instructions Committed in the CPU. */
 734     virtual Counter totalInstructions() const
 735     {
 736         Counter total(0);
 737
 738         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 739             total += thread[tid]->numInst;
 740
 741         return total;
 742     }
 743
 744 #if FULL_SYSTEM
 745     /** Pointer to the system. */
 746     System *system;
 747
 748     /** Pointer to physical memory. */
 749     PhysicalMemory *physmem;
 750 #endif
 751
 752     /** The global sequence number counter. */
 753     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 754
 755 #ifdef DEBUG
 756     /** The global event number counter. */
 757     InstSeqNum cpuEventNum;
 758
 759     /** Number of resource requests active in CPU **/
 760     unsigned resReqCount;
 761 #endif
 762
 763     /** Counter of how many stages have completed switching out. */
 764     int switchCount;
 765
 766     /** Pointers to all of the threads in the CPU. */
 767     std::vector<Thread *> thread;
 768
 769     /** Pointer to the icache interface. */
 770     MemInterface *icacheInterface;
 771
 772     /** Pointer to the dcache interface. */
 773     MemInterface *dcacheInterface;
 774
 775     /** Whether or not the CPU should defer its registration. */
 776     bool deferRegistration;
 777
 778     /** Per-Stage Instruction Tracing */
 779     bool stageTracing;
 780
 781     /** The cycle that the CPU was last running, used for statistics. */
 782     Tick lastRunningCycle;
 783
 784     void updateContextSwitchStats();
 785     unsigned instsPerSwitch;
 786     Stats::Average instsPerCtxtSwitch;
 787     Stats::Scalar numCtxtSwitches;
 788
 789     /** Update Thread , used for statistic purposes*/
 790     inline void tickThreadStats();
 791
 792     /** Per-Thread Tick */
 793     Stats::Vector threadCycles;
 794
 795     /** Tick for SMT */
 796     Stats::Scalar smtCycles;
 797
 798     /** Stat for total number of times the CPU is descheduled. */
 799     Stats::Scalar timesIdled;
 800
 801     /** Stat for total number of cycles the CPU spends descheduled or no
 802      *  stages active.
 803      */
 804     Stats::Scalar idleCycles;
 805
 806     /** Stat for total number of cycles the CPU is active. */
 807     Stats::Scalar runCycles;
 808
 809     /** Percentage of cycles a stage was active */
 810     Stats::Formula activity;
 811
 812     /** Instruction Mix Stats */
 813     Stats::Scalar comLoads;
 814     Stats::Scalar comStores;
 815     Stats::Scalar comBranches;
 816     Stats::Scalar comNops;
 817     Stats::Scalar comNonSpec;
 818     Stats::Scalar comInts;
 819     Stats::Scalar comFloats;
 820
 821     /** Stat for the number of committed instructions per thread. */
 822     Stats::Vector committedInsts;
 823
 824     /** Stat for the number of committed instructions per thread. */
 825     Stats::Vector smtCommittedInsts;
 826
 827     /** Stat for the total number of committed instructions. */
 828     Stats::Scalar totalCommittedInsts;
 829
 830     /** Stat for the CPI per thread. */
 831     Stats::Formula cpi;
 832
 833     /** Stat for the SMT-CPI per thread. */
 834     Stats::Formula smtCpi;
 835
 836     /** Stat for the total CPI. */
 837     Stats::Formula totalCpi;
 838
 839     /** Stat for the IPC per thread. */
 840     Stats::Formula ipc;
 841
 842     /** Stat for the total IPC. */
 843     Stats::Formula smtIpc;
 844
 845     /** Stat for the total IPC. */
 846     Stats::Formula totalIpc;
 847 };
 848
 849 #endif // __CPU_O3_CPU_HH__