src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 MIPS Technologies, Inc.
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Korey Sewell
  41  *
  42  */
  43
  44 #ifndef __CPU_INORDER_CPU_HH__
  45 #define __CPU_INORDER_CPU_HH__
  46
  47 #include <iostream>
  48 #include <list>
  49 #include <queue>
  50 #include <set>
  51 #include <vector>
  52
  53 #include "arch/isa_traits.hh"
  54 #include "arch/registers.hh"
  55 #include "arch/types.hh"
  56 #include "base/statistics.hh"
  57 #include "base/types.hh"
  58 #include "config/the_isa.hh"
  59 #include "cpu/inorder/inorder_dyn_inst.hh"
  60 #include "cpu/inorder/pipeline_stage.hh"
  61 #include "cpu/inorder/pipeline_traits.hh"
  62 #include "cpu/inorder/reg_dep_map.hh"
  63 #include "cpu/inorder/thread_state.hh"
  64 #include "cpu/o3/dep_graph.hh"
  65 #include "cpu/o3/rename_map.hh"
  66 #include "cpu/activity.hh"
  67 #include "cpu/base.hh"
  68 #include "cpu/simple_thread.hh"
  69 #include "cpu/timebuf.hh"
  70 #include "mem/packet.hh"
  71 #include "mem/port.hh"
  72 #include "mem/request.hh"
  73 #include "sim/eventq.hh"
  74 #include "sim/process.hh"
  75
  76 class CacheUnit;
  77 class ThreadContext;
  78 class MemInterface;
  79 class MemObject;
  80 class Process;
  81 class ResourcePool;
  82
  83 class InOrderCPU : public BaseCPU
  84 {
  85
  86   protected:
  87     typedef ThePipeline::Params Params;
  88     typedef InOrderThreadState Thread;
  89
  90    //ISA TypeDefs
  91     typedef TheISA::IntReg IntReg;
  92     typedef TheISA::FloatReg FloatReg;
  93     typedef TheISA::FloatRegBits FloatRegBits;
  94     typedef TheISA::MiscReg MiscReg;
  95     typedef TheISA::RegIndex RegIndex;
  96
  97     //DynInstPtr TypeDefs
  98     typedef ThePipeline::DynInstPtr DynInstPtr;
  99     typedef std::list<DynInstPtr>::iterator ListIt;
 100
 101     //TimeBuffer TypeDefs
 102     typedef TimeBuffer<InterStageStruct> StageQueue;
 103
 104     friend class Resource;
 105
 106   public:
 107     /** Constructs a CPU with the given parameters. */
 108     InOrderCPU(Params *params);
 109     /* Destructor */
 110     ~InOrderCPU();
 111
 112     /** Return a reference to the data port. */
 113     virtual CpuPort &getDataPort() { return dataPort; }
 114
 115     /** Return a reference to the instruction port. */
 116     virtual CpuPort &getInstPort() { return instPort; }
 117
 118     /** CPU ID */
 119     int cpu_id;
 120
 121     // SE Mode ASIDs
 122     ThreadID asid[ThePipeline::MaxThreads];
 123
 124     /** Type of core that this is */
 125     std::string coreType;
 126
 127     // Only need for SE MODE
 128     enum ThreadModel {
 129         Single,
 130         SMT,
 131         SwitchOnCacheMiss
 132     };
 133
 134     ThreadModel threadModel;
 135
 136     int readCpuId() { return cpu_id; }
 137
 138     void setCpuId(int val) { cpu_id = val; }
 139
 140     Params *cpu_params;
 141
 142   public:
 143     enum Status {
 144         Running,
 145         Idle,
 146         Halted,
 147         Blocked,
 148         SwitchedOut
 149     };
 150
 151     /** Overall CPU status. */
 152     Status _status;
 153   private:
 154
 155     /**
 156      * CachePort class for the in-order CPU, interacting with a
 157      * specific CacheUnit in the pipeline.
 158      */
 159     class CachePort : public CpuPort
 160     {
 161
 162       private:
 163         /** Pointer to cache unit */
 164         CacheUnit *cacheUnit;
 165
 166       public:
 167         /** Default constructor. */
 168         CachePort(CacheUnit *_cacheUnit);
 169
 170       protected:
 171
 172         /** Timing version of receive */
 173         bool recvTiming(PacketPtr pkt);
 174
 175         /** Handles doing a retry of a failed timing request. */
 176         void recvRetry();
 177     };
 178
 179     /** Define TickEvent for the CPU */
 180     class TickEvent : public Event
 181     {
 182       private:
 183         /** Pointer to the CPU. */
 184         InOrderCPU *cpu;
 185
 186       public:
 187         /** Constructs a tick event. */
 188         TickEvent(InOrderCPU *c);
 189
 190         /** Processes a tick event, calling tick() on the CPU. */
 191         void process();
 192
 193         /** Returns the description of the tick event. */
 194         const char *description() const;
 195     };
 196
 197     /** The tick event used for scheduling CPU ticks. */
 198     TickEvent tickEvent;
 199
 200     /** Schedule tick event, regardless of its current state. */
 201     void scheduleTickEvent(int delay)
 202     {
 203         assert(!tickEvent.scheduled() || tickEvent.squashed());
 204         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 205     }
 206
 207     /** Unschedule tick event, regardless of its current state. */
 208     void unscheduleTickEvent()
 209     {
 210         if (tickEvent.scheduled())
 211             tickEvent.squash();
 212     }
 213
 214   public:
 215     // List of Events That can be scheduled from
 216     // within the CPU.
 217     // NOTE(1): The Resource Pool also uses this event list
 218     // to schedule events broadcast to all resources interfaces
 219     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 220     // pool event.
 221     enum CPUEventType {
 222         ActivateThread,
 223         ActivateNextReadyThread,
 224         DeactivateThread,
 225         HaltThread,
 226         SuspendThread,
 227         Trap,
 228         Syscall,
 229         SquashFromMemStall,
 230         UpdatePCs,
 231         NumCPUEvents
 232     };
 233
 234     static std::string eventNames[NumCPUEvents];
 235
 236     enum CPUEventPri {
 237         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 238         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 239         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 240     };
 241
 242     /** Define CPU Event */
 243     class CPUEvent : public Event
 244     {
 245       protected:
 246         InOrderCPU *cpu;
 247
 248       public:
 249         CPUEventType cpuEventType;
 250         ThreadID tid;
 251         DynInstPtr inst;
 252         Fault fault;
 253         unsigned vpe;
 254         short syscall_num;
 255
 256       public:
 257         /** Constructs a CPU event. */
 258         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 259                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 260
 261         /** Set Type of Event To Be Scheduled */
 262         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 263                       DynInstPtr _inst)
 264         {
 265             fault = _fault;
 266             cpuEventType = e_type;
 267             tid = _tid;
 268             inst = _inst;
 269             vpe = 0;
 270         }
 271
 272         /** Processes a CPU event. */
 273         void process();
 274
 275         /** Returns the description of the CPU event. */
 276         const char *description() const;
 277
 278         /** Schedule Event */
 279         void scheduleEvent(int delay);
 280
 281         /** Unschedule This Event */
 282         void unscheduleEvent();
 283     };
 284
 285     /** Schedule a CPU Event */
 286     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 287                           DynInstPtr inst, unsigned delay = 0,
 288                           CPUEventPri event_pri = InOrderCPU_Pri);
 289
 290   public:
 291
 292     /** Width (processing bandwidth) of each stage */
 293     int stageWidth;
 294
 295     /** Interface between the CPU and CPU resources. */
 296     ResourcePool *resPool;
 297
 298     /** Instruction used to signify that there is no *real* instruction in
 299         buffer slot */
 300     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 301     DynInstPtr dummyBufferInst;
 302     DynInstPtr dummyReqInst;
 303     DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
 304
 305     /** Used by resources to signify a denied access to a resource. */
 306     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 307
 308     /** The Pipeline Stages for the CPU */
 309     PipelineStage *pipelineStage[ThePipeline::NumStages];
 310
 311     /** Program Counters */
 312     TheISA::PCState pc[ThePipeline::MaxThreads];
 313
 314     /** Last Committed PC */
 315     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 316
 317     /** The Register File for the CPU */
 318     union {
 319         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 320         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 321     } floatRegs;
 322     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 323
 324     /** ISA state */
 325     TheISA::ISA isa[ThePipeline::MaxThreads];
 326
 327     /** Dependency Tracker for Integer & Floating Point Regs */
 328     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 329
 330     /** Register Types Used in Dependency Tracking */
 331     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 332
 333     /** Global communication structure */
 334     TimeBuffer<TimeStruct> timeBuffer;
 335
 336     /** Communication structure that sits in between pipeline stages */
 337     StageQueue *stageQueue[ThePipeline::NumStages-1];
 338
 339     TheISA::TLB *getITBPtr();
 340     TheISA::TLB *getDTBPtr();
 341
 342     Decoder *getDecoderPtr();
 343
 344     /** Accessor Type for the SkedCache */
 345     typedef uint32_t SkedID;
 346
 347     /** Cache of Instruction Schedule using the instruction's name as a key */
 348     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 349
 350     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 351
 352     /** Initialized to last iterator in map, signifying a invalid entry
 353         on map searches
 354     */
 355     SkedCacheIt endOfSkedIt;
 356
 357     ThePipeline::RSkedPtr frontEndSked;
 358     ThePipeline::RSkedPtr faultSked;
 359
 360     /** Add a new instruction schedule to the schedule cache */
 361     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 362     {
 363         SkedID sked_id = genSkedID(inst);
 364         assert(skedCache.find(sked_id) == skedCache.end());
 365         skedCache[sked_id] = inst_sked;
 366     }
 367
 368
 369     /** Find a instruction schedule */
 370     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 371     {
 372         SkedID sked_id = genSkedID(inst);
 373         SkedCacheIt lookup_it = skedCache.find(sked_id);
 374
 375         if (lookup_it != endOfSkedIt) {
 376             return (*lookup_it).second;
 377         } else {
 378             return NULL;
 379         }
 380     }
 381
 382     static const uint8_t INST_OPCLASS                       = 26;
 383     static const uint8_t INST_LOAD                          = 25;
 384     static const uint8_t INST_STORE                         = 24;
 385     static const uint8_t INST_CONTROL                       = 23;
 386     static const uint8_t INST_NONSPEC                       = 22;
 387     static const uint8_t INST_DEST_REGS                     = 18;
 388     static const uint8_t INST_SRC_REGS                      = 14;
 389     static const uint8_t INST_SPLIT_DATA                    = 13;
 390
 391     inline SkedID genSkedID(DynInstPtr inst)
 392     {
 393         SkedID id = 0;
 394         id = (inst->opClass() << INST_OPCLASS) |
 395             (inst->isLoad() << INST_LOAD) |
 396             (inst->isStore() << INST_STORE) |
 397             (inst->isControl() << INST_CONTROL) |
 398             (inst->isNonSpeculative() << INST_NONSPEC) |
 399             (inst->numDestRegs() << INST_DEST_REGS) |
 400             (inst->numSrcRegs() << INST_SRC_REGS) |
 401             (inst->splitInst << INST_SPLIT_DATA);
 402         return id;
 403     }
 404
 405     ThePipeline::RSkedPtr createFrontEndSked();
 406     ThePipeline::RSkedPtr createFaultSked();
 407     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 408
 409     class StageScheduler {
 410       private:
 411         ThePipeline::RSkedPtr rsked;
 412         int stageNum;
 413         int nextTaskPriority;
 414
 415       public:
 416         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 417             : rsked(_rsked), stageNum(stage_num),
 418               nextTaskPriority(0)
 419         { }
 420
 421         void needs(int unit, int request) {
 422             rsked->push(new ScheduleEntry(
 423                             stageNum, nextTaskPriority++, unit, request
 424                             ));
 425         }
 426
 427         void needs(int unit, int request, int param) {
 428             rsked->push(new ScheduleEntry(
 429                             stageNum, nextTaskPriority++, unit, request, param
 430                             ));
 431         }
 432     };
 433
 434   private:
 435
 436     /** Data port. Note that it has to appear after the resPool. */
 437     CachePort dataPort;
 438
 439     /** Instruction port. Note that it has to appear after the resPool. */
 440     CachePort instPort;
 441
 442   public:
 443
 444     /** Registers statistics. */
 445     void regStats();
 446
 447     /** Ticks CPU, calling tick() on each stage, and checking the overall
 448      *  activity to see if the CPU should deschedule itself.
 449      */
 450     void tick();
 451
 452     /** Initialize the CPU */
 453     void init();
 454
 455     /** HW return from error interrupt. */
 456     Fault hwrei(ThreadID tid);
 457
 458     bool simPalCheck(int palFunc, ThreadID tid);
 459
 460     void checkForInterrupts();
 461
 462     /** Returns the Fault for any valid interrupt. */
 463     Fault getInterrupts();
 464
 465     /** Processes any an interrupt fault. */
 466     void processInterrupts(Fault interrupt);
 467
 468     /** Halts the CPU. */
 469     void halt() { panic("Halt not implemented!\n"); }
 470
 471     /** Check if this address is a valid instruction address. */
 472     bool validInstAddr(Addr addr) { return true; }
 473
 474     /** Check if this address is a valid data address. */
 475     bool validDataAddr(Addr addr) { return true; }
 476
 477     /** Schedule a syscall on the CPU */
 478     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 479                         int delay = 0);
 480
 481     /** Executes a syscall.*/
 482     void syscall(int64_t callnum, ThreadID tid);
 483
 484     /** Schedule a trap on the CPU */
 485     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 486
 487     /** Perform trap to Handle Given Fault */
 488     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 489
 490     /** Schedule thread activation on the CPU */
 491     void activateContext(ThreadID tid, int delay = 0);
 492
 493     /** Add Thread to Active Threads List. */
 494     void activateThread(ThreadID tid);
 495
 496     /** Activate Thread In Each Pipeline Stage */
 497     void activateThreadInPipeline(ThreadID tid);
 498
 499     /** Schedule Thread Activation from Ready List */
 500     void activateNextReadyContext(int delay = 0);
 501
 502     /** Add Thread From Ready List to Active Threads List. */
 503     void activateNextReadyThread();
 504
 505     /** Schedule a thread deactivation on the CPU */
 506     void deactivateContext(ThreadID tid, int delay = 0);
 507
 508     /** Remove from Active Thread List */
 509     void deactivateThread(ThreadID tid);
 510
 511     /** Schedule a thread suspension on the CPU */
 512   void suspendContext(ThreadID tid);
 513
 514     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 515     void suspendThread(ThreadID tid);
 516
 517     /** Schedule a thread halt on the CPU */
 518     void haltContext(ThreadID tid);
 519
 520     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 521      *  Threads List
 522      */
 523     void haltThread(ThreadID tid);
 524
 525     /** squashFromMemStall() - sets up a squash event
 526      *  squashDueToMemStall() - squashes pipeline
 527      *  @note: maybe squashContext/squashThread would be better?
 528      */
 529     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 530     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 531
 532     void removePipelineStalls(ThreadID tid);
 533     void squashThreadInPipeline(ThreadID tid);
 534     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 535
 536     PipelineStage* getPipeStage(int stage_num);
 537
 538     int
 539     contextId()
 540     {
 541         hack_once("return a bogus context id");
 542         return 0;
 543     }
 544
 545     /** Update The Order In Which We Process Threads. */
 546     void updateThreadPriority();
 547
 548     /** Switches a Pipeline Stage to Active. (Unused currently) */
 549     void switchToActive(int stage_idx)
 550     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 551
 552     /** Get the current instruction sequence number, and increment it. */
 553     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 554     { return globalSeqNum[tid]++; }
 555
 556     /** Get the current instruction sequence number, and increment it. */
 557     InstSeqNum nextInstSeqNum(ThreadID tid)
 558     { return globalSeqNum[tid]; }
 559
 560     /** Increment Instruction Sequence Number */
 561     void incrInstSeqNum(ThreadID tid)
 562     { globalSeqNum[tid]++; }
 563
 564     /** Set Instruction Sequence Number */
 565     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 566     {
 567         globalSeqNum[tid] = seq_num;
 568     }
 569
 570     /** Get & Update Next Event Number */
 571     InstSeqNum getNextEventNum()
 572     {
 573 #ifdef DEBUG
 574         return cpuEventNum++;
 575 #else
 576         return 0;
 577 #endif
 578     }
 579
 580     /** Register file accessors  */
 581     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 582
 583     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 584
 585     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 586
 587     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 588
 589     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 590
 591     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 592
 593     RegType inline getRegType(RegIndex reg_idx)
 594     {
 595         if (reg_idx < TheISA::FP_Base_DepTag)
 596             return IntType;
 597         else if (reg_idx < TheISA::Ctrl_Base_DepTag)
 598             return FloatType;
 599         else
 600             return MiscType;
 601     }
 602
 603     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 604
 605     /** Reads a miscellaneous register. */
 606     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 607
 608     /** Reads a misc. register, including any side effects the read
 609      * might have as defined by the architecture.
 610      */
 611     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 612
 613     /** Sets a miscellaneous register. */
 614     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 615                             ThreadID tid = 0);
 616
 617     /** Sets a misc. register, including any side effects the write
 618      * might have as defined by the architecture.
 619      */
 620     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 621
 622     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 623      *  target thread
 624      */
 625     uint64_t readRegOtherThread(unsigned misc_reg,
 626                                 ThreadID tid = InvalidThreadID);
 627
 628     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 629      * target thread
 630      */
 631     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 632                            ThreadID tid);
 633
 634     /** Reads the commit PC of a specific thread. */
 635     TheISA::PCState
 636     pcState(ThreadID tid)
 637     {
 638         return pc[tid];
 639     }
 640
 641     /** Sets the commit PC of a specific thread. */
 642     void
 643     pcState(const TheISA::PCState &newPC, ThreadID tid)
 644     {
 645         pc[tid] = newPC;
 646     }
 647
 648     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 649     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 650     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 651
 652     /** Function to add instruction onto the head of the list of the
 653      *  instructions.  Used when new instructions are fetched.
 654      */
 655     ListIt addInst(DynInstPtr inst);
 656
 657     /** Find instruction on instruction list */
 658     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 659
 660     /** Function to tell the CPU that an instruction has completed. */
 661     void instDone(DynInstPtr inst, ThreadID tid);
 662
 663     /** Add Instructions to the CPU Remove List*/
 664     void addToRemoveList(DynInstPtr inst);
 665
 666     /** Remove an instruction from CPU */
 667     void removeInst(DynInstPtr inst);
 668
 669     /** Remove all instructions younger than the given sequence number. */
 670     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 671
 672     /** Removes the instruction pointed to by the iterator. */
 673     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 674
 675     /** Cleans up all instructions on the instruction remove list. */
 676     void cleanUpRemovedInsts();
 677
 678     /** Cleans up all events on the CPU event remove list. */
 679     void cleanUpRemovedEvents();
 680
 681     /** Debug function to print all instructions on the list. */
 682     void dumpInsts();
 683
 684     /** Forwards an instruction read to the appropriate data
 685      *  resource (indexes into Resource Pool thru "dataPortIdx")
 686      */
 687     Fault read(DynInstPtr inst, Addr addr,
 688                uint8_t *data, unsigned size, unsigned flags);
 689
 690     /** Forwards an instruction write. to the appropriate data
 691      *  resource (indexes into Resource Pool thru "dataPortIdx")
 692      */
 693     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 694                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 695
 696   public:
 697     /** Per-Thread List of all the instructions in flight. */
 698     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 699
 700     /** List of all the instructions that will be removed at the end of this
 701      *  cycle.
 702      */
 703     std::queue<ListIt> removeList;
 704
 705     bool trapPending[ThePipeline::MaxThreads];
 706
 707     /** List of all the cpu event requests that will be removed at the end of
 708      *  the current cycle.
 709      */
 710     std::queue<Event*> cpuEventRemoveList;
 711
 712     /** Records if instructions need to be removed this cycle due to
 713      *  being retired or squashed.
 714      */
 715     bool removeInstsThisCycle;
 716
 717     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 718      * execution unit know, NOT to execute while the instruction is active.
 719      */
 720     bool nonSpecInstActive[ThePipeline::MaxThreads];
 721
 722     /** Instruction Seq. Num of current non-speculative instruction. */
 723     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 724
 725     /** Instruction Seq. Num of last instruction squashed in pipeline */
 726     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 727
 728     /** Last Cycle that the CPU squashed instruction end. */
 729     Tick lastSquashCycle[ThePipeline::MaxThreads];
 730
 731     std::list<ThreadID> fetchPriorityList;
 732
 733   protected:
 734     /** Active Threads List */
 735     std::list<ThreadID> activeThreads;
 736
 737     /** Ready Threads List */
 738     std::list<ThreadID> readyThreads;
 739
 740     /** Suspended Threads List */
 741     std::list<ThreadID> suspendedThreads;
 742
 743     /** Halted Threads List */
 744     std::list<ThreadID> haltedThreads;
 745
 746     /** Thread Status Functions */
 747     bool isThreadActive(ThreadID tid);
 748     bool isThreadReady(ThreadID tid);
 749     bool isThreadSuspended(ThreadID tid);
 750
 751   private:
 752     /** The activity recorder; used to tell if the CPU has any
 753      * activity remaining or if it can go to idle and deschedule
 754      * itself.
 755      */
 756     ActivityRecorder activityRec;
 757
 758   public:
 759     /** Number of Active Threads in the CPU */
 760     ThreadID numActiveThreads() { return activeThreads.size(); }
 761
 762     /** Thread id of active thread
 763      *  Only used for SwitchOnCacheMiss model.
 764      *  Assumes only 1 thread active
 765      */
 766     ThreadID activeThreadId()
 767     {
 768         if (numActiveThreads() > 0)
 769             return activeThreads.front();
 770         else
 771             return InvalidThreadID;
 772     }
 773
 774
 775     /** Records that there was time buffer activity this cycle. */
 776     void activityThisCycle() { activityRec.activity(); }
 777
 778     /** Changes a stage's status to active within the activity recorder. */
 779     void activateStage(const int idx)
 780     { activityRec.activateStage(idx); }
 781
 782     /** Changes a stage's status to inactive within the activity recorder. */
 783     void deactivateStage(const int idx)
 784     { activityRec.deactivateStage(idx); }
 785
 786     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 787     void wakeCPU();
 788
 789     virtual void wakeup();
 790
 791     /* LL/SC debug functionality
 792     unsigned stCondFails;
 793
 794     unsigned readStCondFailures()
 795     { return stCondFails; }
 796
 797     unsigned setStCondFailures(unsigned st_fails)
 798     { return stCondFails = st_fails; }
 799     */
 800
 801     /** Returns a pointer to a thread context. */
 802     ThreadContext *tcBase(ThreadID tid = 0)
 803     {
 804         return thread[tid]->getTC();
 805     }
 806
 807     /** Count the Total Instructions Committed in the CPU. */
 808     virtual Counter totalInsts() const
 809     {
 810         Counter total(0);
 811
 812         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 813             total += thread[tid]->numInst;
 814
 815         return total;
 816     }
 817
 818     /** Count the Total Ops Committed in the CPU. */
 819     virtual Counter totalOps() const
 820     {
 821         Counter total(0);
 822
 823         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 824             total += thread[tid]->numOp;
 825
 826         return total;
 827     }
 828
 829     /** Pointer to the system. */
 830     System *system;
 831
 832     /** The global sequence number counter. */
 833     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 834
 835 #ifdef DEBUG
 836     /** The global event number counter. */
 837     InstSeqNum cpuEventNum;
 838
 839     /** Number of resource requests active in CPU **/
 840     unsigned resReqCount;
 841 #endif
 842
 843     Addr lockAddr;
 844
 845     /** Temporary fix for the lock flag, works in the UP case. */
 846     bool lockFlag;
 847
 848     /** Counter of how many stages have completed draining */
 849     int drainCount;
 850
 851     /** Pointers to all of the threads in the CPU. */
 852     std::vector<Thread *> thread;
 853
 854     /** Whether or not the CPU should defer its registration. */
 855     bool deferRegistration;
 856
 857     /** Per-Stage Instruction Tracing */
 858     bool stageTracing;
 859
 860     /** The cycle that the CPU was last running, used for statistics. */
 861     Tick lastRunningCycle;
 862
 863     void updateContextSwitchStats();
 864     unsigned instsPerSwitch;
 865     Stats::Average instsPerCtxtSwitch;
 866     Stats::Scalar numCtxtSwitches;
 867
 868     /** Update Thread , used for statistic purposes*/
 869     inline void tickThreadStats();
 870
 871     /** Per-Thread Tick */
 872     Stats::Vector threadCycles;
 873
 874     /** Tick for SMT */
 875     Stats::Scalar smtCycles;
 876
 877     /** Stat for total number of times the CPU is descheduled. */
 878     Stats::Scalar timesIdled;
 879
 880     /** Stat for total number of cycles the CPU spends descheduled or no
 881      *  stages active.
 882      */
 883     Stats::Scalar idleCycles;
 884
 885     /** Stat for total number of cycles the CPU is active. */
 886     Stats::Scalar runCycles;
 887
 888     /** Percentage of cycles a stage was active */
 889     Stats::Formula activity;
 890
 891     /** Instruction Mix Stats */
 892     Stats::Scalar comLoads;
 893     Stats::Scalar comStores;
 894     Stats::Scalar comBranches;
 895     Stats::Scalar comNops;
 896     Stats::Scalar comNonSpec;
 897     Stats::Scalar comInts;
 898     Stats::Scalar comFloats;
 899
 900     /** Stat for the number of committed instructions per thread. */
 901     Stats::Vector committedInsts;
 902
 903     /** Stat for the number of committed ops per thread. */
 904     Stats::Vector committedOps;
 905
 906     /** Stat for the number of committed instructions per thread. */
 907     Stats::Vector smtCommittedInsts;
 908
 909     /** Stat for the total number of committed instructions. */
 910     Stats::Scalar totalCommittedInsts;
 911
 912     /** Stat for the CPI per thread. */
 913     Stats::Formula cpi;
 914
 915     /** Stat for the SMT-CPI per thread. */
 916     Stats::Formula smtCpi;
 917
 918     /** Stat for the total CPI. */
 919     Stats::Formula totalCpi;
 920
 921     /** Stat for the IPC per thread. */
 922     Stats::Formula ipc;
 923
 924     /** Stat for the total IPC. */
 925     Stats::Formula smtIpc;
 926
 927     /** Stat for the total IPC. */
 928     Stats::Formula totalIpc;
 929 };
 930
 931 #endif // __CPU_O3_CPU_HH__