2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CPU_HH__
33 #define __CPU_INORDER_CPU_HH__
41 #include "arch/isa_traits.hh"
42 #include "arch/types.hh"
43 #include "arch/registers.hh"
44 #include "base/statistics.hh"
45 #include "base/timebuf.hh"
46 #include "base/types.hh"
47 #include "config/full_system.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/activity.hh"
50 #include "cpu/base.hh"
51 #include "cpu/simple_thread.hh"
52 #include "cpu/inorder/inorder_dyn_inst.hh"
53 #include "cpu/inorder/pipeline_traits.hh"
54 #include "cpu/inorder/pipeline_stage.hh"
55 #include "cpu/inorder/thread_state.hh"
56 #include "cpu/inorder/reg_dep_map.hh"
57 #include "cpu/o3/dep_graph.hh"
58 #include "cpu/o3/rename_map.hh"
59 #include "mem/packet.hh"
60 #include "mem/port.hh"
61 #include "mem/request.hh"
62 #include "sim/eventq.hh"
63 #include "sim/process.hh"
71 class InOrderCPU : public BaseCPU
75 typedef ThePipeline::Params Params;
76 typedef InOrderThreadState Thread;
79 typedef TheISA::IntReg IntReg;
80 typedef TheISA::FloatReg FloatReg;
81 typedef TheISA::FloatRegBits FloatRegBits;
82 typedef TheISA::MiscReg MiscReg;
85 typedef ThePipeline::DynInstPtr DynInstPtr;
86 typedef std::list<DynInstPtr>::iterator ListIt;
89 typedef TimeBuffer<InterStageStruct> StageQueue;
91 friend class Resource;
94 /** Constructs a CPU with the given parameters. */
95 InOrderCPU(Params *params);
103 ThreadID asid[ThePipeline::MaxThreads];
105 /** Type of core that this is */
106 std::string coreType;
108 // Only need for SE MODE
115 ThreadModel threadModel;
117 int readCpuId() { return cpu_id; }
119 void setCpuId(int val) { cpu_id = val; }
132 /** Overall CPU status. */
135 /** Define TickEvent for the CPU */
136 class TickEvent : public Event
139 /** Pointer to the CPU. */
143 /** Constructs a tick event. */
144 TickEvent(InOrderCPU *c);
146 /** Processes a tick event, calling tick() on the CPU. */
149 /** Returns the description of the tick event. */
150 const char *description();
153 /** The tick event used for scheduling CPU ticks. */
156 /** Schedule tick event, regardless of its current state. */
157 void scheduleTickEvent(int delay)
159 if (tickEvent.squashed())
160 mainEventQueue.reschedule(&tickEvent,
161 nextCycle(curTick + ticks(delay)));
162 else if (!tickEvent.scheduled())
163 mainEventQueue.schedule(&tickEvent,
164 nextCycle(curTick + ticks(delay)));
167 /** Unschedule tick event, regardless of its current state. */
168 void unscheduleTickEvent()
170 if (tickEvent.scheduled())
175 // List of Events That can be scheduled from
177 // NOTE(1): The Resource Pool also uses this event list
178 // to schedule events broadcast to all resources interfaces
179 // NOTE(2): CPU Events usually need to schedule a corresponding resource
183 ActivateNextReadyThread,
194 static std::string eventNames[NumCPUEvents];
196 /** Define CPU Event */
197 class CPUEvent : public Event
203 CPUEventType cpuEventType;
210 /** Constructs a CPU event. */
211 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
212 ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
214 /** Set Type of Event To Be Scheduled */
215 void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
219 cpuEventType = e_type;
225 /** Processes a CPU event. */
228 /** Returns the description of the CPU event. */
229 const char *description();
231 /** Schedule Event */
232 void scheduleEvent(int delay);
234 /** Unschedule This Event */
235 void unscheduleEvent();
238 /** Schedule a CPU Event */
239 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
240 DynInstPtr inst, unsigned delay = 0,
241 unsigned event_pri_offset = 0);
244 /** Interface between the CPU and CPU resources. */
245 ResourcePool *resPool;
247 /** Instruction used to signify that there is no *real* instruction in
249 DynInstPtr dummyInst[ThePipeline::MaxThreads];
250 DynInstPtr dummyBufferInst;
251 DynInstPtr dummyReqInst;
253 /** Used by resources to signify a denied access to a resource. */
254 ResourceRequest *dummyReq[ThePipeline::MaxThreads];
256 /** Identifies the resource id that identifies a fetch
259 unsigned fetchPortIdx;
261 /** Identifies the resource id that identifies a ITB */
264 /** Identifies the resource id that identifies a data
267 unsigned dataPortIdx;
269 /** Identifies the resource id that identifies a DTB */
272 /** The Pipeline Stages for the CPU */
273 PipelineStage *pipelineStage[ThePipeline::NumStages];
275 /** Program Counters */
276 TheISA::PCState pc[ThePipeline::MaxThreads];
278 /** The Register File for the CPU */
280 FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
281 FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
283 TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
286 TheISA::ISA isa[ThePipeline::MaxThreads];
288 /** Dependency Tracker for Integer & Floating Point Regs */
289 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
291 /** Global communication structure */
292 TimeBuffer<TimeStruct> timeBuffer;
294 /** Communication structure that sits in between pipeline stages */
295 StageQueue *stageQueue[ThePipeline::NumStages-1];
297 TheISA::TLB *getITBPtr();
298 TheISA::TLB *getDTBPtr();
302 /** Registers statistics. */
305 /** Ticks CPU, calling tick() on each stage, and checking the overall
306 * activity to see if the CPU should deschedule itself.
310 /** Initialize the CPU */
313 /** Reset State in the CPU */
316 /** Get a Memory Port */
317 Port* getPort(const std::string &if_name, int idx = 0);
320 /** HW return from error interrupt. */
321 Fault hwrei(ThreadID tid);
323 bool simPalCheck(int palFunc, ThreadID tid);
325 /** Returns the Fault for any valid interrupt. */
326 Fault getInterrupts();
328 /** Processes any an interrupt fault. */
329 void processInterrupts(Fault interrupt);
331 /** Halts the CPU. */
332 void halt() { panic("Halt not implemented!\n"); }
334 /** Update the Virt and Phys ports of all ThreadContexts to
335 * reflect change in memory connections. */
336 void updateMemPorts();
338 /** Check if this address is a valid instruction address. */
339 bool validInstAddr(Addr addr) { return true; }
341 /** Check if this address is a valid data address. */
342 bool validDataAddr(Addr addr) { return true; }
345 /** trap() - sets up a trap event on the cpuTraps to handle given fault.
346 * trapCPU() - Traps to handle given fault
348 void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
349 void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
351 /** Add Thread to Active Threads List. */
352 void activateContext(ThreadID tid, int delay = 0);
353 void activateThread(ThreadID tid);
354 void activateThreadInPipeline(ThreadID tid);
356 /** Add Thread to Active Threads List. */
357 void activateNextReadyContext(int delay = 0);
358 void activateNextReadyThread();
360 /** Remove from Active Thread List */
361 void deactivateContext(ThreadID tid, int delay = 0);
362 void deactivateThread(ThreadID tid);
364 /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
365 void suspendContext(ThreadID tid, int delay = 0);
366 void suspendThread(ThreadID tid);
368 /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
371 void haltContext(ThreadID tid, int delay = 0);
372 void haltThread(ThreadID tid);
374 /** squashFromMemStall() - sets up a squash event
375 * squashDueToMemStall() - squashes pipeline
376 * @note: maybe squashContext/squashThread would be better?
378 void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
379 void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
381 void removePipelineStalls(ThreadID tid);
382 void squashThreadInPipeline(ThreadID tid);
383 void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
385 PipelineStage* getPipeStage(int stage_num);
390 hack_once("return a bogus context id");
394 /** Update The Order In Which We Process Threads. */
395 void updateThreadPriority();
397 /** Switches a Pipeline Stage to Active. (Unused currently) */
398 void switchToActive(int stage_idx)
399 { /*pipelineStage[stage_idx]->switchToActive();*/ }
401 /** Get the current instruction sequence number, and increment it. */
402 InstSeqNum getAndIncrementInstSeq(ThreadID tid)
403 { return globalSeqNum[tid]++; }
405 /** Get the current instruction sequence number, and increment it. */
406 InstSeqNum nextInstSeqNum(ThreadID tid)
407 { return globalSeqNum[tid]; }
409 /** Increment Instruction Sequence Number */
410 void incrInstSeqNum(ThreadID tid)
411 { globalSeqNum[tid]++; }
413 /** Set Instruction Sequence Number */
414 void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
416 globalSeqNum[tid] = seq_num;
419 /** Get & Update Next Event Number */
420 InstSeqNum getNextEventNum()
423 return cpuEventNum++;
429 /** Register file accessors */
430 uint64_t readIntReg(int reg_idx, ThreadID tid);
432 FloatReg readFloatReg(int reg_idx, ThreadID tid);
434 FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
436 void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
438 void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
440 void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid);
442 /** Reads a miscellaneous register. */
443 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
445 /** Reads a misc. register, including any side effects the read
446 * might have as defined by the architecture.
448 MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
450 /** Sets a miscellaneous register. */
451 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
454 /** Sets a misc. register, including any side effects the write
455 * might have as defined by the architecture.
457 void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
459 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
462 uint64_t readRegOtherThread(unsigned misc_reg,
463 ThreadID tid = InvalidThreadID);
465 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
468 void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
471 /** Reads the commit PC of a specific thread. */
473 pcState(ThreadID tid)
478 /** Sets the commit PC of a specific thread. */
480 pcState(const TheISA::PCState &newPC, ThreadID tid)
485 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
486 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
487 MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
489 /** Function to add instruction onto the head of the list of the
490 * instructions. Used when new instructions are fetched.
492 ListIt addInst(DynInstPtr &inst);
494 /** Function to tell the CPU that an instruction has completed. */
495 void instDone(DynInstPtr inst, ThreadID tid);
497 /** Add Instructions to the CPU Remove List*/
498 void addToRemoveList(DynInstPtr &inst);
500 /** Remove an instruction from CPU */
501 void removeInst(DynInstPtr &inst);
503 /** Remove all instructions younger than the given sequence number. */
504 void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
506 /** Removes the instruction pointed to by the iterator. */
507 inline void squashInstIt(const ListIt &instIt, ThreadID tid);
509 /** Cleans up all instructions on the instruction remove list. */
510 void cleanUpRemovedInsts();
512 /** Cleans up all instructions on the request remove list. */
513 void cleanUpRemovedReqs();
515 /** Cleans up all instructions on the CPU event remove list. */
516 void cleanUpRemovedEvents();
518 /** Debug function to print all instructions on the list. */
521 /** Forwards an instruction read to the appropriate data
522 * resource (indexes into Resource Pool thru "dataPortIdx")
524 Fault read(DynInstPtr inst, Addr addr,
525 uint8_t *data, unsigned size, unsigned flags);
527 /** Forwards an instruction write. to the appropriate data
528 * resource (indexes into Resource Pool thru "dataPortIdx")
530 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
531 Addr addr, unsigned flags, uint64_t *write_res = NULL);
533 /** Executes a syscall.*/
534 void syscall(int64_t callnum, ThreadID tid);
537 /** Per-Thread List of all the instructions in flight. */
538 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
540 /** List of all the instructions that will be removed at the end of this
543 std::queue<ListIt> removeList;
545 /** List of all the resource requests that will be removed at the end
548 std::queue<ResourceRequest*> reqRemoveList;
550 /** List of all the cpu event requests that will be removed at the end of
553 std::queue<Event*> cpuEventRemoveList;
555 /** Records if instructions need to be removed this cycle due to
556 * being retired or squashed.
558 bool removeInstsThisCycle;
560 /** True if there is non-speculative Inst Active In Pipeline. Lets any
561 * execution unit know, NOT to execute while the instruction is active.
563 bool nonSpecInstActive[ThePipeline::MaxThreads];
565 /** Instruction Seq. Num of current non-speculative instruction. */
566 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
568 /** Instruction Seq. Num of last instruction squashed in pipeline */
569 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
571 /** Last Cycle that the CPU squashed instruction end. */
572 Tick lastSquashCycle[ThePipeline::MaxThreads];
574 std::list<ThreadID> fetchPriorityList;
577 /** Active Threads List */
578 std::list<ThreadID> activeThreads;
580 /** Ready Threads List */
581 std::list<ThreadID> readyThreads;
583 /** Suspended Threads List */
584 std::list<ThreadID> suspendedThreads;
586 /** Halted Threads List */
587 std::list<ThreadID> haltedThreads;
589 /** Thread Status Functions */
590 bool isThreadActive(ThreadID tid);
591 bool isThreadReady(ThreadID tid);
592 bool isThreadSuspended(ThreadID tid);
595 /** The activity recorder; used to tell if the CPU has any
596 * activity remaining or if it can go to idle and deschedule
599 ActivityRecorder activityRec;
602 /** Number of Active Threads in the CPU */
603 ThreadID numActiveThreads() { return activeThreads.size(); }
605 /** Thread id of active thread
606 * Only used for SwitchOnCacheMiss model.
607 * Assumes only 1 thread active
609 ThreadID activeThreadId()
611 if (numActiveThreads() > 0)
612 return activeThreads.front();
614 return InvalidThreadID;
618 /** Records that there was time buffer activity this cycle. */
619 void activityThisCycle() { activityRec.activity(); }
621 /** Changes a stage's status to active within the activity recorder. */
622 void activateStage(const int idx)
623 { activityRec.activateStage(idx); }
625 /** Changes a stage's status to inactive within the activity recorder. */
626 void deactivateStage(const int idx)
627 { activityRec.deactivateStage(idx); }
629 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
633 virtual void wakeup();
636 // LL/SC debug functionality
637 unsigned stCondFails;
639 unsigned readStCondFailures()
640 { return stCondFails; }
642 unsigned setStCondFailures(unsigned st_fails)
643 { return stCondFails = st_fails; }
645 /** Returns a pointer to a thread context. */
646 ThreadContext *tcBase(ThreadID tid = 0)
648 return thread[tid]->getTC();
651 /** Count the Total Instructions Committed in the CPU. */
652 virtual Counter totalInstructions() const
656 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
657 total += thread[tid]->numInst;
663 /** Pointer to the system. */
666 /** Pointer to physical memory. */
667 PhysicalMemory *physmem;
670 /** The global sequence number counter. */
671 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
674 /** The global event number counter. */
675 InstSeqNum cpuEventNum;
677 /** Number of resource requests active in CPU **/
678 unsigned resReqCount;
681 /** Counter of how many stages have completed switching out. */
684 /** Pointers to all of the threads in the CPU. */
685 std::vector<Thread *> thread;
687 /** Pointer to the icache interface. */
688 MemInterface *icacheInterface;
690 /** Pointer to the dcache interface. */
691 MemInterface *dcacheInterface;
693 /** Whether or not the CPU should defer its registration. */
694 bool deferRegistration;
696 /** Per-Stage Instruction Tracing */
699 /** The cycle that the CPU was last running, used for statistics. */
700 Tick lastRunningCycle;
702 void updateContextSwitchStats();
703 unsigned instsPerSwitch;
704 Stats::Average instsPerCtxtSwitch;
705 Stats::Scalar numCtxtSwitches;
707 /** Update Thread , used for statistic purposes*/
708 inline void tickThreadStats();
710 /** Per-Thread Tick */
711 Stats::Vector threadCycles;
714 Stats::Scalar smtCycles;
716 /** Stat for total number of times the CPU is descheduled. */
717 Stats::Scalar timesIdled;
719 /** Stat for total number of cycles the CPU spends descheduled or no
722 Stats::Scalar idleCycles;
724 /** Stat for total number of cycles the CPU is active. */
725 Stats::Scalar runCycles;
727 /** Percentage of cycles a stage was active */
728 Stats::Formula activity;
730 /** Instruction Mix Stats */
731 Stats::Scalar comLoads;
732 Stats::Scalar comStores;
733 Stats::Scalar comBranches;
734 Stats::Scalar comNops;
735 Stats::Scalar comNonSpec;
736 Stats::Scalar comInts;
737 Stats::Scalar comFloats;
739 /** Stat for the number of committed instructions per thread. */
740 Stats::Vector committedInsts;
742 /** Stat for the number of committed instructions per thread. */
743 Stats::Vector smtCommittedInsts;
745 /** Stat for the total number of committed instructions. */
746 Stats::Scalar totalCommittedInsts;
748 /** Stat for the CPI per thread. */
751 /** Stat for the SMT-CPI per thread. */
752 Stats::Formula smtCpi;
754 /** Stat for the total CPI. */
755 Stats::Formula totalCpi;
757 /** Stat for the IPC per thread. */
760 /** Stat for the total IPC. */
761 Stats::Formula smtIpc;
763 /** Stat for the total IPC. */
764 Stats::Formula totalIpc;
767 #endif // __CPU_O3_CPU_HH__