2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_CPU_HH__
33 #define __CPU_INORDER_CPU_HH__
41 #include "arch/isa_traits.hh"
42 #include "arch/registers.hh"
43 #include "arch/types.hh"
44 #include "base/statistics.hh"
45 #include "base/types.hh"
46 #include "config/the_isa.hh"
47 #include "cpu/inorder/inorder_dyn_inst.hh"
48 #include "cpu/inorder/pipeline_stage.hh"
49 #include "cpu/inorder/pipeline_traits.hh"
50 #include "cpu/inorder/reg_dep_map.hh"
51 #include "cpu/inorder/thread_state.hh"
52 #include "cpu/o3/dep_graph.hh"
53 #include "cpu/o3/rename_map.hh"
54 #include "cpu/activity.hh"
55 #include "cpu/base.hh"
56 #include "cpu/simple_thread.hh"
57 #include "cpu/timebuf.hh"
58 #include "mem/packet.hh"
59 #include "mem/port.hh"
60 #include "mem/request.hh"
61 #include "sim/eventq.hh"
62 #include "sim/process.hh"
70 class InOrderCPU : public BaseCPU
74 typedef ThePipeline::Params Params;
75 typedef InOrderThreadState Thread;
78 typedef TheISA::IntReg IntReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
81 typedef TheISA::MiscReg MiscReg;
82 typedef TheISA::RegIndex RegIndex;
85 typedef ThePipeline::DynInstPtr DynInstPtr;
86 typedef std::list<DynInstPtr>::iterator ListIt;
89 typedef TimeBuffer<InterStageStruct> StageQueue;
91 friend class Resource;
94 /** Constructs a CPU with the given parameters. */
95 InOrderCPU(Params *params);
103 ThreadID asid[ThePipeline::MaxThreads];
105 /** Type of core that this is */
106 std::string coreType;
108 // Only need for SE MODE
115 ThreadModel threadModel;
117 int readCpuId() { return cpu_id; }
119 void setCpuId(int val) { cpu_id = val; }
132 /** Overall CPU status. */
135 /** Define TickEvent for the CPU */
136 class TickEvent : public Event
139 /** Pointer to the CPU. */
143 /** Constructs a tick event. */
144 TickEvent(InOrderCPU *c);
146 /** Processes a tick event, calling tick() on the CPU. */
149 /** Returns the description of the tick event. */
150 const char *description();
153 /** The tick event used for scheduling CPU ticks. */
156 /** Schedule tick event, regardless of its current state. */
157 void scheduleTickEvent(int delay)
159 assert(!tickEvent.scheduled() || tickEvent.squashed());
160 reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
163 /** Unschedule tick event, regardless of its current state. */
164 void unscheduleTickEvent()
166 if (tickEvent.scheduled())
171 // List of Events That can be scheduled from
173 // NOTE(1): The Resource Pool also uses this event list
174 // to schedule events broadcast to all resources interfaces
175 // NOTE(2): CPU Events usually need to schedule a corresponding resource
179 ActivateNextReadyThread,
190 static std::string eventNames[NumCPUEvents];
193 InOrderCPU_Pri = Event::CPU_Tick_Pri,
194 Syscall_Pri = Event::CPU_Tick_Pri + 9,
195 ActivateNextReadyThread_Pri = Event::CPU_Tick_Pri + 10
198 /** Define CPU Event */
199 class CPUEvent : public Event
205 CPUEventType cpuEventType;
213 /** Constructs a CPU event. */
214 CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
215 ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
217 /** Set Type of Event To Be Scheduled */
218 void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
222 cpuEventType = e_type;
228 /** Processes a CPU event. */
231 /** Returns the description of the CPU event. */
232 const char *description();
234 /** Schedule Event */
235 void scheduleEvent(int delay);
237 /** Unschedule This Event */
238 void unscheduleEvent();
241 /** Schedule a CPU Event */
242 void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
243 DynInstPtr inst, unsigned delay = 0,
244 CPUEventPri event_pri = InOrderCPU_Pri);
247 /** Interface between the CPU and CPU resources. */
248 ResourcePool *resPool;
250 /** Instruction used to signify that there is no *real* instruction in
252 DynInstPtr dummyInst[ThePipeline::MaxThreads];
253 DynInstPtr dummyBufferInst;
254 DynInstPtr dummyReqInst;
255 DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
257 /** Used by resources to signify a denied access to a resource. */
258 ResourceRequest *dummyReq[ThePipeline::MaxThreads];
260 /** Identifies the resource id that identifies a fetch
263 unsigned fetchPortIdx;
265 /** Identifies the resource id that identifies a data
268 unsigned dataPortIdx;
270 /** The Pipeline Stages for the CPU */
271 PipelineStage *pipelineStage[ThePipeline::NumStages];
273 /** Width (processing bandwidth) of each stage */
276 /** Program Counters */
277 TheISA::PCState pc[ThePipeline::MaxThreads];
279 /** Last Committed PC */
280 TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
282 /** The Register File for the CPU */
284 FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
285 FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
287 TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
290 TheISA::ISA isa[ThePipeline::MaxThreads];
292 /** Dependency Tracker for Integer & Floating Point Regs */
293 RegDepMap archRegDepMap[ThePipeline::MaxThreads];
295 /** Register Types Used in Dependency Tracking */
296 enum RegType { IntType, FloatType, MiscType, NumRegTypes};
298 /** Global communication structure */
299 TimeBuffer<TimeStruct> timeBuffer;
301 /** Communication structure that sits in between pipeline stages */
302 StageQueue *stageQueue[ThePipeline::NumStages-1];
304 TheISA::TLB *getITBPtr();
305 TheISA::TLB *getDTBPtr();
307 Decoder *getDecoderPtr();
309 /** Accessor Type for the SkedCache */
310 typedef uint32_t SkedID;
312 /** Cache of Instruction Schedule using the instruction's name as a key */
313 static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
315 typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
317 /** Initialized to last iterator in map, signifying a invalid entry
320 SkedCacheIt endOfSkedIt;
322 ThePipeline::RSkedPtr frontEndSked;
323 ThePipeline::RSkedPtr faultSked;
325 /** Add a new instruction schedule to the schedule cache */
326 void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
328 SkedID sked_id = genSkedID(inst);
329 assert(skedCache.find(sked_id) == skedCache.end());
330 skedCache[sked_id] = inst_sked;
334 /** Find a instruction schedule */
335 ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
337 SkedID sked_id = genSkedID(inst);
338 SkedCacheIt lookup_it = skedCache.find(sked_id);
340 if (lookup_it != endOfSkedIt) {
341 return (*lookup_it).second;
347 static const uint8_t INST_OPCLASS = 26;
348 static const uint8_t INST_LOAD = 25;
349 static const uint8_t INST_STORE = 24;
350 static const uint8_t INST_CONTROL = 23;
351 static const uint8_t INST_NONSPEC = 22;
352 static const uint8_t INST_DEST_REGS = 18;
353 static const uint8_t INST_SRC_REGS = 14;
354 static const uint8_t INST_SPLIT_DATA = 13;
356 inline SkedID genSkedID(DynInstPtr inst)
359 id = (inst->opClass() << INST_OPCLASS) |
360 (inst->isLoad() << INST_LOAD) |
361 (inst->isStore() << INST_STORE) |
362 (inst->isControl() << INST_CONTROL) |
363 (inst->isNonSpeculative() << INST_NONSPEC) |
364 (inst->numDestRegs() << INST_DEST_REGS) |
365 (inst->numSrcRegs() << INST_SRC_REGS) |
366 (inst->splitInst << INST_SPLIT_DATA);
370 ThePipeline::RSkedPtr createFrontEndSked();
371 ThePipeline::RSkedPtr createFaultSked();
372 ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
374 class StageScheduler {
376 ThePipeline::RSkedPtr rsked;
378 int nextTaskPriority;
381 StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
382 : rsked(_rsked), stageNum(stage_num),
386 void needs(int unit, int request) {
387 rsked->push(new ScheduleEntry(
388 stageNum, nextTaskPriority++, unit, request
392 void needs(int unit, int request, int param) {
393 rsked->push(new ScheduleEntry(
394 stageNum, nextTaskPriority++, unit, request, param
401 /** Registers statistics. */
404 /** Ticks CPU, calling tick() on each stage, and checking the overall
405 * activity to see if the CPU should deschedule itself.
409 /** Initialize the CPU */
412 /** Get a Memory Port */
413 Port* getPort(const std::string &if_name, int idx = 0);
415 /** HW return from error interrupt. */
416 Fault hwrei(ThreadID tid);
418 bool simPalCheck(int palFunc, ThreadID tid);
420 void checkForInterrupts();
422 /** Returns the Fault for any valid interrupt. */
423 Fault getInterrupts();
425 /** Processes any an interrupt fault. */
426 void processInterrupts(Fault interrupt);
428 /** Halts the CPU. */
429 void halt() { panic("Halt not implemented!\n"); }
431 /** Update the Virt and Phys ports of all ThreadContexts to
432 * reflect change in memory connections. */
433 void updateMemPorts();
435 /** Check if this address is a valid instruction address. */
436 bool validInstAddr(Addr addr) { return true; }
438 /** Check if this address is a valid data address. */
439 bool validDataAddr(Addr addr) { return true; }
441 /** Schedule a syscall on the CPU */
442 void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
445 /** Executes a syscall.*/
446 void syscall(int64_t callnum, ThreadID tid);
448 /** Schedule a trap on the CPU */
449 void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
451 /** Perform trap to Handle Given Fault */
452 void trap(Fault fault, ThreadID tid, DynInstPtr inst);
454 /** Schedule thread activation on the CPU */
455 void activateContext(ThreadID tid, int delay = 0);
457 /** Add Thread to Active Threads List. */
458 void activateThread(ThreadID tid);
460 /** Activate Thread In Each Pipeline Stage */
461 void activateThreadInPipeline(ThreadID tid);
463 /** Schedule Thread Activation from Ready List */
464 void activateNextReadyContext(int delay = 0);
466 /** Add Thread From Ready List to Active Threads List. */
467 void activateNextReadyThread();
469 /** Schedule a thread deactivation on the CPU */
470 void deactivateContext(ThreadID tid, int delay = 0);
472 /** Remove from Active Thread List */
473 void deactivateThread(ThreadID tid);
475 /** Schedule a thread suspension on the CPU */
476 void suspendContext(ThreadID tid, int delay = 0);
478 /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
479 void suspendThread(ThreadID tid);
481 /** Schedule a thread halt on the CPU */
482 void haltContext(ThreadID tid, int delay = 0);
484 /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
487 void haltThread(ThreadID tid);
489 /** squashFromMemStall() - sets up a squash event
490 * squashDueToMemStall() - squashes pipeline
491 * @note: maybe squashContext/squashThread would be better?
493 void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
494 void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
496 void removePipelineStalls(ThreadID tid);
497 void squashThreadInPipeline(ThreadID tid);
498 void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
500 PipelineStage* getPipeStage(int stage_num);
505 hack_once("return a bogus context id");
509 /** Update The Order In Which We Process Threads. */
510 void updateThreadPriority();
512 /** Switches a Pipeline Stage to Active. (Unused currently) */
513 void switchToActive(int stage_idx)
514 { /*pipelineStage[stage_idx]->switchToActive();*/ }
516 /** Get the current instruction sequence number, and increment it. */
517 InstSeqNum getAndIncrementInstSeq(ThreadID tid)
518 { return globalSeqNum[tid]++; }
520 /** Get the current instruction sequence number, and increment it. */
521 InstSeqNum nextInstSeqNum(ThreadID tid)
522 { return globalSeqNum[tid]; }
524 /** Increment Instruction Sequence Number */
525 void incrInstSeqNum(ThreadID tid)
526 { globalSeqNum[tid]++; }
528 /** Set Instruction Sequence Number */
529 void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
531 globalSeqNum[tid] = seq_num;
534 /** Get & Update Next Event Number */
535 InstSeqNum getNextEventNum()
538 return cpuEventNum++;
544 /** Register file accessors */
545 uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
547 FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
549 FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
551 void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
553 void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
555 void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
557 RegType inline getRegType(RegIndex reg_idx)
559 if (reg_idx < TheISA::FP_Base_DepTag)
561 else if (reg_idx < TheISA::Ctrl_Base_DepTag)
567 RegIndex flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid);
569 /** Reads a miscellaneous register. */
570 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
572 /** Reads a misc. register, including any side effects the read
573 * might have as defined by the architecture.
575 MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
577 /** Sets a miscellaneous register. */
578 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
581 /** Sets a misc. register, including any side effects the write
582 * might have as defined by the architecture.
584 void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
586 /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
589 uint64_t readRegOtherThread(unsigned misc_reg,
590 ThreadID tid = InvalidThreadID);
592 /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
595 void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
598 /** Reads the commit PC of a specific thread. */
600 pcState(ThreadID tid)
605 /** Sets the commit PC of a specific thread. */
607 pcState(const TheISA::PCState &newPC, ThreadID tid)
612 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
613 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
614 MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
616 /** Function to add instruction onto the head of the list of the
617 * instructions. Used when new instructions are fetched.
619 ListIt addInst(DynInstPtr inst);
621 /** Find instruction on instruction list */
622 ListIt findInst(InstSeqNum seq_num, ThreadID tid);
624 /** Function to tell the CPU that an instruction has completed. */
625 void instDone(DynInstPtr inst, ThreadID tid);
627 /** Add Instructions to the CPU Remove List*/
628 void addToRemoveList(DynInstPtr inst);
630 /** Remove an instruction from CPU */
631 void removeInst(DynInstPtr inst);
633 /** Remove all instructions younger than the given sequence number. */
634 void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
636 /** Removes the instruction pointed to by the iterator. */
637 inline void squashInstIt(const ListIt inst_it, ThreadID tid);
639 /** Cleans up all instructions on the instruction remove list. */
640 void cleanUpRemovedInsts();
642 /** Cleans up all events on the CPU event remove list. */
643 void cleanUpRemovedEvents();
645 /** Debug function to print all instructions on the list. */
648 /** Forwards an instruction read to the appropriate data
649 * resource (indexes into Resource Pool thru "dataPortIdx")
651 Fault read(DynInstPtr inst, Addr addr,
652 uint8_t *data, unsigned size, unsigned flags);
654 /** Forwards an instruction write. to the appropriate data
655 * resource (indexes into Resource Pool thru "dataPortIdx")
657 Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
658 Addr addr, unsigned flags, uint64_t *write_res = NULL);
661 /** Per-Thread List of all the instructions in flight. */
662 std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
664 /** List of all the instructions that will be removed at the end of this
667 std::queue<ListIt> removeList;
669 bool trapPending[ThePipeline::MaxThreads];
671 /** List of all the cpu event requests that will be removed at the end of
674 std::queue<Event*> cpuEventRemoveList;
676 /** Records if instructions need to be removed this cycle due to
677 * being retired or squashed.
679 bool removeInstsThisCycle;
681 /** True if there is non-speculative Inst Active In Pipeline. Lets any
682 * execution unit know, NOT to execute while the instruction is active.
684 bool nonSpecInstActive[ThePipeline::MaxThreads];
686 /** Instruction Seq. Num of current non-speculative instruction. */
687 InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
689 /** Instruction Seq. Num of last instruction squashed in pipeline */
690 InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
692 /** Last Cycle that the CPU squashed instruction end. */
693 Tick lastSquashCycle[ThePipeline::MaxThreads];
695 std::list<ThreadID> fetchPriorityList;
698 /** Active Threads List */
699 std::list<ThreadID> activeThreads;
701 /** Ready Threads List */
702 std::list<ThreadID> readyThreads;
704 /** Suspended Threads List */
705 std::list<ThreadID> suspendedThreads;
707 /** Halted Threads List */
708 std::list<ThreadID> haltedThreads;
710 /** Thread Status Functions */
711 bool isThreadActive(ThreadID tid);
712 bool isThreadReady(ThreadID tid);
713 bool isThreadSuspended(ThreadID tid);
716 /** The activity recorder; used to tell if the CPU has any
717 * activity remaining or if it can go to idle and deschedule
720 ActivityRecorder activityRec;
723 /** Number of Active Threads in the CPU */
724 ThreadID numActiveThreads() { return activeThreads.size(); }
726 /** Thread id of active thread
727 * Only used for SwitchOnCacheMiss model.
728 * Assumes only 1 thread active
730 ThreadID activeThreadId()
732 if (numActiveThreads() > 0)
733 return activeThreads.front();
735 return InvalidThreadID;
739 /** Records that there was time buffer activity this cycle. */
740 void activityThisCycle() { activityRec.activity(); }
742 /** Changes a stage's status to active within the activity recorder. */
743 void activateStage(const int idx)
744 { activityRec.activateStage(idx); }
746 /** Changes a stage's status to inactive within the activity recorder. */
747 void deactivateStage(const int idx)
748 { activityRec.deactivateStage(idx); }
750 /** Wakes the CPU, rescheduling the CPU if it's not already active. */
753 virtual void wakeup();
755 /* LL/SC debug functionality
756 unsigned stCondFails;
758 unsigned readStCondFailures()
759 { return stCondFails; }
761 unsigned setStCondFailures(unsigned st_fails)
762 { return stCondFails = st_fails; }
765 /** Returns a pointer to a thread context. */
766 ThreadContext *tcBase(ThreadID tid = 0)
768 return thread[tid]->getTC();
771 /** Count the Total Instructions Committed in the CPU. */
772 virtual Counter totalInstructions() const
776 for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
777 total += thread[tid]->numInst;
782 /** Pointer to the system. */
785 /** The global sequence number counter. */
786 InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
789 /** The global event number counter. */
790 InstSeqNum cpuEventNum;
792 /** Number of resource requests active in CPU **/
793 unsigned resReqCount;
798 /** Temporary fix for the lock flag, works in the UP case. */
801 /** Counter of how many stages have completed draining */
804 /** Pointers to all of the threads in the CPU. */
805 std::vector<Thread *> thread;
807 /** Pointer to the icache interface. */
808 MemInterface *icacheInterface;
810 /** Pointer to the dcache interface. */
811 MemInterface *dcacheInterface;
813 /** Whether or not the CPU should defer its registration. */
814 bool deferRegistration;
816 /** Per-Stage Instruction Tracing */
819 /** The cycle that the CPU was last running, used for statistics. */
820 Tick lastRunningCycle;
822 void updateContextSwitchStats();
823 unsigned instsPerSwitch;
824 Stats::Average instsPerCtxtSwitch;
825 Stats::Scalar numCtxtSwitches;
827 /** Update Thread , used for statistic purposes*/
828 inline void tickThreadStats();
830 /** Per-Thread Tick */
831 Stats::Vector threadCycles;
834 Stats::Scalar smtCycles;
836 /** Stat for total number of times the CPU is descheduled. */
837 Stats::Scalar timesIdled;
839 /** Stat for total number of cycles the CPU spends descheduled or no
842 Stats::Scalar idleCycles;
844 /** Stat for total number of cycles the CPU is active. */
845 Stats::Scalar runCycles;
847 /** Percentage of cycles a stage was active */
848 Stats::Formula activity;
850 /** Instruction Mix Stats */
851 Stats::Scalar comLoads;
852 Stats::Scalar comStores;
853 Stats::Scalar comBranches;
854 Stats::Scalar comNops;
855 Stats::Scalar comNonSpec;
856 Stats::Scalar comInts;
857 Stats::Scalar comFloats;
859 /** Stat for the number of committed instructions per thread. */
860 Stats::Vector committedInsts;
862 /** Stat for the number of committed instructions per thread. */
863 Stats::Vector smtCommittedInsts;
865 /** Stat for the total number of committed instructions. */
866 Stats::Scalar totalCommittedInsts;
868 /** Stat for the CPI per thread. */
871 /** Stat for the SMT-CPI per thread. */
872 Stats::Formula smtCpi;
874 /** Stat for the total CPI. */
875 Stats::Formula totalCpi;
877 /** Stat for the IPC per thread. */
880 /** Stat for the total IPC. */
881 Stats::Formula smtIpc;
883 /** Stat for the total IPC. */
884 Stats::Formula totalIpc;
887 #endif // __CPU_O3_CPU_HH__