src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/registers.hh"
  43 #include "arch/types.hh"
  44 #include "base/statistics.hh"
  45 #include "base/types.hh"
  46 #include "config/full_system.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/inorder/inorder_dyn_inst.hh"
  49 #include "cpu/inorder/pipeline_stage.hh"
  50 #include "cpu/inorder/pipeline_traits.hh"
  51 #include "cpu/inorder/reg_dep_map.hh"
  52 #include "cpu/inorder/thread_state.hh"
  53 #include "cpu/o3/dep_graph.hh"
  54 #include "cpu/o3/rename_map.hh"
  55 #include "cpu/activity.hh"
  56 #include "cpu/base.hh"
  57 #include "cpu/simple_thread.hh"
  58 #include "cpu/timebuf.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83     typedef TheISA::RegIndex RegIndex;
  84
  85     //DynInstPtr TypeDefs
  86     typedef ThePipeline::DynInstPtr DynInstPtr;
  87     typedef std::list<DynInstPtr>::iterator ListIt;
  88
  89     //TimeBuffer TypeDefs
  90     typedef TimeBuffer<InterStageStruct> StageQueue;
  91
  92     friend class Resource;
  93
  94   public:
  95     /** Constructs a CPU with the given parameters. */
  96     InOrderCPU(Params *params);
  97     /* Destructor */
  98     ~InOrderCPU();
  99
 100     /** CPU ID */
 101     int cpu_id;
 102
 103     // SE Mode ASIDs
 104     ThreadID asid[ThePipeline::MaxThreads];
 105
 106     /** Type of core that this is */
 107     std::string coreType;
 108
 109     // Only need for SE MODE
 110     enum ThreadModel {
 111         Single,
 112         SMT,
 113         SwitchOnCacheMiss
 114     };
 115
 116     ThreadModel threadModel;
 117
 118     int readCpuId() { return cpu_id; }
 119
 120     void setCpuId(int val) { cpu_id = val; }
 121
 122     Params *cpu_params;
 123
 124   public:
 125     enum Status {
 126         Running,
 127         Idle,
 128         Halted,
 129         Blocked,
 130         SwitchedOut
 131     };
 132
 133     /** Overall CPU status. */
 134     Status _status;
 135   private:
 136     /** Define TickEvent for the CPU */
 137     class TickEvent : public Event
 138     {
 139       private:
 140         /** Pointer to the CPU. */
 141         InOrderCPU *cpu;
 142
 143       public:
 144         /** Constructs a tick event. */
 145         TickEvent(InOrderCPU *c);
 146
 147         /** Processes a tick event, calling tick() on the CPU. */
 148         void process();
 149
 150         /** Returns the description of the tick event. */
 151         const char *description();
 152     };
 153
 154     /** The tick event used for scheduling CPU ticks. */
 155     TickEvent tickEvent;
 156
 157     /** Schedule tick event, regardless of its current state. */
 158     void scheduleTickEvent(int delay)
 159     {
 160         assert(!tickEvent.scheduled() || tickEvent.squashed());
 161         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 162     }
 163
 164     /** Unschedule tick event, regardless of its current state. */
 165     void unscheduleTickEvent()
 166     {
 167         if (tickEvent.scheduled())
 168             tickEvent.squash();
 169     }
 170
 171   public:
 172     // List of Events That can be scheduled from
 173     // within the CPU.
 174     // NOTE(1): The Resource Pool also uses this event list
 175     // to schedule events broadcast to all resources interfaces
 176     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 177     // pool event.
 178     enum CPUEventType {
 179         ActivateThread,
 180         ActivateNextReadyThread,
 181         DeactivateThread,
 182         HaltThread,
 183         SuspendThread,
 184         Trap,
 185         Syscall,
 186         SquashFromMemStall,
 187         UpdatePCs,
 188         NumCPUEvents
 189     };
 190
 191     static std::string eventNames[NumCPUEvents];
 192
 193     enum CPUEventPri {
 194         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 195         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 196         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 197     };
 198
 199     /** Define CPU Event */
 200     class CPUEvent : public Event
 201     {
 202       protected:
 203         InOrderCPU *cpu;
 204
 205       public:
 206         CPUEventType cpuEventType;
 207         ThreadID tid;
 208         DynInstPtr inst;
 209         Fault fault;
 210         unsigned vpe;
 211         short syscall_num;
 212
 213       public:
 214         /** Constructs a CPU event. */
 215         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 216                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 217
 218         /** Set Type of Event To Be Scheduled */
 219         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 220                       DynInstPtr _inst)
 221         {
 222             fault = _fault;
 223             cpuEventType = e_type;
 224             tid = _tid;
 225             inst = _inst;
 226             vpe = 0;
 227         }
 228
 229         /** Processes a CPU event. */
 230         void process();
 231
 232         /** Returns the description of the CPU event. */
 233         const char *description();
 234
 235         /** Schedule Event */
 236         void scheduleEvent(int delay);
 237
 238         /** Unschedule This Event */
 239         void unscheduleEvent();
 240     };
 241
 242     /** Schedule a CPU Event */
 243     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 244                           DynInstPtr inst, unsigned delay = 0,
 245                           CPUEventPri event_pri = InOrderCPU_Pri);
 246
 247   public:
 248     /** Interface between the CPU and CPU resources. */
 249     ResourcePool *resPool;
 250
 251     /** Instruction used to signify that there is no *real* instruction in
 252         buffer slot */
 253     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 254     DynInstPtr dummyBufferInst;
 255     DynInstPtr dummyReqInst;
 256
 257     /** Used by resources to signify a denied access to a resource. */
 258     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 259
 260     /** Identifies the resource id that identifies a fetch
 261      * access unit.
 262      */
 263     unsigned fetchPortIdx;
 264
 265     /** Identifies the resource id that identifies a ITB       */
 266     unsigned itbIdx;
 267
 268     /** Identifies the resource id that identifies a data
 269      * access unit.
 270      */
 271     unsigned dataPortIdx;
 272
 273     /** Identifies the resource id that identifies a DTB       */
 274     unsigned dtbIdx;
 275
 276     /** The Pipeline Stages for the CPU */
 277     PipelineStage *pipelineStage[ThePipeline::NumStages];
 278
 279     /** Width (processing bandwidth) of each stage */
 280     int stageWidth;
 281
 282     /** Program Counters */
 283     TheISA::PCState pc[ThePipeline::MaxThreads];
 284
 285     /** Last Committed PC */
 286     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 287
 288     /** The Register File for the CPU */
 289     union {
 290         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 291         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 292     } floatRegs;
 293     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 294
 295     /** ISA state */
 296     TheISA::ISA isa[ThePipeline::MaxThreads];
 297
 298     /** Dependency Tracker for Integer & Floating Point Regs */
 299     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 300
 301     /** Register Types Used in Dependency Tracking */
 302     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 303
 304     /** Global communication structure */
 305     TimeBuffer<TimeStruct> timeBuffer;
 306
 307     /** Communication structure that sits in between pipeline stages */
 308     StageQueue *stageQueue[ThePipeline::NumStages-1];
 309
 310     TheISA::TLB *getITBPtr();
 311     TheISA::TLB *getDTBPtr();
 312
 313     /** Accessor Type for the SkedCache */
 314     typedef uint32_t SkedID;
 315
 316     /** Cache of Instruction Schedule using the instruction's name as a key */
 317     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 318
 319     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 320
 321     /** Initialized to last iterator in map, signifying a invalid entry
 322         on map searches
 323     */
 324     SkedCacheIt endOfSkedIt;
 325
 326     ThePipeline::RSkedPtr frontEndSked;
 327
 328     /** Add a new instruction schedule to the schedule cache */
 329     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 330     {
 331         SkedID sked_id = genSkedID(inst);
 332         assert(skedCache.find(sked_id) == skedCache.end());
 333         skedCache[sked_id] = inst_sked;
 334     }
 335
 336
 337     /** Find a instruction schedule */
 338     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 339     {
 340         SkedID sked_id = genSkedID(inst);
 341         SkedCacheIt lookup_it = skedCache.find(sked_id);
 342
 343         if (lookup_it != endOfSkedIt) {
 344             return (*lookup_it).second;
 345         } else {
 346             return NULL;
 347         }
 348     }
 349
 350     static const uint8_t INST_OPCLASS                       = 26;
 351     static const uint8_t INST_LOAD                          = 25;
 352     static const uint8_t INST_STORE                         = 24;
 353     static const uint8_t INST_CONTROL                       = 23;
 354     static const uint8_t INST_NONSPEC                       = 22;
 355     static const uint8_t INST_DEST_REGS                     = 18;
 356     static const uint8_t INST_SRC_REGS                      = 14;
 357     static const uint8_t INST_SPLIT_DATA                    = 13;
 358
 359     inline SkedID genSkedID(DynInstPtr inst)
 360     {
 361         SkedID id = 0;
 362         id = (inst->opClass() << INST_OPCLASS) |
 363             (inst->isLoad() << INST_LOAD) |
 364             (inst->isStore() << INST_STORE) |
 365             (inst->isControl() << INST_CONTROL) |
 366             (inst->isNonSpeculative() << INST_NONSPEC) |
 367             (inst->numDestRegs() << INST_DEST_REGS) |
 368             (inst->numSrcRegs() << INST_SRC_REGS) |
 369             (inst->splitInst << INST_SPLIT_DATA);
 370         return id;
 371     }
 372
 373     ThePipeline::RSkedPtr createFrontEndSked();
 374     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 375
 376     class StageScheduler {
 377       private:
 378         ThePipeline::RSkedPtr rsked;
 379         int stageNum;
 380         int nextTaskPriority;
 381
 382       public:
 383         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 384             : rsked(_rsked), stageNum(stage_num),
 385               nextTaskPriority(0)
 386         { }
 387
 388         void needs(int unit, int request) {
 389             rsked->push(new ScheduleEntry(
 390                             stageNum, nextTaskPriority++, unit, request
 391                             ));
 392         }
 393
 394         void needs(int unit, int request, int param) {
 395             rsked->push(new ScheduleEntry(
 396                             stageNum, nextTaskPriority++, unit, request, param
 397                             ));
 398         }
 399     };
 400
 401   public:
 402
 403     /** Registers statistics. */
 404     void regStats();
 405
 406     /** Ticks CPU, calling tick() on each stage, and checking the overall
 407      *  activity to see if the CPU should deschedule itself.
 408      */
 409     void tick();
 410
 411     /** Initialize the CPU */
 412     void init();
 413
 414     /** Get a Memory Port */
 415     Port* getPort(const std::string &if_name, int idx = 0);
 416
 417 #if FULL_SYSTEM
 418     /** HW return from error interrupt. */
 419     Fault hwrei(ThreadID tid);
 420
 421     bool simPalCheck(int palFunc, ThreadID tid);
 422
 423     /** Returns the Fault for any valid interrupt. */
 424     Fault getInterrupts();
 425
 426     /** Processes any an interrupt fault. */
 427     void processInterrupts(Fault interrupt);
 428
 429     /** Halts the CPU. */
 430     void halt() { panic("Halt not implemented!\n"); }
 431
 432     /** Update the Virt and Phys ports of all ThreadContexts to
 433      * reflect change in memory connections. */
 434     void updateMemPorts();
 435
 436     /** Check if this address is a valid instruction address. */
 437     bool validInstAddr(Addr addr) { return true; }
 438
 439     /** Check if this address is a valid data address. */
 440     bool validDataAddr(Addr addr) { return true; }
 441 #else
 442     /** Schedule a syscall on the CPU */
 443     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 444                         int delay = 0);
 445
 446     /** Executes a syscall.*/
 447     void syscall(int64_t callnum, ThreadID tid);
 448 #endif
 449
 450     /** Schedule a trap on the CPU */
 451     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 452
 453     /** Perform trap to Handle Given Fault */
 454     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 455
 456     /** Schedule thread activation on the CPU */
 457     void activateContext(ThreadID tid, int delay = 0);
 458
 459     /** Add Thread to Active Threads List. */
 460     void activateThread(ThreadID tid);
 461
 462     /** Activate Thread In Each Pipeline Stage */
 463     void activateThreadInPipeline(ThreadID tid);
 464
 465     /** Schedule Thread Activation from Ready List */
 466     void activateNextReadyContext(int delay = 0);
 467
 468     /** Add Thread From Ready List to Active Threads List. */
 469     void activateNextReadyThread();
 470
 471     /** Schedule a thread deactivation on the CPU */
 472     void deactivateContext(ThreadID tid, int delay = 0);
 473
 474     /** Remove from Active Thread List */
 475     void deactivateThread(ThreadID tid);
 476
 477     /** Schedule a thread suspension on the CPU */
 478     void suspendContext(ThreadID tid, int delay = 0);
 479
 480     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 481     void suspendThread(ThreadID tid);
 482
 483     /** Schedule a thread halt on the CPU */
 484     void haltContext(ThreadID tid, int delay = 0);
 485
 486     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 487      *  Threads List
 488      */
 489     void haltThread(ThreadID tid);
 490
 491     /** squashFromMemStall() - sets up a squash event
 492      *  squashDueToMemStall() - squashes pipeline
 493      *  @note: maybe squashContext/squashThread would be better?
 494      */
 495     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 496     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 497
 498     void removePipelineStalls(ThreadID tid);
 499     void squashThreadInPipeline(ThreadID tid);
 500     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 501
 502     PipelineStage* getPipeStage(int stage_num);
 503
 504     int
 505     contextId()
 506     {
 507         hack_once("return a bogus context id");
 508         return 0;
 509     }
 510
 511     /** Update The Order In Which We Process Threads. */
 512     void updateThreadPriority();
 513
 514     /** Switches a Pipeline Stage to Active. (Unused currently) */
 515     void switchToActive(int stage_idx)
 516     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 517
 518     /** Get the current instruction sequence number, and increment it. */
 519     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 520     { return globalSeqNum[tid]++; }
 521
 522     /** Get the current instruction sequence number, and increment it. */
 523     InstSeqNum nextInstSeqNum(ThreadID tid)
 524     { return globalSeqNum[tid]; }
 525
 526     /** Increment Instruction Sequence Number */
 527     void incrInstSeqNum(ThreadID tid)
 528     { globalSeqNum[tid]++; }
 529
 530     /** Set Instruction Sequence Number */
 531     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 532     {
 533         globalSeqNum[tid] = seq_num;
 534     }
 535
 536     /** Get & Update Next Event Number */
 537     InstSeqNum getNextEventNum()
 538     {
 539 #ifdef DEBUG
 540         return cpuEventNum++;
 541 #else
 542         return 0;
 543 #endif
 544     }
 545
 546     /** Register file accessors  */
 547     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 548
 549     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 550
 551     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 552
 553     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 554
 555     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 556
 557     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 558
 559     RegType inline getRegType(RegIndex reg_idx)
 560     {
 561         if (reg_idx < TheISA::FP_Base_DepTag)
 562             return IntType;
 563         else if (reg_idx < TheISA::Ctrl_Base_DepTag)
 564             return FloatType;
 565         else
 566             return MiscType;
 567     }
 568
 569     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 570
 571     /** Reads a miscellaneous register. */
 572     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 573
 574     /** Reads a misc. register, including any side effects the read
 575      * might have as defined by the architecture.
 576      */
 577     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 578
 579     /** Sets a miscellaneous register. */
 580     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 581                             ThreadID tid = 0);
 582
 583     /** Sets a misc. register, including any side effects the write
 584      * might have as defined by the architecture.
 585      */
 586     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 587
 588     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 589      *  target thread
 590      */
 591     uint64_t readRegOtherThread(unsigned misc_reg,
 592                                 ThreadID tid = InvalidThreadID);
 593
 594     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 595      * target thread
 596      */
 597     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 598                            ThreadID tid);
 599
 600     /** Reads the commit PC of a specific thread. */
 601     TheISA::PCState
 602     pcState(ThreadID tid)
 603     {
 604         return pc[tid];
 605     }
 606
 607     /** Sets the commit PC of a specific thread. */
 608     void
 609     pcState(const TheISA::PCState &newPC, ThreadID tid)
 610     {
 611         pc[tid] = newPC;
 612     }
 613
 614     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 615     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 616     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 617
 618     /** Function to add instruction onto the head of the list of the
 619      *  instructions.  Used when new instructions are fetched.
 620      */
 621     ListIt addInst(DynInstPtr inst);
 622
 623     /** Find instruction on instruction list */
 624     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 625
 626     /** Function to tell the CPU that an instruction has completed. */
 627     void instDone(DynInstPtr inst, ThreadID tid);
 628
 629     /** Add Instructions to the CPU Remove List*/
 630     void addToRemoveList(DynInstPtr inst);
 631
 632     /** Remove an instruction from CPU */
 633     void removeInst(DynInstPtr inst);
 634
 635     /** Remove all instructions younger than the given sequence number. */
 636     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 637
 638     /** Removes the instruction pointed to by the iterator. */
 639     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 640
 641     /** Cleans up all instructions on the instruction remove list. */
 642     void cleanUpRemovedInsts();
 643
 644     /** Cleans up all events on the CPU event remove list. */
 645     void cleanUpRemovedEvents();
 646
 647     /** Debug function to print all instructions on the list. */
 648     void dumpInsts();
 649
 650     /** Forwards an instruction read to the appropriate data
 651      *  resource (indexes into Resource Pool thru "dataPortIdx")
 652      */
 653     Fault read(DynInstPtr inst, Addr addr,
 654                uint8_t *data, unsigned size, unsigned flags);
 655
 656     /** Forwards an instruction write. to the appropriate data
 657      *  resource (indexes into Resource Pool thru "dataPortIdx")
 658      */
 659     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 660                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 661
 662   public:
 663     /** Per-Thread List of all the instructions in flight. */
 664     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 665
 666     /** List of all the instructions that will be removed at the end of this
 667      *  cycle.
 668      */
 669     std::queue<ListIt> removeList;
 670
 671     /** List of all the cpu event requests that will be removed at the end of
 672      *  the current cycle.
 673      */
 674     std::queue<Event*> cpuEventRemoveList;
 675
 676     /** Records if instructions need to be removed this cycle due to
 677      *  being retired or squashed.
 678      */
 679     bool removeInstsThisCycle;
 680
 681     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 682      * execution unit know, NOT to execute while the instruction is active.
 683      */
 684     bool nonSpecInstActive[ThePipeline::MaxThreads];
 685
 686     /** Instruction Seq. Num of current non-speculative instruction. */
 687     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 688
 689     /** Instruction Seq. Num of last instruction squashed in pipeline */
 690     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 691
 692     /** Last Cycle that the CPU squashed instruction end. */
 693     Tick lastSquashCycle[ThePipeline::MaxThreads];
 694
 695     std::list<ThreadID> fetchPriorityList;
 696
 697   protected:
 698     /** Active Threads List */
 699     std::list<ThreadID> activeThreads;
 700
 701     /** Ready Threads List */
 702     std::list<ThreadID> readyThreads;
 703
 704     /** Suspended Threads List */
 705     std::list<ThreadID> suspendedThreads;
 706
 707     /** Halted Threads List */
 708     std::list<ThreadID> haltedThreads;
 709
 710     /** Thread Status Functions */
 711     bool isThreadActive(ThreadID tid);
 712     bool isThreadReady(ThreadID tid);
 713     bool isThreadSuspended(ThreadID tid);
 714
 715   private:
 716     /** The activity recorder; used to tell if the CPU has any
 717      * activity remaining or if it can go to idle and deschedule
 718      * itself.
 719      */
 720     ActivityRecorder activityRec;
 721
 722   public:
 723     /** Number of Active Threads in the CPU */
 724     ThreadID numActiveThreads() { return activeThreads.size(); }
 725
 726     /** Thread id of active thread
 727      *  Only used for SwitchOnCacheMiss model.
 728      *  Assumes only 1 thread active
 729      */
 730     ThreadID activeThreadId()
 731     {
 732         if (numActiveThreads() > 0)
 733             return activeThreads.front();
 734         else
 735             return InvalidThreadID;
 736     }
 737
 738
 739     /** Records that there was time buffer activity this cycle. */
 740     void activityThisCycle() { activityRec.activity(); }
 741
 742     /** Changes a stage's status to active within the activity recorder. */
 743     void activateStage(const int idx)
 744     { activityRec.activateStage(idx); }
 745
 746     /** Changes a stage's status to inactive within the activity recorder. */
 747     void deactivateStage(const int idx)
 748     { activityRec.deactivateStage(idx); }
 749
 750     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 751     void wakeCPU();
 752
 753 #if FULL_SYSTEM
 754     virtual void wakeup();
 755 #endif
 756
 757     // LL/SC debug functionality
 758     unsigned stCondFails;
 759
 760     unsigned readStCondFailures()
 761     { return stCondFails; }
 762
 763     unsigned setStCondFailures(unsigned st_fails)
 764     { return stCondFails = st_fails; }
 765
 766     /** Returns a pointer to a thread context. */
 767     ThreadContext *tcBase(ThreadID tid = 0)
 768     {
 769         return thread[tid]->getTC();
 770     }
 771
 772     /** Count the Total Instructions Committed in the CPU. */
 773     virtual Counter totalInstructions() const
 774     {
 775         Counter total(0);
 776
 777         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 778             total += thread[tid]->numInst;
 779
 780         return total;
 781     }
 782
 783 #if FULL_SYSTEM
 784     /** Pointer to the system. */
 785     System *system;
 786
 787     /** Pointer to physical memory. */
 788     PhysicalMemory *physmem;
 789 #endif
 790
 791     /** The global sequence number counter. */
 792     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 793
 794 #ifdef DEBUG
 795     /** The global event number counter. */
 796     InstSeqNum cpuEventNum;
 797
 798     /** Number of resource requests active in CPU **/
 799     unsigned resReqCount;
 800 #endif
 801
 802     /** Counter of how many stages have completed switching out. */
 803     int switchCount;
 804
 805     /** Pointers to all of the threads in the CPU. */
 806     std::vector<Thread *> thread;
 807
 808     /** Pointer to the icache interface. */
 809     MemInterface *icacheInterface;
 810
 811     /** Pointer to the dcache interface. */
 812     MemInterface *dcacheInterface;
 813
 814     /** Whether or not the CPU should defer its registration. */
 815     bool deferRegistration;
 816
 817     /** Per-Stage Instruction Tracing */
 818     bool stageTracing;
 819
 820     /** The cycle that the CPU was last running, used for statistics. */
 821     Tick lastRunningCycle;
 822
 823     void updateContextSwitchStats();
 824     unsigned instsPerSwitch;
 825     Stats::Average instsPerCtxtSwitch;
 826     Stats::Scalar numCtxtSwitches;
 827
 828     /** Update Thread , used for statistic purposes*/
 829     inline void tickThreadStats();
 830
 831     /** Per-Thread Tick */
 832     Stats::Vector threadCycles;
 833
 834     /** Tick for SMT */
 835     Stats::Scalar smtCycles;
 836
 837     /** Stat for total number of times the CPU is descheduled. */
 838     Stats::Scalar timesIdled;
 839
 840     /** Stat for total number of cycles the CPU spends descheduled or no
 841      *  stages active.
 842      */
 843     Stats::Scalar idleCycles;
 844
 845     /** Stat for total number of cycles the CPU is active. */
 846     Stats::Scalar runCycles;
 847
 848     /** Percentage of cycles a stage was active */
 849     Stats::Formula activity;
 850
 851     /** Instruction Mix Stats */
 852     Stats::Scalar comLoads;
 853     Stats::Scalar comStores;
 854     Stats::Scalar comBranches;
 855     Stats::Scalar comNops;
 856     Stats::Scalar comNonSpec;
 857     Stats::Scalar comInts;
 858     Stats::Scalar comFloats;
 859
 860     /** Stat for the number of committed instructions per thread. */
 861     Stats::Vector committedInsts;
 862
 863     /** Stat for the number of committed instructions per thread. */
 864     Stats::Vector smtCommittedInsts;
 865
 866     /** Stat for the total number of committed instructions. */
 867     Stats::Scalar totalCommittedInsts;
 868
 869     /** Stat for the CPI per thread. */
 870     Stats::Formula cpi;
 871
 872     /** Stat for the SMT-CPI per thread. */
 873     Stats::Formula smtCpi;
 874
 875     /** Stat for the total CPI. */
 876     Stats::Formula totalCpi;
 877
 878     /** Stat for the IPC per thread. */
 879     Stats::Formula ipc;
 880
 881     /** Stat for the total IPC. */
 882     Stats::Formula smtIpc;
 883
 884     /** Stat for the total IPC. */
 885     Stats::Formula totalIpc;
 886 };
 887
 888 #endif // __CPU_O3_CPU_HH__