src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/types.hh"
  43 #include "arch/registers.hh"
  44 #include "base/statistics.hh"
  45 #include "cpu/timebuf.hh"
  46 #include "base/types.hh"
  47 #include "config/full_system.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/activity.hh"
  50 #include "cpu/base.hh"
  51 #include "cpu/simple_thread.hh"
  52 #include "cpu/inorder/inorder_dyn_inst.hh"
  53 #include "cpu/inorder/pipeline_traits.hh"
  54 #include "cpu/inorder/pipeline_stage.hh"
  55 #include "cpu/inorder/thread_state.hh"
  56 #include "cpu/inorder/reg_dep_map.hh"
  57 #include "cpu/o3/dep_graph.hh"
  58 #include "cpu/o3/rename_map.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83
  84     //DynInstPtr TypeDefs
  85     typedef ThePipeline::DynInstPtr DynInstPtr;
  86     typedef std::list<DynInstPtr>::iterator ListIt;
  87
  88     //TimeBuffer TypeDefs
  89     typedef TimeBuffer<InterStageStruct> StageQueue;
  90
  91     friend class Resource;
  92
  93   public:
  94     /** Constructs a CPU with the given parameters. */
  95     InOrderCPU(Params *params);
  96     /* Destructor */
  97     ~InOrderCPU();
  98
  99     /** CPU ID */
 100     int cpu_id;
 101
 102     // SE Mode ASIDs
 103     ThreadID asid[ThePipeline::MaxThreads];
 104
 105     /** Type of core that this is */
 106     std::string coreType;
 107
 108     // Only need for SE MODE
 109     enum ThreadModel {
 110         Single,
 111         SMT,
 112         SwitchOnCacheMiss
 113     };
 114
 115     ThreadModel threadModel;
 116
 117     int readCpuId() { return cpu_id; }
 118
 119     void setCpuId(int val) { cpu_id = val; }
 120
 121     Params *cpu_params;
 122
 123   public:
 124     enum Status {
 125         Running,
 126         Idle,
 127         Halted,
 128         Blocked,
 129         SwitchedOut
 130     };
 131
 132     /** Overall CPU status. */
 133     Status _status;
 134   private:
 135     /** Define TickEvent for the CPU */
 136     class TickEvent : public Event
 137     {
 138       private:
 139         /** Pointer to the CPU. */
 140         InOrderCPU *cpu;
 141
 142       public:
 143         /** Constructs a tick event. */
 144         TickEvent(InOrderCPU *c);
 145
 146         /** Processes a tick event, calling tick() on the CPU. */
 147         void process();
 148
 149         /** Returns the description of the tick event. */
 150         const char *description();
 151     };
 152
 153     /** The tick event used for scheduling CPU ticks. */
 154     TickEvent tickEvent;
 155
 156     /** Schedule tick event, regardless of its current state. */
 157     void scheduleTickEvent(int delay)
 158     {
 159         assert(!tickEvent.scheduled() || tickEvent.squashed());
 160         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 161     }
 162
 163     /** Unschedule tick event, regardless of its current state. */
 164     void unscheduleTickEvent()
 165     {
 166         if (tickEvent.scheduled())
 167             tickEvent.squash();
 168     }
 169
 170   public:
 171     // List of Events That can be scheduled from
 172     // within the CPU.
 173     // NOTE(1): The Resource Pool also uses this event list
 174     // to schedule events broadcast to all resources interfaces
 175     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 176     // pool event.
 177     enum CPUEventType {
 178         ActivateThread,
 179         ActivateNextReadyThread,
 180         DeactivateThread,
 181         HaltThread,
 182         SuspendThread,
 183         Trap,
 184         InstGraduated,
 185         SquashFromMemStall,
 186         UpdatePCs,
 187         NumCPUEvents
 188     };
 189
 190     static std::string eventNames[NumCPUEvents];
 191
 192     /** Define CPU Event */
 193     class CPUEvent : public Event
 194     {
 195       protected:
 196         InOrderCPU *cpu;
 197
 198       public:
 199         CPUEventType cpuEventType;
 200         ThreadID tid;
 201         DynInstPtr inst;
 202         Fault fault;
 203         unsigned vpe;
 204
 205       public:
 206         /** Constructs a CPU event. */
 207         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 208                  ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
 209
 210         /** Set Type of Event To Be Scheduled */
 211         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 212                       DynInstPtr _inst)
 213         {
 214             fault = _fault;
 215             cpuEventType = e_type;
 216             tid = _tid;
 217             inst = _inst;
 218             vpe = 0;
 219         }
 220
 221         /** Processes a CPU event. */
 222         void process();
 223
 224         /** Returns the description of the CPU event. */
 225         const char *description();
 226
 227         /** Schedule Event */
 228         void scheduleEvent(int delay);
 229
 230         /** Unschedule This Event */
 231         void unscheduleEvent();
 232     };
 233
 234     /** Schedule a CPU Event */
 235     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 236                           DynInstPtr inst, unsigned delay = 0,
 237                           unsigned event_pri_offset = 0);
 238
 239   public:
 240     /** Interface between the CPU and CPU resources. */
 241     ResourcePool *resPool;
 242
 243     /** Instruction used to signify that there is no *real* instruction in
 244         buffer slot */
 245     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 246     DynInstPtr dummyBufferInst;
 247     DynInstPtr dummyReqInst;
 248
 249     /** Used by resources to signify a denied access to a resource. */
 250     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 251
 252     /** Identifies the resource id that identifies a fetch
 253      * access unit.
 254      */
 255     unsigned fetchPortIdx;
 256
 257     /** Identifies the resource id that identifies a ITB       */
 258     unsigned itbIdx;
 259
 260     /** Identifies the resource id that identifies a data
 261      * access unit.
 262      */
 263     unsigned dataPortIdx;
 264
 265     /** Identifies the resource id that identifies a DTB       */
 266     unsigned dtbIdx;
 267
 268     /** The Pipeline Stages for the CPU */
 269     PipelineStage *pipelineStage[ThePipeline::NumStages];
 270
 271     /** Width (processing bandwidth) of each stage */
 272     int stageWidth;
 273
 274     /** Program Counters */
 275     TheISA::PCState pc[ThePipeline::MaxThreads];
 276
 277     /** The Register File for the CPU */
 278     union {
 279         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 280         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 281     } floatRegs;
 282     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 283
 284     /** ISA state */
 285     TheISA::ISA isa[ThePipeline::MaxThreads];
 286
 287     /** Dependency Tracker for Integer & Floating Point Regs */
 288     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 289
 290     /** Global communication structure */
 291     TimeBuffer<TimeStruct> timeBuffer;
 292
 293     /** Communication structure that sits in between pipeline stages */
 294     StageQueue *stageQueue[ThePipeline::NumStages-1];
 295
 296     TheISA::TLB *getITBPtr();
 297     TheISA::TLB *getDTBPtr();
 298
 299     /** Accessor Type for the SkedCache */
 300     typedef uint32_t SkedID;
 301
 302     /** Cache of Instruction Schedule using the instruction's name as a key */
 303     static std::map<SkedID, ThePipeline::RSkedPtr> skedCache;
 304
 305     typedef std::map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 306
 307     /** Initialized to last iterator in map, signifying a invalid entry
 308         on map searches
 309     */
 310     SkedCacheIt endOfSkedIt;
 311
 312     ThePipeline::RSkedPtr frontEndSked;
 313
 314     /** Add a new instruction schedule to the schedule cache */
 315     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 316     {
 317         SkedID sked_id = genSkedID(inst);
 318         assert(skedCache.find(sked_id) == skedCache.end());
 319         skedCache[sked_id] = inst_sked;
 320     }
 321
 322
 323     /** Find a instruction schedule */
 324     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 325     {
 326         SkedID sked_id = genSkedID(inst);
 327         SkedCacheIt lookup_it = skedCache.find(sked_id);
 328
 329         if (lookup_it != endOfSkedIt) {
 330             return (*lookup_it).second;
 331         } else {
 332             return NULL;
 333         }
 334     }
 335
 336     static const uint8_t INST_OPCLASS                       = 26;
 337     static const uint8_t INST_LOAD                          = 25;
 338     static const uint8_t INST_STORE                         = 24;
 339     static const uint8_t INST_CONTROL                       = 23;
 340     static const uint8_t INST_NONSPEC                       = 22;
 341     static const uint8_t INST_DEST_REGS                     = 18;
 342     static const uint8_t INST_SRC_REGS                      = 14;
 343
 344     inline SkedID genSkedID(DynInstPtr inst)
 345     {
 346         SkedID id = 0;
 347         id = (inst->opClass() << INST_OPCLASS) |
 348             (inst->isLoad() << INST_LOAD) |
 349             (inst->isStore() << INST_STORE) |
 350             (inst->isControl() << INST_CONTROL) |
 351             (inst->isNonSpeculative() << INST_NONSPEC) |
 352             (inst->numDestRegs() << INST_DEST_REGS) |
 353             (inst->numSrcRegs() << INST_SRC_REGS);
 354         return id;
 355     }
 356
 357     ThePipeline::RSkedPtr createFrontEndSked();
 358     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 359
 360     class StageScheduler {
 361       private:
 362         ThePipeline::RSkedPtr rsked;
 363         int stageNum;
 364         int nextTaskPriority;
 365
 366       public:
 367         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 368             : rsked(_rsked), stageNum(stage_num),
 369               nextTaskPriority(0)
 370         { }
 371
 372         void needs(int unit, int request) {
 373             rsked->push(new ScheduleEntry(
 374                             stageNum, nextTaskPriority++, unit, request
 375                             ));
 376         }
 377
 378         void needs(int unit, int request, int param) {
 379             rsked->push(new ScheduleEntry(
 380                             stageNum, nextTaskPriority++, unit, request, param
 381                             ));
 382         }
 383     };
 384
 385   public:
 386
 387     /** Registers statistics. */
 388     void regStats();
 389
 390     /** Ticks CPU, calling tick() on each stage, and checking the overall
 391      *  activity to see if the CPU should deschedule itself.
 392      */
 393     void tick();
 394
 395     /** Initialize the CPU */
 396     void init();
 397
 398     /** Get a Memory Port */
 399     Port* getPort(const std::string &if_name, int idx = 0);
 400
 401 #if FULL_SYSTEM
 402     /** HW return from error interrupt. */
 403     Fault hwrei(ThreadID tid);
 404
 405     bool simPalCheck(int palFunc, ThreadID tid);
 406
 407     /** Returns the Fault for any valid interrupt. */
 408     Fault getInterrupts();
 409
 410     /** Processes any an interrupt fault. */
 411     void processInterrupts(Fault interrupt);
 412
 413     /** Halts the CPU. */
 414     void halt() { panic("Halt not implemented!\n"); }
 415
 416     /** Update the Virt and Phys ports of all ThreadContexts to
 417      * reflect change in memory connections. */
 418     void updateMemPorts();
 419
 420     /** Check if this address is a valid instruction address. */
 421     bool validInstAddr(Addr addr) { return true; }
 422
 423     /** Check if this address is a valid data address. */
 424     bool validDataAddr(Addr addr) { return true; }
 425 #endif
 426
 427     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 428      *  trapCPU() - Traps to handle given fault
 429      */
 430     void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 431     void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
 432
 433     /** Add Thread to Active Threads List. */
 434     void activateContext(ThreadID tid, int delay = 0);
 435     void activateThread(ThreadID tid);
 436     void activateThreadInPipeline(ThreadID tid);
 437
 438     /** Add Thread to Active Threads List. */
 439     void activateNextReadyContext(int delay = 0);
 440     void activateNextReadyThread();
 441
 442     /** Remove from Active Thread List */
 443     void deactivateContext(ThreadID tid, int delay = 0);
 444     void deactivateThread(ThreadID tid);
 445
 446     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 447     void suspendContext(ThreadID tid, int delay = 0);
 448     void suspendThread(ThreadID tid);
 449
 450     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 451      *  Threads List
 452      */
 453     void haltContext(ThreadID tid, int delay = 0);
 454     void haltThread(ThreadID tid);
 455
 456     /** squashFromMemStall() - sets up a squash event
 457      *  squashDueToMemStall() - squashes pipeline
 458      *  @note: maybe squashContext/squashThread would be better?
 459      */
 460     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 461     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 462
 463     void removePipelineStalls(ThreadID tid);
 464     void squashThreadInPipeline(ThreadID tid);
 465     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 466
 467     PipelineStage* getPipeStage(int stage_num);
 468
 469     int
 470     contextId()
 471     {
 472         hack_once("return a bogus context id");
 473         return 0;
 474     }
 475
 476     /** Update The Order In Which We Process Threads. */
 477     void updateThreadPriority();
 478
 479     /** Switches a Pipeline Stage to Active. (Unused currently) */
 480     void switchToActive(int stage_idx)
 481     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 482
 483     /** Get the current instruction sequence number, and increment it. */
 484     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 485     { return globalSeqNum[tid]++; }
 486
 487     /** Get the current instruction sequence number, and increment it. */
 488     InstSeqNum nextInstSeqNum(ThreadID tid)
 489     { return globalSeqNum[tid]; }
 490
 491     /** Increment Instruction Sequence Number */
 492     void incrInstSeqNum(ThreadID tid)
 493     { globalSeqNum[tid]++; }
 494
 495     /** Set Instruction Sequence Number */
 496     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 497     {
 498         globalSeqNum[tid] = seq_num;
 499     }
 500
 501     /** Get & Update Next Event Number */
 502     InstSeqNum getNextEventNum()
 503     {
 504 #ifdef DEBUG
 505         return cpuEventNum++;
 506 #else
 507         return 0;
 508 #endif
 509     }
 510
 511     /** Register file accessors  */
 512     uint64_t readIntReg(int reg_idx, ThreadID tid);
 513
 514     FloatReg readFloatReg(int reg_idx, ThreadID tid);
 515
 516     FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
 517
 518     void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 519
 520     void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
 521
 522     void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid);
 523
 524     /** Reads a miscellaneous register. */
 525     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 526
 527     /** Reads a misc. register, including any side effects the read
 528      * might have as defined by the architecture.
 529      */
 530     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 531
 532     /** Sets a miscellaneous register. */
 533     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 534                             ThreadID tid = 0);
 535
 536     /** Sets a misc. register, including any side effects the write
 537      * might have as defined by the architecture.
 538      */
 539     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 540
 541     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 542      *  target thread
 543      */
 544     uint64_t readRegOtherThread(unsigned misc_reg,
 545                                 ThreadID tid = InvalidThreadID);
 546
 547     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 548      * target thread
 549      */
 550     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 551                            ThreadID tid);
 552
 553     /** Reads the commit PC of a specific thread. */
 554     TheISA::PCState
 555     pcState(ThreadID tid)
 556     {
 557         return pc[tid];
 558     }
 559
 560     /** Sets the commit PC of a specific thread. */
 561     void
 562     pcState(const TheISA::PCState &newPC, ThreadID tid)
 563     {
 564         pc[tid] = newPC;
 565     }
 566
 567     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 568     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 569     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 570
 571     /** Function to add instruction onto the head of the list of the
 572      *  instructions.  Used when new instructions are fetched.
 573      */
 574     ListIt addInst(DynInstPtr &inst);
 575
 576     /** Function to tell the CPU that an instruction has completed. */
 577     void instDone(DynInstPtr inst, ThreadID tid);
 578
 579     /** Add Instructions to the CPU Remove List*/
 580     void addToRemoveList(DynInstPtr &inst);
 581
 582     /** Remove an instruction from CPU */
 583     void removeInst(DynInstPtr &inst);
 584
 585     /** Remove all instructions younger than the given sequence number. */
 586     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 587
 588     /** Removes the instruction pointed to by the iterator. */
 589     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 590
 591     /** Cleans up all instructions on the instruction remove list. */
 592     void cleanUpRemovedInsts();
 593
 594     /** Cleans up all events on the CPU event remove list. */
 595     void cleanUpRemovedEvents();
 596
 597     /** Debug function to print all instructions on the list. */
 598     void dumpInsts();
 599
 600     /** Forwards an instruction read to the appropriate data
 601      *  resource (indexes into Resource Pool thru "dataPortIdx")
 602      */
 603     Fault read(DynInstPtr inst, Addr addr,
 604                uint8_t *data, unsigned size, unsigned flags);
 605
 606     /** Forwards an instruction write. to the appropriate data
 607      *  resource (indexes into Resource Pool thru "dataPortIdx")
 608      */
 609     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 610                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 611
 612     /** Executes a syscall.*/
 613     void syscall(int64_t callnum, ThreadID tid);
 614
 615   public:
 616     /** Per-Thread List of all the instructions in flight. */
 617     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 618
 619     /** List of all the instructions that will be removed at the end of this
 620      *  cycle.
 621      */
 622     std::queue<ListIt> removeList;
 623
 624     /** List of all the cpu event requests that will be removed at the end of
 625      *  the current cycle.
 626      */
 627     std::queue<Event*> cpuEventRemoveList;
 628
 629     /** Records if instructions need to be removed this cycle due to
 630      *  being retired or squashed.
 631      */
 632     bool removeInstsThisCycle;
 633
 634     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 635      * execution unit know, NOT to execute while the instruction is active.
 636      */
 637     bool nonSpecInstActive[ThePipeline::MaxThreads];
 638
 639     /** Instruction Seq. Num of current non-speculative instruction. */
 640     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 641
 642     /** Instruction Seq. Num of last instruction squashed in pipeline */
 643     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 644
 645     /** Last Cycle that the CPU squashed instruction end. */
 646     Tick lastSquashCycle[ThePipeline::MaxThreads];
 647
 648     std::list<ThreadID> fetchPriorityList;
 649
 650   protected:
 651     /** Active Threads List */
 652     std::list<ThreadID> activeThreads;
 653
 654     /** Ready Threads List */
 655     std::list<ThreadID> readyThreads;
 656
 657     /** Suspended Threads List */
 658     std::list<ThreadID> suspendedThreads;
 659
 660     /** Halted Threads List */
 661     std::list<ThreadID> haltedThreads;
 662
 663     /** Thread Status Functions */
 664     bool isThreadActive(ThreadID tid);
 665     bool isThreadReady(ThreadID tid);
 666     bool isThreadSuspended(ThreadID tid);
 667
 668   private:
 669     /** The activity recorder; used to tell if the CPU has any
 670      * activity remaining or if it can go to idle and deschedule
 671      * itself.
 672      */
 673     ActivityRecorder activityRec;
 674
 675   public:
 676     /** Number of Active Threads in the CPU */
 677     ThreadID numActiveThreads() { return activeThreads.size(); }
 678
 679     /** Thread id of active thread
 680      *  Only used for SwitchOnCacheMiss model.
 681      *  Assumes only 1 thread active
 682      */
 683     ThreadID activeThreadId()
 684     {
 685         if (numActiveThreads() > 0)
 686             return activeThreads.front();
 687         else
 688             return InvalidThreadID;
 689     }
 690
 691
 692     /** Records that there was time buffer activity this cycle. */
 693     void activityThisCycle() { activityRec.activity(); }
 694
 695     /** Changes a stage's status to active within the activity recorder. */
 696     void activateStage(const int idx)
 697     { activityRec.activateStage(idx); }
 698
 699     /** Changes a stage's status to inactive within the activity recorder. */
 700     void deactivateStage(const int idx)
 701     { activityRec.deactivateStage(idx); }
 702
 703     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 704     void wakeCPU();
 705
 706 #if FULL_SYSTEM
 707     virtual void wakeup();
 708 #endif
 709
 710     // LL/SC debug functionality
 711     unsigned stCondFails;
 712
 713     unsigned readStCondFailures()
 714     { return stCondFails; }
 715
 716     unsigned setStCondFailures(unsigned st_fails)
 717     { return stCondFails = st_fails; }
 718
 719     /** Returns a pointer to a thread context. */
 720     ThreadContext *tcBase(ThreadID tid = 0)
 721     {
 722         return thread[tid]->getTC();
 723     }
 724
 725     /** Count the Total Instructions Committed in the CPU. */
 726     virtual Counter totalInstructions() const
 727     {
 728         Counter total(0);
 729
 730         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 731             total += thread[tid]->numInst;
 732
 733         return total;
 734     }
 735
 736 #if FULL_SYSTEM
 737     /** Pointer to the system. */
 738     System *system;
 739
 740     /** Pointer to physical memory. */
 741     PhysicalMemory *physmem;
 742 #endif
 743
 744     /** The global sequence number counter. */
 745     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 746
 747 #ifdef DEBUG
 748     /** The global event number counter. */
 749     InstSeqNum cpuEventNum;
 750
 751     /** Number of resource requests active in CPU **/
 752     unsigned resReqCount;
 753 #endif
 754
 755     /** Counter of how many stages have completed switching out. */
 756     int switchCount;
 757
 758     /** Pointers to all of the threads in the CPU. */
 759     std::vector<Thread *> thread;
 760
 761     /** Pointer to the icache interface. */
 762     MemInterface *icacheInterface;
 763
 764     /** Pointer to the dcache interface. */
 765     MemInterface *dcacheInterface;
 766
 767     /** Whether or not the CPU should defer its registration. */
 768     bool deferRegistration;
 769
 770     /** Per-Stage Instruction Tracing */
 771     bool stageTracing;
 772
 773     /** The cycle that the CPU was last running, used for statistics. */
 774     Tick lastRunningCycle;
 775
 776     void updateContextSwitchStats();
 777     unsigned instsPerSwitch;
 778     Stats::Average instsPerCtxtSwitch;
 779     Stats::Scalar numCtxtSwitches;
 780
 781     /** Update Thread , used for statistic purposes*/
 782     inline void tickThreadStats();
 783
 784     /** Per-Thread Tick */
 785     Stats::Vector threadCycles;
 786
 787     /** Tick for SMT */
 788     Stats::Scalar smtCycles;
 789
 790     /** Stat for total number of times the CPU is descheduled. */
 791     Stats::Scalar timesIdled;
 792
 793     /** Stat for total number of cycles the CPU spends descheduled or no
 794      *  stages active.
 795      */
 796     Stats::Scalar idleCycles;
 797
 798     /** Stat for total number of cycles the CPU is active. */
 799     Stats::Scalar runCycles;
 800
 801     /** Percentage of cycles a stage was active */
 802     Stats::Formula activity;
 803
 804     /** Instruction Mix Stats */
 805     Stats::Scalar comLoads;
 806     Stats::Scalar comStores;
 807     Stats::Scalar comBranches;
 808     Stats::Scalar comNops;
 809     Stats::Scalar comNonSpec;
 810     Stats::Scalar comInts;
 811     Stats::Scalar comFloats;
 812
 813     /** Stat for the number of committed instructions per thread. */
 814     Stats::Vector committedInsts;
 815
 816     /** Stat for the number of committed instructions per thread. */
 817     Stats::Vector smtCommittedInsts;
 818
 819     /** Stat for the total number of committed instructions. */
 820     Stats::Scalar totalCommittedInsts;
 821
 822     /** Stat for the CPI per thread. */
 823     Stats::Formula cpi;
 824
 825     /** Stat for the SMT-CPI per thread. */
 826     Stats::Formula smtCpi;
 827
 828     /** Stat for the total CPI. */
 829     Stats::Formula totalCpi;
 830
 831     /** Stat for the IPC per thread. */
 832     Stats::Formula ipc;
 833
 834     /** Stat for the total IPC. */
 835     Stats::Formula smtIpc;
 836
 837     /** Stat for the total IPC. */
 838     Stats::Formula totalIpc;
 839 };
 840
 841 #endif // __CPU_O3_CPU_HH__