src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/registers.hh"
  43 #include "arch/types.hh"
  44 #include "base/statistics.hh"
  45 #include "base/types.hh"
  46 #include "config/full_system.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/inorder/inorder_dyn_inst.hh"
  49 #include "cpu/inorder/pipeline_stage.hh"
  50 #include "cpu/inorder/pipeline_traits.hh"
  51 #include "cpu/inorder/reg_dep_map.hh"
  52 #include "cpu/inorder/thread_state.hh"
  53 #include "cpu/o3/dep_graph.hh"
  54 #include "cpu/o3/rename_map.hh"
  55 #include "cpu/activity.hh"
  56 #include "cpu/base.hh"
  57 #include "cpu/simple_thread.hh"
  58 #include "cpu/timebuf.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83     typedef TheISA::RegIndex RegIndex;
  84
  85     //DynInstPtr TypeDefs
  86     typedef ThePipeline::DynInstPtr DynInstPtr;
  87     typedef std::list<DynInstPtr>::iterator ListIt;
  88
  89     //TimeBuffer TypeDefs
  90     typedef TimeBuffer<InterStageStruct> StageQueue;
  91
  92     friend class Resource;
  93
  94   public:
  95     /** Constructs a CPU with the given parameters. */
  96     InOrderCPU(Params *params);
  97     /* Destructor */
  98     ~InOrderCPU();
  99
 100     /** CPU ID */
 101     int cpu_id;
 102
 103     // SE Mode ASIDs
 104     ThreadID asid[ThePipeline::MaxThreads];
 105
 106     /** Type of core that this is */
 107     std::string coreType;
 108
 109     // Only need for SE MODE
 110     enum ThreadModel {
 111         Single,
 112         SMT,
 113         SwitchOnCacheMiss
 114     };
 115
 116     ThreadModel threadModel;
 117
 118     int readCpuId() { return cpu_id; }
 119
 120     void setCpuId(int val) { cpu_id = val; }
 121
 122     Params *cpu_params;
 123
 124   public:
 125     enum Status {
 126         Running,
 127         Idle,
 128         Halted,
 129         Blocked,
 130         SwitchedOut
 131     };
 132
 133     /** Overall CPU status. */
 134     Status _status;
 135   private:
 136     /** Define TickEvent for the CPU */
 137     class TickEvent : public Event
 138     {
 139       private:
 140         /** Pointer to the CPU. */
 141         InOrderCPU *cpu;
 142
 143       public:
 144         /** Constructs a tick event. */
 145         TickEvent(InOrderCPU *c);
 146
 147         /** Processes a tick event, calling tick() on the CPU. */
 148         void process();
 149
 150         /** Returns the description of the tick event. */
 151         const char *description();
 152     };
 153
 154     /** The tick event used for scheduling CPU ticks. */
 155     TickEvent tickEvent;
 156
 157     /** Schedule tick event, regardless of its current state. */
 158     void scheduleTickEvent(int delay)
 159     {
 160         assert(!tickEvent.scheduled() || tickEvent.squashed());
 161         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 162     }
 163
 164     /** Unschedule tick event, regardless of its current state. */
 165     void unscheduleTickEvent()
 166     {
 167         if (tickEvent.scheduled())
 168             tickEvent.squash();
 169     }
 170
 171   public:
 172     // List of Events That can be scheduled from
 173     // within the CPU.
 174     // NOTE(1): The Resource Pool also uses this event list
 175     // to schedule events broadcast to all resources interfaces
 176     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 177     // pool event.
 178     enum CPUEventType {
 179         ActivateThread,
 180         ActivateNextReadyThread,
 181         DeactivateThread,
 182         HaltThread,
 183         SuspendThread,
 184         Trap,
 185         Syscall,
 186         SquashFromMemStall,
 187         UpdatePCs,
 188         NumCPUEvents
 189     };
 190
 191     static std::string eventNames[NumCPUEvents];
 192
 193     enum CPUEventPri {
 194         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 195         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 196         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 197     };
 198
 199     /** Define CPU Event */
 200     class CPUEvent : public Event
 201     {
 202       protected:
 203         InOrderCPU *cpu;
 204
 205       public:
 206         CPUEventType cpuEventType;
 207         ThreadID tid;
 208         DynInstPtr inst;
 209         Fault fault;
 210         unsigned vpe;
 211         short syscall_num;
 212
 213       public:
 214         /** Constructs a CPU event. */
 215         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 216                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 217
 218         /** Set Type of Event To Be Scheduled */
 219         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 220                       DynInstPtr _inst)
 221         {
 222             fault = _fault;
 223             cpuEventType = e_type;
 224             tid = _tid;
 225             inst = _inst;
 226             vpe = 0;
 227         }
 228
 229         /** Processes a CPU event. */
 230         void process();
 231
 232         /** Returns the description of the CPU event. */
 233         const char *description();
 234
 235         /** Schedule Event */
 236         void scheduleEvent(int delay);
 237
 238         /** Unschedule This Event */
 239         void unscheduleEvent();
 240     };
 241
 242     /** Schedule a CPU Event */
 243     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 244                           DynInstPtr inst, unsigned delay = 0,
 245                           CPUEventPri event_pri = InOrderCPU_Pri);
 246
 247   public:
 248     /** Interface between the CPU and CPU resources. */
 249     ResourcePool *resPool;
 250
 251     /** Instruction used to signify that there is no *real* instruction in
 252         buffer slot */
 253     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 254     DynInstPtr dummyBufferInst;
 255     DynInstPtr dummyReqInst;
 256
 257     /** Used by resources to signify a denied access to a resource. */
 258     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 259
 260     /** Identifies the resource id that identifies a fetch
 261      * access unit.
 262      */
 263     unsigned fetchPortIdx;
 264
 265     /** Identifies the resource id that identifies a data
 266      * access unit.
 267      */
 268     unsigned dataPortIdx;
 269
 270     /** The Pipeline Stages for the CPU */
 271     PipelineStage *pipelineStage[ThePipeline::NumStages];
 272
 273     /** Width (processing bandwidth) of each stage */
 274     int stageWidth;
 275
 276     /** Program Counters */
 277     TheISA::PCState pc[ThePipeline::MaxThreads];
 278
 279     /** Last Committed PC */
 280     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 281
 282     /** The Register File for the CPU */
 283     union {
 284         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 285         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 286     } floatRegs;
 287     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 288
 289     /** ISA state */
 290     TheISA::ISA isa[ThePipeline::MaxThreads];
 291
 292     /** Dependency Tracker for Integer & Floating Point Regs */
 293     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 294
 295     /** Register Types Used in Dependency Tracking */
 296     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 297
 298     /** Global communication structure */
 299     TimeBuffer<TimeStruct> timeBuffer;
 300
 301     /** Communication structure that sits in between pipeline stages */
 302     StageQueue *stageQueue[ThePipeline::NumStages-1];
 303
 304     TheISA::TLB *getITBPtr();
 305     TheISA::TLB *getDTBPtr();
 306
 307     /** Accessor Type for the SkedCache */
 308     typedef uint32_t SkedID;
 309
 310     /** Cache of Instruction Schedule using the instruction's name as a key */
 311     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 312
 313     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 314
 315     /** Initialized to last iterator in map, signifying a invalid entry
 316         on map searches
 317     */
 318     SkedCacheIt endOfSkedIt;
 319
 320     ThePipeline::RSkedPtr frontEndSked;
 321
 322     /** Add a new instruction schedule to the schedule cache */
 323     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 324     {
 325         SkedID sked_id = genSkedID(inst);
 326         assert(skedCache.find(sked_id) == skedCache.end());
 327         skedCache[sked_id] = inst_sked;
 328     }
 329
 330
 331     /** Find a instruction schedule */
 332     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 333     {
 334         SkedID sked_id = genSkedID(inst);
 335         SkedCacheIt lookup_it = skedCache.find(sked_id);
 336
 337         if (lookup_it != endOfSkedIt) {
 338             return (*lookup_it).second;
 339         } else {
 340             return NULL;
 341         }
 342     }
 343
 344     static const uint8_t INST_OPCLASS                       = 26;
 345     static const uint8_t INST_LOAD                          = 25;
 346     static const uint8_t INST_STORE                         = 24;
 347     static const uint8_t INST_CONTROL                       = 23;
 348     static const uint8_t INST_NONSPEC                       = 22;
 349     static const uint8_t INST_DEST_REGS                     = 18;
 350     static const uint8_t INST_SRC_REGS                      = 14;
 351     static const uint8_t INST_SPLIT_DATA                    = 13;
 352
 353     inline SkedID genSkedID(DynInstPtr inst)
 354     {
 355         SkedID id = 0;
 356         id = (inst->opClass() << INST_OPCLASS) |
 357             (inst->isLoad() << INST_LOAD) |
 358             (inst->isStore() << INST_STORE) |
 359             (inst->isControl() << INST_CONTROL) |
 360             (inst->isNonSpeculative() << INST_NONSPEC) |
 361             (inst->numDestRegs() << INST_DEST_REGS) |
 362             (inst->numSrcRegs() << INST_SRC_REGS) |
 363             (inst->splitInst << INST_SPLIT_DATA);
 364         return id;
 365     }
 366
 367     ThePipeline::RSkedPtr createFrontEndSked();
 368     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 369
 370     class StageScheduler {
 371       private:
 372         ThePipeline::RSkedPtr rsked;
 373         int stageNum;
 374         int nextTaskPriority;
 375
 376       public:
 377         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 378             : rsked(_rsked), stageNum(stage_num),
 379               nextTaskPriority(0)
 380         { }
 381
 382         void needs(int unit, int request) {
 383             rsked->push(new ScheduleEntry(
 384                             stageNum, nextTaskPriority++, unit, request
 385                             ));
 386         }
 387
 388         void needs(int unit, int request, int param) {
 389             rsked->push(new ScheduleEntry(
 390                             stageNum, nextTaskPriority++, unit, request, param
 391                             ));
 392         }
 393     };
 394
 395   public:
 396
 397     /** Registers statistics. */
 398     void regStats();
 399
 400     /** Ticks CPU, calling tick() on each stage, and checking the overall
 401      *  activity to see if the CPU should deschedule itself.
 402      */
 403     void tick();
 404
 405     /** Initialize the CPU */
 406     void init();
 407
 408     /** Get a Memory Port */
 409     Port* getPort(const std::string &if_name, int idx = 0);
 410
 411 #if FULL_SYSTEM
 412     /** HW return from error interrupt. */
 413     Fault hwrei(ThreadID tid);
 414
 415     bool simPalCheck(int palFunc, ThreadID tid);
 416
 417     /** Returns the Fault for any valid interrupt. */
 418     Fault getInterrupts();
 419
 420     /** Processes any an interrupt fault. */
 421     void processInterrupts(Fault interrupt);
 422
 423     /** Halts the CPU. */
 424     void halt() { panic("Halt not implemented!\n"); }
 425
 426     /** Update the Virt and Phys ports of all ThreadContexts to
 427      * reflect change in memory connections. */
 428     void updateMemPorts();
 429
 430     /** Check if this address is a valid instruction address. */
 431     bool validInstAddr(Addr addr) { return true; }
 432
 433     /** Check if this address is a valid data address. */
 434     bool validDataAddr(Addr addr) { return true; }
 435 #else
 436     /** Schedule a syscall on the CPU */
 437     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 438                         int delay = 0);
 439
 440     /** Executes a syscall.*/
 441     void syscall(int64_t callnum, ThreadID tid);
 442 #endif
 443
 444     /** Schedule a trap on the CPU */
 445     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 446
 447     /** Perform trap to Handle Given Fault */
 448     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 449
 450     /** Schedule thread activation on the CPU */
 451     void activateContext(ThreadID tid, int delay = 0);
 452
 453     /** Add Thread to Active Threads List. */
 454     void activateThread(ThreadID tid);
 455
 456     /** Activate Thread In Each Pipeline Stage */
 457     void activateThreadInPipeline(ThreadID tid);
 458
 459     /** Schedule Thread Activation from Ready List */
 460     void activateNextReadyContext(int delay = 0);
 461
 462     /** Add Thread From Ready List to Active Threads List. */
 463     void activateNextReadyThread();
 464
 465     /** Schedule a thread deactivation on the CPU */
 466     void deactivateContext(ThreadID tid, int delay = 0);
 467
 468     /** Remove from Active Thread List */
 469     void deactivateThread(ThreadID tid);
 470
 471     /** Schedule a thread suspension on the CPU */
 472     void suspendContext(ThreadID tid, int delay = 0);
 473
 474     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 475     void suspendThread(ThreadID tid);
 476
 477     /** Schedule a thread halt on the CPU */
 478     void haltContext(ThreadID tid, int delay = 0);
 479
 480     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 481      *  Threads List
 482      */
 483     void haltThread(ThreadID tid);
 484
 485     /** squashFromMemStall() - sets up a squash event
 486      *  squashDueToMemStall() - squashes pipeline
 487      *  @note: maybe squashContext/squashThread would be better?
 488      */
 489     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 490     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 491
 492     void removePipelineStalls(ThreadID tid);
 493     void squashThreadInPipeline(ThreadID tid);
 494     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 495
 496     PipelineStage* getPipeStage(int stage_num);
 497
 498     int
 499     contextId()
 500     {
 501         hack_once("return a bogus context id");
 502         return 0;
 503     }
 504
 505     /** Update The Order In Which We Process Threads. */
 506     void updateThreadPriority();
 507
 508     /** Switches a Pipeline Stage to Active. (Unused currently) */
 509     void switchToActive(int stage_idx)
 510     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 511
 512     /** Get the current instruction sequence number, and increment it. */
 513     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 514     { return globalSeqNum[tid]++; }
 515
 516     /** Get the current instruction sequence number, and increment it. */
 517     InstSeqNum nextInstSeqNum(ThreadID tid)
 518     { return globalSeqNum[tid]; }
 519
 520     /** Increment Instruction Sequence Number */
 521     void incrInstSeqNum(ThreadID tid)
 522     { globalSeqNum[tid]++; }
 523
 524     /** Set Instruction Sequence Number */
 525     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 526     {
 527         globalSeqNum[tid] = seq_num;
 528     }
 529
 530     /** Get & Update Next Event Number */
 531     InstSeqNum getNextEventNum()
 532     {
 533 #ifdef DEBUG
 534         return cpuEventNum++;
 535 #else
 536         return 0;
 537 #endif
 538     }
 539
 540     /** Register file accessors  */
 541     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 542
 543     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 544
 545     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 546
 547     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 548
 549     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 550
 551     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 552
 553     RegType inline getRegType(RegIndex reg_idx)
 554     {
 555         if (reg_idx < TheISA::FP_Base_DepTag)
 556             return IntType;
 557         else if (reg_idx < TheISA::Ctrl_Base_DepTag)
 558             return FloatType;
 559         else
 560             return MiscType;
 561     }
 562
 563     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 564
 565     /** Reads a miscellaneous register. */
 566     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 567
 568     /** Reads a misc. register, including any side effects the read
 569      * might have as defined by the architecture.
 570      */
 571     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 572
 573     /** Sets a miscellaneous register. */
 574     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 575                             ThreadID tid = 0);
 576
 577     /** Sets a misc. register, including any side effects the write
 578      * might have as defined by the architecture.
 579      */
 580     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 581
 582     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 583      *  target thread
 584      */
 585     uint64_t readRegOtherThread(unsigned misc_reg,
 586                                 ThreadID tid = InvalidThreadID);
 587
 588     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 589      * target thread
 590      */
 591     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 592                            ThreadID tid);
 593
 594     /** Reads the commit PC of a specific thread. */
 595     TheISA::PCState
 596     pcState(ThreadID tid)
 597     {
 598         return pc[tid];
 599     }
 600
 601     /** Sets the commit PC of a specific thread. */
 602     void
 603     pcState(const TheISA::PCState &newPC, ThreadID tid)
 604     {
 605         pc[tid] = newPC;
 606     }
 607
 608     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 609     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 610     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 611
 612     /** Function to add instruction onto the head of the list of the
 613      *  instructions.  Used when new instructions are fetched.
 614      */
 615     ListIt addInst(DynInstPtr inst);
 616
 617     /** Find instruction on instruction list */
 618     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 619
 620     /** Function to tell the CPU that an instruction has completed. */
 621     void instDone(DynInstPtr inst, ThreadID tid);
 622
 623     /** Add Instructions to the CPU Remove List*/
 624     void addToRemoveList(DynInstPtr inst);
 625
 626     /** Remove an instruction from CPU */
 627     void removeInst(DynInstPtr inst);
 628
 629     /** Remove all instructions younger than the given sequence number. */
 630     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 631
 632     /** Removes the instruction pointed to by the iterator. */
 633     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 634
 635     /** Cleans up all instructions on the instruction remove list. */
 636     void cleanUpRemovedInsts();
 637
 638     /** Cleans up all events on the CPU event remove list. */
 639     void cleanUpRemovedEvents();
 640
 641     /** Debug function to print all instructions on the list. */
 642     void dumpInsts();
 643
 644     /** Forwards an instruction read to the appropriate data
 645      *  resource (indexes into Resource Pool thru "dataPortIdx")
 646      */
 647     Fault read(DynInstPtr inst, Addr addr,
 648                uint8_t *data, unsigned size, unsigned flags);
 649
 650     /** Forwards an instruction write. to the appropriate data
 651      *  resource (indexes into Resource Pool thru "dataPortIdx")
 652      */
 653     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 654                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 655
 656   public:
 657     /** Per-Thread List of all the instructions in flight. */
 658     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 659
 660     /** List of all the instructions that will be removed at the end of this
 661      *  cycle.
 662      */
 663     std::queue<ListIt> removeList;
 664
 665     /** List of all the cpu event requests that will be removed at the end of
 666      *  the current cycle.
 667      */
 668     std::queue<Event*> cpuEventRemoveList;
 669
 670     /** Records if instructions need to be removed this cycle due to
 671      *  being retired or squashed.
 672      */
 673     bool removeInstsThisCycle;
 674
 675     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 676      * execution unit know, NOT to execute while the instruction is active.
 677      */
 678     bool nonSpecInstActive[ThePipeline::MaxThreads];
 679
 680     /** Instruction Seq. Num of current non-speculative instruction. */
 681     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 682
 683     /** Instruction Seq. Num of last instruction squashed in pipeline */
 684     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 685
 686     /** Last Cycle that the CPU squashed instruction end. */
 687     Tick lastSquashCycle[ThePipeline::MaxThreads];
 688
 689     std::list<ThreadID> fetchPriorityList;
 690
 691   protected:
 692     /** Active Threads List */
 693     std::list<ThreadID> activeThreads;
 694
 695     /** Ready Threads List */
 696     std::list<ThreadID> readyThreads;
 697
 698     /** Suspended Threads List */
 699     std::list<ThreadID> suspendedThreads;
 700
 701     /** Halted Threads List */
 702     std::list<ThreadID> haltedThreads;
 703
 704     /** Thread Status Functions */
 705     bool isThreadActive(ThreadID tid);
 706     bool isThreadReady(ThreadID tid);
 707     bool isThreadSuspended(ThreadID tid);
 708
 709   private:
 710     /** The activity recorder; used to tell if the CPU has any
 711      * activity remaining or if it can go to idle and deschedule
 712      * itself.
 713      */
 714     ActivityRecorder activityRec;
 715
 716   public:
 717     /** Number of Active Threads in the CPU */
 718     ThreadID numActiveThreads() { return activeThreads.size(); }
 719
 720     /** Thread id of active thread
 721      *  Only used for SwitchOnCacheMiss model.
 722      *  Assumes only 1 thread active
 723      */
 724     ThreadID activeThreadId()
 725     {
 726         if (numActiveThreads() > 0)
 727             return activeThreads.front();
 728         else
 729             return InvalidThreadID;
 730     }
 731
 732
 733     /** Records that there was time buffer activity this cycle. */
 734     void activityThisCycle() { activityRec.activity(); }
 735
 736     /** Changes a stage's status to active within the activity recorder. */
 737     void activateStage(const int idx)
 738     { activityRec.activateStage(idx); }
 739
 740     /** Changes a stage's status to inactive within the activity recorder. */
 741     void deactivateStage(const int idx)
 742     { activityRec.deactivateStage(idx); }
 743
 744     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 745     void wakeCPU();
 746
 747 #if FULL_SYSTEM
 748     virtual void wakeup();
 749 #endif
 750
 751     // LL/SC debug functionality
 752     unsigned stCondFails;
 753
 754     unsigned readStCondFailures()
 755     { return stCondFails; }
 756
 757     unsigned setStCondFailures(unsigned st_fails)
 758     { return stCondFails = st_fails; }
 759
 760     /** Returns a pointer to a thread context. */
 761     ThreadContext *tcBase(ThreadID tid = 0)
 762     {
 763         return thread[tid]->getTC();
 764     }
 765
 766     /** Count the Total Instructions Committed in the CPU. */
 767     virtual Counter totalInstructions() const
 768     {
 769         Counter total(0);
 770
 771         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 772             total += thread[tid]->numInst;
 773
 774         return total;
 775     }
 776
 777 #if FULL_SYSTEM
 778     /** Pointer to the system. */
 779     System *system;
 780 #endif
 781
 782     /** The global sequence number counter. */
 783     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 784
 785 #ifdef DEBUG
 786     /** The global event number counter. */
 787     InstSeqNum cpuEventNum;
 788
 789     /** Number of resource requests active in CPU **/
 790     unsigned resReqCount;
 791 #endif
 792
 793     Addr lockAddr;
 794
 795     /** Temporary fix for the lock flag, works in the UP case. */
 796     bool lockFlag;
 797
 798     /** Counter of how many stages have completed draining */
 799     int drainCount;
 800
 801     /** Pointers to all of the threads in the CPU. */
 802     std::vector<Thread *> thread;
 803
 804     /** Pointer to the icache interface. */
 805     MemInterface *icacheInterface;
 806
 807     /** Pointer to the dcache interface. */
 808     MemInterface *dcacheInterface;
 809
 810     /** Whether or not the CPU should defer its registration. */
 811     bool deferRegistration;
 812
 813     /** Per-Stage Instruction Tracing */
 814     bool stageTracing;
 815
 816     /** The cycle that the CPU was last running, used for statistics. */
 817     Tick lastRunningCycle;
 818
 819     void updateContextSwitchStats();
 820     unsigned instsPerSwitch;
 821     Stats::Average instsPerCtxtSwitch;
 822     Stats::Scalar numCtxtSwitches;
 823
 824     /** Update Thread , used for statistic purposes*/
 825     inline void tickThreadStats();
 826
 827     /** Per-Thread Tick */
 828     Stats::Vector threadCycles;
 829
 830     /** Tick for SMT */
 831     Stats::Scalar smtCycles;
 832
 833     /** Stat for total number of times the CPU is descheduled. */
 834     Stats::Scalar timesIdled;
 835
 836     /** Stat for total number of cycles the CPU spends descheduled or no
 837      *  stages active.
 838      */
 839     Stats::Scalar idleCycles;
 840
 841     /** Stat for total number of cycles the CPU is active. */
 842     Stats::Scalar runCycles;
 843
 844     /** Percentage of cycles a stage was active */
 845     Stats::Formula activity;
 846
 847     /** Instruction Mix Stats */
 848     Stats::Scalar comLoads;
 849     Stats::Scalar comStores;
 850     Stats::Scalar comBranches;
 851     Stats::Scalar comNops;
 852     Stats::Scalar comNonSpec;
 853     Stats::Scalar comInts;
 854     Stats::Scalar comFloats;
 855
 856     /** Stat for the number of committed instructions per thread. */
 857     Stats::Vector committedInsts;
 858
 859     /** Stat for the number of committed instructions per thread. */
 860     Stats::Vector smtCommittedInsts;
 861
 862     /** Stat for the total number of committed instructions. */
 863     Stats::Scalar totalCommittedInsts;
 864
 865     /** Stat for the CPI per thread. */
 866     Stats::Formula cpi;
 867
 868     /** Stat for the SMT-CPI per thread. */
 869     Stats::Formula smtCpi;
 870
 871     /** Stat for the total CPI. */
 872     Stats::Formula totalCpi;
 873
 874     /** Stat for the IPC per thread. */
 875     Stats::Formula ipc;
 876
 877     /** Stat for the total IPC. */
 878     Stats::Formula smtIpc;
 879
 880     /** Stat for the total IPC. */
 881     Stats::Formula totalIpc;
 882 };
 883
 884 #endif // __CPU_O3_CPU_HH__