src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/registers.hh"
  43 #include "arch/types.hh"
  44 #include "base/statistics.hh"
  45 #include "base/types.hh"
  46 #include "config/the_isa.hh"
  47 #include "cpu/inorder/inorder_dyn_inst.hh"
  48 #include "cpu/inorder/pipeline_stage.hh"
  49 #include "cpu/inorder/pipeline_traits.hh"
  50 #include "cpu/inorder/reg_dep_map.hh"
  51 #include "cpu/inorder/thread_state.hh"
  52 #include "cpu/o3/dep_graph.hh"
  53 #include "cpu/o3/rename_map.hh"
  54 #include "cpu/activity.hh"
  55 #include "cpu/base.hh"
  56 #include "cpu/simple_thread.hh"
  57 #include "cpu/timebuf.hh"
  58 #include "mem/packet.hh"
  59 #include "mem/port.hh"
  60 #include "mem/request.hh"
  61 #include "sim/eventq.hh"
  62 #include "sim/process.hh"
  63
  64 class ThreadContext;
  65 class MemInterface;
  66 class MemObject;
  67 class Process;
  68 class ResourcePool;
  69
  70 class InOrderCPU : public BaseCPU
  71 {
  72
  73   protected:
  74     typedef ThePipeline::Params Params;
  75     typedef InOrderThreadState Thread;
  76
  77    //ISA TypeDefs
  78     typedef TheISA::IntReg IntReg;
  79     typedef TheISA::FloatReg FloatReg;
  80     typedef TheISA::FloatRegBits FloatRegBits;
  81     typedef TheISA::MiscReg MiscReg;
  82     typedef TheISA::RegIndex RegIndex;
  83
  84     //DynInstPtr TypeDefs
  85     typedef ThePipeline::DynInstPtr DynInstPtr;
  86     typedef std::list<DynInstPtr>::iterator ListIt;
  87
  88     //TimeBuffer TypeDefs
  89     typedef TimeBuffer<InterStageStruct> StageQueue;
  90
  91     friend class Resource;
  92
  93   public:
  94     /** Constructs a CPU with the given parameters. */
  95     InOrderCPU(Params *params);
  96     /* Destructor */
  97     ~InOrderCPU();
  98
  99     /** CPU ID */
 100     int cpu_id;
 101
 102     // SE Mode ASIDs
 103     ThreadID asid[ThePipeline::MaxThreads];
 104
 105     /** Type of core that this is */
 106     std::string coreType;
 107
 108     // Only need for SE MODE
 109     enum ThreadModel {
 110         Single,
 111         SMT,
 112         SwitchOnCacheMiss
 113     };
 114
 115     ThreadModel threadModel;
 116
 117     int readCpuId() { return cpu_id; }
 118
 119     void setCpuId(int val) { cpu_id = val; }
 120
 121     Params *cpu_params;
 122
 123   public:
 124     enum Status {
 125         Running,
 126         Idle,
 127         Halted,
 128         Blocked,
 129         SwitchedOut
 130     };
 131
 132     /** Overall CPU status. */
 133     Status _status;
 134   private:
 135     /** Define TickEvent for the CPU */
 136     class TickEvent : public Event
 137     {
 138       private:
 139         /** Pointer to the CPU. */
 140         InOrderCPU *cpu;
 141
 142       public:
 143         /** Constructs a tick event. */
 144         TickEvent(InOrderCPU *c);
 145
 146         /** Processes a tick event, calling tick() on the CPU. */
 147         void process();
 148
 149         /** Returns the description of the tick event. */
 150         const char *description();
 151     };
 152
 153     /** The tick event used for scheduling CPU ticks. */
 154     TickEvent tickEvent;
 155
 156     /** Schedule tick event, regardless of its current state. */
 157     void scheduleTickEvent(int delay)
 158     {
 159         assert(!tickEvent.scheduled() || tickEvent.squashed());
 160         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 161     }
 162
 163     /** Unschedule tick event, regardless of its current state. */
 164     void unscheduleTickEvent()
 165     {
 166         if (tickEvent.scheduled())
 167             tickEvent.squash();
 168     }
 169
 170   public:
 171     // List of Events That can be scheduled from
 172     // within the CPU.
 173     // NOTE(1): The Resource Pool also uses this event list
 174     // to schedule events broadcast to all resources interfaces
 175     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 176     // pool event.
 177     enum CPUEventType {
 178         ActivateThread,
 179         ActivateNextReadyThread,
 180         DeactivateThread,
 181         HaltThread,
 182         SuspendThread,
 183         Trap,
 184         Syscall,
 185         SquashFromMemStall,
 186         UpdatePCs,
 187         NumCPUEvents
 188     };
 189
 190     static std::string eventNames[NumCPUEvents];
 191
 192     enum CPUEventPri {
 193         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 194         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 195         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 196     };
 197
 198     /** Define CPU Event */
 199     class CPUEvent : public Event
 200     {
 201       protected:
 202         InOrderCPU *cpu;
 203
 204       public:
 205         CPUEventType cpuEventType;
 206         ThreadID tid;
 207         DynInstPtr inst;
 208         Fault fault;
 209         unsigned vpe;
 210         short syscall_num;
 211
 212       public:
 213         /** Constructs a CPU event. */
 214         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 215                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 216
 217         /** Set Type of Event To Be Scheduled */
 218         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 219                       DynInstPtr _inst)
 220         {
 221             fault = _fault;
 222             cpuEventType = e_type;
 223             tid = _tid;
 224             inst = _inst;
 225             vpe = 0;
 226         }
 227
 228         /** Processes a CPU event. */
 229         void process();
 230
 231         /** Returns the description of the CPU event. */
 232         const char *description();
 233
 234         /** Schedule Event */
 235         void scheduleEvent(int delay);
 236
 237         /** Unschedule This Event */
 238         void unscheduleEvent();
 239     };
 240
 241     /** Schedule a CPU Event */
 242     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 243                           DynInstPtr inst, unsigned delay = 0,
 244                           CPUEventPri event_pri = InOrderCPU_Pri);
 245
 246   public:
 247     /** Interface between the CPU and CPU resources. */
 248     ResourcePool *resPool;
 249
 250     /** Instruction used to signify that there is no *real* instruction in
 251         buffer slot */
 252     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 253     DynInstPtr dummyBufferInst;
 254     DynInstPtr dummyReqInst;
 255     DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
 256
 257     /** Used by resources to signify a denied access to a resource. */
 258     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 259
 260     /** Identifies the resource id that identifies a fetch
 261      * access unit.
 262      */
 263     unsigned fetchPortIdx;
 264
 265     /** Identifies the resource id that identifies a data
 266      * access unit.
 267      */
 268     unsigned dataPortIdx;
 269
 270     /** The Pipeline Stages for the CPU */
 271     PipelineStage *pipelineStage[ThePipeline::NumStages];
 272
 273     /** Width (processing bandwidth) of each stage */
 274     int stageWidth;
 275
 276     /** Program Counters */
 277     TheISA::PCState pc[ThePipeline::MaxThreads];
 278
 279     /** Last Committed PC */
 280     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 281
 282     /** The Register File for the CPU */
 283     union {
 284         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 285         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 286     } floatRegs;
 287     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 288
 289     /** ISA state */
 290     TheISA::ISA isa[ThePipeline::MaxThreads];
 291
 292     /** Dependency Tracker for Integer & Floating Point Regs */
 293     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 294
 295     /** Register Types Used in Dependency Tracking */
 296     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 297
 298     /** Global communication structure */
 299     TimeBuffer<TimeStruct> timeBuffer;
 300
 301     /** Communication structure that sits in between pipeline stages */
 302     StageQueue *stageQueue[ThePipeline::NumStages-1];
 303
 304     TheISA::TLB *getITBPtr();
 305     TheISA::TLB *getDTBPtr();
 306
 307     Decoder *getDecoderPtr();
 308
 309     /** Accessor Type for the SkedCache */
 310     typedef uint32_t SkedID;
 311
 312     /** Cache of Instruction Schedule using the instruction's name as a key */
 313     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 314
 315     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 316
 317     /** Initialized to last iterator in map, signifying a invalid entry
 318         on map searches
 319     */
 320     SkedCacheIt endOfSkedIt;
 321
 322     ThePipeline::RSkedPtr frontEndSked;
 323     ThePipeline::RSkedPtr faultSked;
 324
 325     /** Add a new instruction schedule to the schedule cache */
 326     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 327     {
 328         SkedID sked_id = genSkedID(inst);
 329         assert(skedCache.find(sked_id) == skedCache.end());
 330         skedCache[sked_id] = inst_sked;
 331     }
 332
 333
 334     /** Find a instruction schedule */
 335     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 336     {
 337         SkedID sked_id = genSkedID(inst);
 338         SkedCacheIt lookup_it = skedCache.find(sked_id);
 339
 340         if (lookup_it != endOfSkedIt) {
 341             return (*lookup_it).second;
 342         } else {
 343             return NULL;
 344         }
 345     }
 346
 347     static const uint8_t INST_OPCLASS                       = 26;
 348     static const uint8_t INST_LOAD                          = 25;
 349     static const uint8_t INST_STORE                         = 24;
 350     static const uint8_t INST_CONTROL                       = 23;
 351     static const uint8_t INST_NONSPEC                       = 22;
 352     static const uint8_t INST_DEST_REGS                     = 18;
 353     static const uint8_t INST_SRC_REGS                      = 14;
 354     static const uint8_t INST_SPLIT_DATA                    = 13;
 355
 356     inline SkedID genSkedID(DynInstPtr inst)
 357     {
 358         SkedID id = 0;
 359         id = (inst->opClass() << INST_OPCLASS) |
 360             (inst->isLoad() << INST_LOAD) |
 361             (inst->isStore() << INST_STORE) |
 362             (inst->isControl() << INST_CONTROL) |
 363             (inst->isNonSpeculative() << INST_NONSPEC) |
 364             (inst->numDestRegs() << INST_DEST_REGS) |
 365             (inst->numSrcRegs() << INST_SRC_REGS) |
 366             (inst->splitInst << INST_SPLIT_DATA);
 367         return id;
 368     }
 369
 370     ThePipeline::RSkedPtr createFrontEndSked();
 371     ThePipeline::RSkedPtr createFaultSked();
 372     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 373
 374     class StageScheduler {
 375       private:
 376         ThePipeline::RSkedPtr rsked;
 377         int stageNum;
 378         int nextTaskPriority;
 379
 380       public:
 381         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 382             : rsked(_rsked), stageNum(stage_num),
 383               nextTaskPriority(0)
 384         { }
 385
 386         void needs(int unit, int request) {
 387             rsked->push(new ScheduleEntry(
 388                             stageNum, nextTaskPriority++, unit, request
 389                             ));
 390         }
 391
 392         void needs(int unit, int request, int param) {
 393             rsked->push(new ScheduleEntry(
 394                             stageNum, nextTaskPriority++, unit, request, param
 395                             ));
 396         }
 397     };
 398
 399   public:
 400
 401     /** Registers statistics. */
 402     void regStats();
 403
 404     /** Ticks CPU, calling tick() on each stage, and checking the overall
 405      *  activity to see if the CPU should deschedule itself.
 406      */
 407     void tick();
 408
 409     /** Initialize the CPU */
 410     void init();
 411
 412     /** Get a Memory Port */
 413     Port* getPort(const std::string &if_name, int idx = 0);
 414
 415     /** HW return from error interrupt. */
 416     Fault hwrei(ThreadID tid);
 417
 418     bool simPalCheck(int palFunc, ThreadID tid);
 419
 420     void checkForInterrupts();
 421
 422     /** Returns the Fault for any valid interrupt. */
 423     Fault getInterrupts();
 424
 425     /** Processes any an interrupt fault. */
 426     void processInterrupts(Fault interrupt);
 427
 428     /** Halts the CPU. */
 429     void halt() { panic("Halt not implemented!\n"); }
 430
 431     /** Update the Virt and Phys ports of all ThreadContexts to
 432      * reflect change in memory connections. */
 433     void updateMemPorts();
 434
 435     /** Check if this address is a valid instruction address. */
 436     bool validInstAddr(Addr addr) { return true; }
 437
 438     /** Check if this address is a valid data address. */
 439     bool validDataAddr(Addr addr) { return true; }
 440
 441     /** Schedule a syscall on the CPU */
 442     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 443                         int delay = 0);
 444
 445     /** Executes a syscall.*/
 446     void syscall(int64_t callnum, ThreadID tid);
 447
 448     /** Schedule a trap on the CPU */
 449     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 450
 451     /** Perform trap to Handle Given Fault */
 452     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 453
 454     /** Schedule thread activation on the CPU */
 455     void activateContext(ThreadID tid, int delay = 0);
 456
 457     /** Add Thread to Active Threads List. */
 458     void activateThread(ThreadID tid);
 459
 460     /** Activate Thread In Each Pipeline Stage */
 461     void activateThreadInPipeline(ThreadID tid);
 462
 463     /** Schedule Thread Activation from Ready List */
 464     void activateNextReadyContext(int delay = 0);
 465
 466     /** Add Thread From Ready List to Active Threads List. */
 467     void activateNextReadyThread();
 468
 469     /** Schedule a thread deactivation on the CPU */
 470     void deactivateContext(ThreadID tid, int delay = 0);
 471
 472     /** Remove from Active Thread List */
 473     void deactivateThread(ThreadID tid);
 474
 475     /** Schedule a thread suspension on the CPU */
 476     void suspendContext(ThreadID tid, int delay = 0);
 477
 478     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 479     void suspendThread(ThreadID tid);
 480
 481     /** Schedule a thread halt on the CPU */
 482     void haltContext(ThreadID tid, int delay = 0);
 483
 484     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 485      *  Threads List
 486      */
 487     void haltThread(ThreadID tid);
 488
 489     /** squashFromMemStall() - sets up a squash event
 490      *  squashDueToMemStall() - squashes pipeline
 491      *  @note: maybe squashContext/squashThread would be better?
 492      */
 493     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 494     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 495
 496     void removePipelineStalls(ThreadID tid);
 497     void squashThreadInPipeline(ThreadID tid);
 498     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 499
 500     PipelineStage* getPipeStage(int stage_num);
 501
 502     int
 503     contextId()
 504     {
 505         hack_once("return a bogus context id");
 506         return 0;
 507     }
 508
 509     /** Update The Order In Which We Process Threads. */
 510     void updateThreadPriority();
 511
 512     /** Switches a Pipeline Stage to Active. (Unused currently) */
 513     void switchToActive(int stage_idx)
 514     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 515
 516     /** Get the current instruction sequence number, and increment it. */
 517     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 518     { return globalSeqNum[tid]++; }
 519
 520     /** Get the current instruction sequence number, and increment it. */
 521     InstSeqNum nextInstSeqNum(ThreadID tid)
 522     { return globalSeqNum[tid]; }
 523
 524     /** Increment Instruction Sequence Number */
 525     void incrInstSeqNum(ThreadID tid)
 526     { globalSeqNum[tid]++; }
 527
 528     /** Set Instruction Sequence Number */
 529     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 530     {
 531         globalSeqNum[tid] = seq_num;
 532     }
 533
 534     /** Get & Update Next Event Number */
 535     InstSeqNum getNextEventNum()
 536     {
 537 #ifdef DEBUG
 538         return cpuEventNum++;
 539 #else
 540         return 0;
 541 #endif
 542     }
 543
 544     /** Register file accessors  */
 545     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 546
 547     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 548
 549     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 550
 551     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 552
 553     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 554
 555     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 556
 557     RegType inline getRegType(RegIndex reg_idx)
 558     {
 559         if (reg_idx < TheISA::FP_Base_DepTag)
 560             return IntType;
 561         else if (reg_idx < TheISA::Ctrl_Base_DepTag)
 562             return FloatType;
 563         else
 564             return MiscType;
 565     }
 566
 567     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 568
 569     /** Reads a miscellaneous register. */
 570     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 571
 572     /** Reads a misc. register, including any side effects the read
 573      * might have as defined by the architecture.
 574      */
 575     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 576
 577     /** Sets a miscellaneous register. */
 578     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 579                             ThreadID tid = 0);
 580
 581     /** Sets a misc. register, including any side effects the write
 582      * might have as defined by the architecture.
 583      */
 584     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 585
 586     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 587      *  target thread
 588      */
 589     uint64_t readRegOtherThread(unsigned misc_reg,
 590                                 ThreadID tid = InvalidThreadID);
 591
 592     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 593      * target thread
 594      */
 595     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 596                            ThreadID tid);
 597
 598     /** Reads the commit PC of a specific thread. */
 599     TheISA::PCState
 600     pcState(ThreadID tid)
 601     {
 602         return pc[tid];
 603     }
 604
 605     /** Sets the commit PC of a specific thread. */
 606     void
 607     pcState(const TheISA::PCState &newPC, ThreadID tid)
 608     {
 609         pc[tid] = newPC;
 610     }
 611
 612     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 613     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 614     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 615
 616     /** Function to add instruction onto the head of the list of the
 617      *  instructions.  Used when new instructions are fetched.
 618      */
 619     ListIt addInst(DynInstPtr inst);
 620
 621     /** Find instruction on instruction list */
 622     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 623
 624     /** Function to tell the CPU that an instruction has completed. */
 625     void instDone(DynInstPtr inst, ThreadID tid);
 626
 627     /** Add Instructions to the CPU Remove List*/
 628     void addToRemoveList(DynInstPtr inst);
 629
 630     /** Remove an instruction from CPU */
 631     void removeInst(DynInstPtr inst);
 632
 633     /** Remove all instructions younger than the given sequence number. */
 634     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 635
 636     /** Removes the instruction pointed to by the iterator. */
 637     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 638
 639     /** Cleans up all instructions on the instruction remove list. */
 640     void cleanUpRemovedInsts();
 641
 642     /** Cleans up all events on the CPU event remove list. */
 643     void cleanUpRemovedEvents();
 644
 645     /** Debug function to print all instructions on the list. */
 646     void dumpInsts();
 647
 648     /** Forwards an instruction read to the appropriate data
 649      *  resource (indexes into Resource Pool thru "dataPortIdx")
 650      */
 651     Fault read(DynInstPtr inst, Addr addr,
 652                uint8_t *data, unsigned size, unsigned flags);
 653
 654     /** Forwards an instruction write. to the appropriate data
 655      *  resource (indexes into Resource Pool thru "dataPortIdx")
 656      */
 657     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 658                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 659
 660   public:
 661     /** Per-Thread List of all the instructions in flight. */
 662     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 663
 664     /** List of all the instructions that will be removed at the end of this
 665      *  cycle.
 666      */
 667     std::queue<ListIt> removeList;
 668
 669     bool trapPending[ThePipeline::MaxThreads];
 670
 671     /** List of all the cpu event requests that will be removed at the end of
 672      *  the current cycle.
 673      */
 674     std::queue<Event*> cpuEventRemoveList;
 675
 676     /** Records if instructions need to be removed this cycle due to
 677      *  being retired or squashed.
 678      */
 679     bool removeInstsThisCycle;
 680
 681     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 682      * execution unit know, NOT to execute while the instruction is active.
 683      */
 684     bool nonSpecInstActive[ThePipeline::MaxThreads];
 685
 686     /** Instruction Seq. Num of current non-speculative instruction. */
 687     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 688
 689     /** Instruction Seq. Num of last instruction squashed in pipeline */
 690     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 691
 692     /** Last Cycle that the CPU squashed instruction end. */
 693     Tick lastSquashCycle[ThePipeline::MaxThreads];
 694
 695     std::list<ThreadID> fetchPriorityList;
 696
 697   protected:
 698     /** Active Threads List */
 699     std::list<ThreadID> activeThreads;
 700
 701     /** Ready Threads List */
 702     std::list<ThreadID> readyThreads;
 703
 704     /** Suspended Threads List */
 705     std::list<ThreadID> suspendedThreads;
 706
 707     /** Halted Threads List */
 708     std::list<ThreadID> haltedThreads;
 709
 710     /** Thread Status Functions */
 711     bool isThreadActive(ThreadID tid);
 712     bool isThreadReady(ThreadID tid);
 713     bool isThreadSuspended(ThreadID tid);
 714
 715   private:
 716     /** The activity recorder; used to tell if the CPU has any
 717      * activity remaining or if it can go to idle and deschedule
 718      * itself.
 719      */
 720     ActivityRecorder activityRec;
 721
 722   public:
 723     /** Number of Active Threads in the CPU */
 724     ThreadID numActiveThreads() { return activeThreads.size(); }
 725
 726     /** Thread id of active thread
 727      *  Only used for SwitchOnCacheMiss model.
 728      *  Assumes only 1 thread active
 729      */
 730     ThreadID activeThreadId()
 731     {
 732         if (numActiveThreads() > 0)
 733             return activeThreads.front();
 734         else
 735             return InvalidThreadID;
 736     }
 737
 738
 739     /** Records that there was time buffer activity this cycle. */
 740     void activityThisCycle() { activityRec.activity(); }
 741
 742     /** Changes a stage's status to active within the activity recorder. */
 743     void activateStage(const int idx)
 744     { activityRec.activateStage(idx); }
 745
 746     /** Changes a stage's status to inactive within the activity recorder. */
 747     void deactivateStage(const int idx)
 748     { activityRec.deactivateStage(idx); }
 749
 750     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 751     void wakeCPU();
 752
 753     virtual void wakeup();
 754
 755     /* LL/SC debug functionality
 756     unsigned stCondFails;
 757
 758     unsigned readStCondFailures()
 759     { return stCondFails; }
 760
 761     unsigned setStCondFailures(unsigned st_fails)
 762     { return stCondFails = st_fails; }
 763     */
 764
 765     /** Returns a pointer to a thread context. */
 766     ThreadContext *tcBase(ThreadID tid = 0)
 767     {
 768         return thread[tid]->getTC();
 769     }
 770
 771     /** Count the Total Instructions Committed in the CPU. */
 772     virtual Counter totalInstructions() const
 773     {
 774         Counter total(0);
 775
 776         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 777             total += thread[tid]->numInst;
 778
 779         return total;
 780     }
 781
 782     /** Pointer to the system. */
 783     System *system;
 784
 785     /** The global sequence number counter. */
 786     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 787
 788 #ifdef DEBUG
 789     /** The global event number counter. */
 790     InstSeqNum cpuEventNum;
 791
 792     /** Number of resource requests active in CPU **/
 793     unsigned resReqCount;
 794 #endif
 795
 796     Addr lockAddr;
 797
 798     /** Temporary fix for the lock flag, works in the UP case. */
 799     bool lockFlag;
 800
 801     /** Counter of how many stages have completed draining */
 802     int drainCount;
 803
 804     /** Pointers to all of the threads in the CPU. */
 805     std::vector<Thread *> thread;
 806
 807     /** Pointer to the icache interface. */
 808     MemInterface *icacheInterface;
 809
 810     /** Pointer to the dcache interface. */
 811     MemInterface *dcacheInterface;
 812
 813     /** Whether or not the CPU should defer its registration. */
 814     bool deferRegistration;
 815
 816     /** Per-Stage Instruction Tracing */
 817     bool stageTracing;
 818
 819     /** The cycle that the CPU was last running, used for statistics. */
 820     Tick lastRunningCycle;
 821
 822     void updateContextSwitchStats();
 823     unsigned instsPerSwitch;
 824     Stats::Average instsPerCtxtSwitch;
 825     Stats::Scalar numCtxtSwitches;
 826
 827     /** Update Thread , used for statistic purposes*/
 828     inline void tickThreadStats();
 829
 830     /** Per-Thread Tick */
 831     Stats::Vector threadCycles;
 832
 833     /** Tick for SMT */
 834     Stats::Scalar smtCycles;
 835
 836     /** Stat for total number of times the CPU is descheduled. */
 837     Stats::Scalar timesIdled;
 838
 839     /** Stat for total number of cycles the CPU spends descheduled or no
 840      *  stages active.
 841      */
 842     Stats::Scalar idleCycles;
 843
 844     /** Stat for total number of cycles the CPU is active. */
 845     Stats::Scalar runCycles;
 846
 847     /** Percentage of cycles a stage was active */
 848     Stats::Formula activity;
 849
 850     /** Instruction Mix Stats */
 851     Stats::Scalar comLoads;
 852     Stats::Scalar comStores;
 853     Stats::Scalar comBranches;
 854     Stats::Scalar comNops;
 855     Stats::Scalar comNonSpec;
 856     Stats::Scalar comInts;
 857     Stats::Scalar comFloats;
 858
 859     /** Stat for the number of committed instructions per thread. */
 860     Stats::Vector committedInsts;
 861
 862     /** Stat for the number of committed instructions per thread. */
 863     Stats::Vector smtCommittedInsts;
 864
 865     /** Stat for the total number of committed instructions. */
 866     Stats::Scalar totalCommittedInsts;
 867
 868     /** Stat for the CPI per thread. */
 869     Stats::Formula cpi;
 870
 871     /** Stat for the SMT-CPI per thread. */
 872     Stats::Formula smtCpi;
 873
 874     /** Stat for the total CPI. */
 875     Stats::Formula totalCpi;
 876
 877     /** Stat for the IPC per thread. */
 878     Stats::Formula ipc;
 879
 880     /** Stat for the total IPC. */
 881     Stats::Formula smtIpc;
 882
 883     /** Stat for the total IPC. */
 884     Stats::Formula totalIpc;
 885 };
 886
 887 #endif // __CPU_O3_CPU_HH__