src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/types.hh"
  43 #include "arch/registers.hh"
  44 #include "base/statistics.hh"
  45 #include "cpu/timebuf.hh"
  46 #include "base/types.hh"
  47 #include "config/full_system.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/activity.hh"
  50 #include "cpu/base.hh"
  51 #include "cpu/simple_thread.hh"
  52 #include "cpu/inorder/inorder_dyn_inst.hh"
  53 #include "cpu/inorder/pipeline_traits.hh"
  54 #include "cpu/inorder/pipeline_stage.hh"
  55 #include "cpu/inorder/thread_state.hh"
  56 #include "cpu/inorder/reg_dep_map.hh"
  57 #include "cpu/o3/dep_graph.hh"
  58 #include "cpu/o3/rename_map.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83
  84     //DynInstPtr TypeDefs
  85     typedef ThePipeline::DynInstPtr DynInstPtr;
  86     typedef std::list<DynInstPtr>::iterator ListIt;
  87
  88     //TimeBuffer TypeDefs
  89     typedef TimeBuffer<InterStageStruct> StageQueue;
  90
  91     friend class Resource;
  92
  93   public:
  94     /** Constructs a CPU with the given parameters. */
  95     InOrderCPU(Params *params);
  96     /* Destructor */
  97     ~InOrderCPU();
  98
  99     /** CPU ID */
 100     int cpu_id;
 101
 102     // SE Mode ASIDs
 103     ThreadID asid[ThePipeline::MaxThreads];
 104
 105     /** Type of core that this is */
 106     std::string coreType;
 107
 108     // Only need for SE MODE
 109     enum ThreadModel {
 110         Single,
 111         SMT,
 112         SwitchOnCacheMiss
 113     };
 114
 115     ThreadModel threadModel;
 116
 117     int readCpuId() { return cpu_id; }
 118
 119     void setCpuId(int val) { cpu_id = val; }
 120
 121     Params *cpu_params;
 122
 123   public:
 124     enum Status {
 125         Running,
 126         Idle,
 127         Halted,
 128         Blocked,
 129         SwitchedOut
 130     };
 131
 132     /** Overall CPU status. */
 133     Status _status;
 134   private:
 135     /** Define TickEvent for the CPU */
 136     class TickEvent : public Event
 137     {
 138       private:
 139         /** Pointer to the CPU. */
 140         InOrderCPU *cpu;
 141
 142       public:
 143         /** Constructs a tick event. */
 144         TickEvent(InOrderCPU *c);
 145
 146         /** Processes a tick event, calling tick() on the CPU. */
 147         void process();
 148
 149         /** Returns the description of the tick event. */
 150         const char *description();
 151     };
 152
 153     /** The tick event used for scheduling CPU ticks. */
 154     TickEvent tickEvent;
 155
 156     /** Schedule tick event, regardless of its current state. */
 157     void scheduleTickEvent(int delay)
 158     {
 159         assert(!tickEvent.scheduled() || tickEvent.squashed());
 160         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 161     }
 162
 163     /** Unschedule tick event, regardless of its current state. */
 164     void unscheduleTickEvent()
 165     {
 166         if (tickEvent.scheduled())
 167             tickEvent.squash();
 168     }
 169
 170   public:
 171     // List of Events That can be scheduled from
 172     // within the CPU.
 173     // NOTE(1): The Resource Pool also uses this event list
 174     // to schedule events broadcast to all resources interfaces
 175     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 176     // pool event.
 177     enum CPUEventType {
 178         ActivateThread,
 179         ActivateNextReadyThread,
 180         DeactivateThread,
 181         HaltThread,
 182         SuspendThread,
 183         Trap,
 184         InstGraduated,
 185         SquashFromMemStall,
 186         UpdatePCs,
 187         NumCPUEvents
 188     };
 189
 190     static std::string eventNames[NumCPUEvents];
 191
 192     /** Define CPU Event */
 193     class CPUEvent : public Event
 194     {
 195       protected:
 196         InOrderCPU *cpu;
 197
 198       public:
 199         CPUEventType cpuEventType;
 200         ThreadID tid;
 201         DynInstPtr inst;
 202         Fault fault;
 203         unsigned vpe;
 204
 205       public:
 206         /** Constructs a CPU event. */
 207         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 208                  ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
 209
 210         /** Set Type of Event To Be Scheduled */
 211         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 212                       DynInstPtr _inst)
 213         {
 214             fault = _fault;
 215             cpuEventType = e_type;
 216             tid = _tid;
 217             inst = _inst;
 218             vpe = 0;
 219         }
 220
 221         /** Processes a CPU event. */
 222         void process();
 223
 224         /** Returns the description of the CPU event. */
 225         const char *description();
 226
 227         /** Schedule Event */
 228         void scheduleEvent(int delay);
 229
 230         /** Unschedule This Event */
 231         void unscheduleEvent();
 232     };
 233
 234     /** Schedule a CPU Event */
 235     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 236                           DynInstPtr inst, unsigned delay = 0,
 237                           unsigned event_pri_offset = 0);
 238
 239   public:
 240     /** Interface between the CPU and CPU resources. */
 241     ResourcePool *resPool;
 242
 243     /** Instruction used to signify that there is no *real* instruction in
 244         buffer slot */
 245     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 246     DynInstPtr dummyBufferInst;
 247     DynInstPtr dummyReqInst;
 248
 249     /** Used by resources to signify a denied access to a resource. */
 250     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 251
 252     /** Identifies the resource id that identifies a fetch
 253      * access unit.
 254      */
 255     unsigned fetchPortIdx;
 256
 257     /** Identifies the resource id that identifies a ITB       */
 258     unsigned itbIdx;
 259
 260     /** Identifies the resource id that identifies a data
 261      * access unit.
 262      */
 263     unsigned dataPortIdx;
 264
 265     /** Identifies the resource id that identifies a DTB       */
 266     unsigned dtbIdx;
 267
 268     /** The Pipeline Stages for the CPU */
 269     PipelineStage *pipelineStage[ThePipeline::NumStages];
 270
 271     /** Width (processing bandwidth) of each stage */
 272     int stageWidth;
 273
 274     /** Program Counters */
 275     TheISA::PCState pc[ThePipeline::MaxThreads];
 276
 277     /** The Register File for the CPU */
 278     union {
 279         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 280         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 281     } floatRegs;
 282     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 283
 284     /** ISA state */
 285     TheISA::ISA isa[ThePipeline::MaxThreads];
 286
 287     /** Dependency Tracker for Integer & Floating Point Regs */
 288     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 289
 290     /** Global communication structure */
 291     TimeBuffer<TimeStruct> timeBuffer;
 292
 293     /** Communication structure that sits in between pipeline stages */
 294     StageQueue *stageQueue[ThePipeline::NumStages-1];
 295
 296     TheISA::TLB *getITBPtr();
 297     TheISA::TLB *getDTBPtr();
 298
 299     /** Accessor Type for the SkedCache */
 300     typedef uint32_t SkedID;
 301
 302     /** Cache of Instruction Schedule using the instruction's name as a key */
 303     static std::map<SkedID, ThePipeline::RSkedPtr> skedCache;
 304
 305     typedef std::map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 306
 307     /** Initialized to last iterator in map, signifying a invalid entry
 308         on map searches
 309     */
 310     SkedCacheIt endOfSkedIt;
 311
 312     ThePipeline::RSkedPtr frontEndSked;
 313
 314     /** Add a new instruction schedule to the schedule cache */
 315     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 316     {
 317         SkedID sked_id = genSkedID(inst);
 318         skedCache[sked_id] = inst_sked;
 319     }
 320
 321
 322     /** Find a instruction schedule */
 323     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 324     {
 325         SkedID sked_id = genSkedID(inst);
 326         SkedCacheIt lookup_it = skedCache.find(sked_id);
 327
 328         if (lookup_it != endOfSkedIt) {
 329             return (*lookup_it).second;
 330         } else {
 331             return NULL;
 332         }
 333     }
 334
 335     static const uint8_t INST_OPCLASS                       = 26;
 336     static const uint8_t INST_LOAD                          = 25;
 337     static const uint8_t INST_STORE                         = 24;
 338     static const uint8_t INST_CONTROL                       = 23;
 339     static const uint8_t INST_NONSPEC                       = 22;
 340     static const uint8_t INST_DEST_REGS                     = 18;
 341     static const uint8_t INST_SRC_REGS                      = 14;
 342
 343     inline SkedID genSkedID(DynInstPtr inst)
 344     {
 345         SkedID id = 0;
 346         id = (inst->opClass() << INST_OPCLASS) |
 347             (inst->isLoad() << INST_LOAD) |
 348             (inst->isStore() << INST_STORE) |
 349             (inst->isControl() << INST_CONTROL) |
 350             (inst->isNonSpeculative() << INST_NONSPEC) |
 351             (inst->numDestRegs() << INST_DEST_REGS) |
 352             (inst->numSrcRegs() << INST_SRC_REGS);
 353         return id;
 354     }
 355
 356     ThePipeline::RSkedPtr createFrontEndSked();
 357     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 358
 359     class StageScheduler {
 360       private:
 361         ThePipeline::RSkedPtr rsked;
 362         int stageNum;
 363         int nextTaskPriority;
 364
 365       public:
 366         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 367             : rsked(_rsked), stageNum(stage_num),
 368               nextTaskPriority(0)
 369         { }
 370
 371         void needs(int unit, int request) {
 372             rsked->push(new ScheduleEntry(
 373                             stageNum, nextTaskPriority++, unit, request
 374                             ));
 375         }
 376
 377         void needs(int unit, int request, int param) {
 378             rsked->push(new ScheduleEntry(
 379                             stageNum, nextTaskPriority++, unit, request, param
 380                             ));
 381         }
 382     };
 383
 384   public:
 385
 386     /** Registers statistics. */
 387     void regStats();
 388
 389     /** Ticks CPU, calling tick() on each stage, and checking the overall
 390      *  activity to see if the CPU should deschedule itself.
 391      */
 392     void tick();
 393
 394     /** Initialize the CPU */
 395     void init();
 396
 397     /** Reset State in the CPU */
 398     void reset();
 399
 400     /** Get a Memory Port */
 401     Port* getPort(const std::string &if_name, int idx = 0);
 402
 403 #if FULL_SYSTEM
 404     /** HW return from error interrupt. */
 405     Fault hwrei(ThreadID tid);
 406
 407     bool simPalCheck(int palFunc, ThreadID tid);
 408
 409     /** Returns the Fault for any valid interrupt. */
 410     Fault getInterrupts();
 411
 412     /** Processes any an interrupt fault. */
 413     void processInterrupts(Fault interrupt);
 414
 415     /** Halts the CPU. */
 416     void halt() { panic("Halt not implemented!\n"); }
 417
 418     /** Update the Virt and Phys ports of all ThreadContexts to
 419      * reflect change in memory connections. */
 420     void updateMemPorts();
 421
 422     /** Check if this address is a valid instruction address. */
 423     bool validInstAddr(Addr addr) { return true; }
 424
 425     /** Check if this address is a valid data address. */
 426     bool validDataAddr(Addr addr) { return true; }
 427 #endif
 428
 429     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
 430      *  trapCPU() - Traps to handle given fault
 431      */
 432     void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 433     void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
 434
 435     /** Add Thread to Active Threads List. */
 436     void activateContext(ThreadID tid, int delay = 0);
 437     void activateThread(ThreadID tid);
 438     void activateThreadInPipeline(ThreadID tid);
 439
 440     /** Add Thread to Active Threads List. */
 441     void activateNextReadyContext(int delay = 0);
 442     void activateNextReadyThread();
 443
 444     /** Remove from Active Thread List */
 445     void deactivateContext(ThreadID tid, int delay = 0);
 446     void deactivateThread(ThreadID tid);
 447
 448     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 449     void suspendContext(ThreadID tid, int delay = 0);
 450     void suspendThread(ThreadID tid);
 451
 452     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 453      *  Threads List
 454      */
 455     void haltContext(ThreadID tid, int delay = 0);
 456     void haltThread(ThreadID tid);
 457
 458     /** squashFromMemStall() - sets up a squash event
 459      *  squashDueToMemStall() - squashes pipeline
 460      *  @note: maybe squashContext/squashThread would be better?
 461      */
 462     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 463     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 464
 465     void removePipelineStalls(ThreadID tid);
 466     void squashThreadInPipeline(ThreadID tid);
 467     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 468
 469     PipelineStage* getPipeStage(int stage_num);
 470
 471     int
 472     contextId()
 473     {
 474         hack_once("return a bogus context id");
 475         return 0;
 476     }
 477
 478     /** Update The Order In Which We Process Threads. */
 479     void updateThreadPriority();
 480
 481     /** Switches a Pipeline Stage to Active. (Unused currently) */
 482     void switchToActive(int stage_idx)
 483     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 484
 485     /** Get the current instruction sequence number, and increment it. */
 486     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 487     { return globalSeqNum[tid]++; }
 488
 489     /** Get the current instruction sequence number, and increment it. */
 490     InstSeqNum nextInstSeqNum(ThreadID tid)
 491     { return globalSeqNum[tid]; }
 492
 493     /** Increment Instruction Sequence Number */
 494     void incrInstSeqNum(ThreadID tid)
 495     { globalSeqNum[tid]++; }
 496
 497     /** Set Instruction Sequence Number */
 498     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 499     {
 500         globalSeqNum[tid] = seq_num;
 501     }
 502
 503     /** Get & Update Next Event Number */
 504     InstSeqNum getNextEventNum()
 505     {
 506 #ifdef DEBUG
 507         return cpuEventNum++;
 508 #else
 509         return 0;
 510 #endif
 511     }
 512
 513     /** Register file accessors  */
 514     uint64_t readIntReg(int reg_idx, ThreadID tid);
 515
 516     FloatReg readFloatReg(int reg_idx, ThreadID tid);
 517
 518     FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
 519
 520     void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 521
 522     void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
 523
 524     void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid);
 525
 526     /** Reads a miscellaneous register. */
 527     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 528
 529     /** Reads a misc. register, including any side effects the read
 530      * might have as defined by the architecture.
 531      */
 532     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 533
 534     /** Sets a miscellaneous register. */
 535     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 536                             ThreadID tid = 0);
 537
 538     /** Sets a misc. register, including any side effects the write
 539      * might have as defined by the architecture.
 540      */
 541     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 542
 543     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 544      *  target thread
 545      */
 546     uint64_t readRegOtherThread(unsigned misc_reg,
 547                                 ThreadID tid = InvalidThreadID);
 548
 549     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 550      * target thread
 551      */
 552     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 553                            ThreadID tid);
 554
 555     /** Reads the commit PC of a specific thread. */
 556     TheISA::PCState
 557     pcState(ThreadID tid)
 558     {
 559         return pc[tid];
 560     }
 561
 562     /** Sets the commit PC of a specific thread. */
 563     void
 564     pcState(const TheISA::PCState &newPC, ThreadID tid)
 565     {
 566         pc[tid] = newPC;
 567     }
 568
 569     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 570     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 571     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 572
 573     /** Function to add instruction onto the head of the list of the
 574      *  instructions.  Used when new instructions are fetched.
 575      */
 576     ListIt addInst(DynInstPtr &inst);
 577
 578     /** Function to tell the CPU that an instruction has completed. */
 579     void instDone(DynInstPtr inst, ThreadID tid);
 580
 581     /** Add Instructions to the CPU Remove List*/
 582     void addToRemoveList(DynInstPtr &inst);
 583
 584     /** Remove an instruction from CPU */
 585     void removeInst(DynInstPtr &inst);
 586
 587     /** Remove all instructions younger than the given sequence number. */
 588     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 589
 590     /** Removes the instruction pointed to by the iterator. */
 591     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 592
 593     /** Cleans up all instructions on the instruction remove list. */
 594     void cleanUpRemovedInsts();
 595
 596     /** Cleans up all instructions on the request remove list. */
 597     void cleanUpRemovedReqs();
 598
 599     /** Cleans up all instructions on the CPU event remove list. */
 600     void cleanUpRemovedEvents();
 601
 602     /** Debug function to print all instructions on the list. */
 603     void dumpInsts();
 604
 605     /** Forwards an instruction read to the appropriate data
 606      *  resource (indexes into Resource Pool thru "dataPortIdx")
 607      */
 608     Fault read(DynInstPtr inst, Addr addr,
 609                uint8_t *data, unsigned size, unsigned flags);
 610
 611     /** Forwards an instruction write. to the appropriate data
 612      *  resource (indexes into Resource Pool thru "dataPortIdx")
 613      */
 614     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 615                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 616
 617     /** Executes a syscall.*/
 618     void syscall(int64_t callnum, ThreadID tid);
 619
 620   public:
 621     /** Per-Thread List of all the instructions in flight. */
 622     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 623
 624     /** List of all the instructions that will be removed at the end of this
 625      *  cycle.
 626      */
 627     std::queue<ListIt> removeList;
 628
 629     /** List of all the resource requests that will be removed at the end
 630      *  of this cycle.
 631      */
 632     std::queue<ResourceRequest*> reqRemoveList;
 633
 634     /** List of all the cpu event requests that will be removed at the end of
 635      *  the current cycle.
 636      */
 637     std::queue<Event*> cpuEventRemoveList;
 638
 639     /** Records if instructions need to be removed this cycle due to
 640      *  being retired or squashed.
 641      */
 642     bool removeInstsThisCycle;
 643
 644     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 645      * execution unit know, NOT to execute while the instruction is active.
 646      */
 647     bool nonSpecInstActive[ThePipeline::MaxThreads];
 648
 649     /** Instruction Seq. Num of current non-speculative instruction. */
 650     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 651
 652     /** Instruction Seq. Num of last instruction squashed in pipeline */
 653     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 654
 655     /** Last Cycle that the CPU squashed instruction end. */
 656     Tick lastSquashCycle[ThePipeline::MaxThreads];
 657
 658     std::list<ThreadID> fetchPriorityList;
 659
 660   protected:
 661     /** Active Threads List */
 662     std::list<ThreadID> activeThreads;
 663
 664     /** Ready Threads List */
 665     std::list<ThreadID> readyThreads;
 666
 667     /** Suspended Threads List */
 668     std::list<ThreadID> suspendedThreads;
 669
 670     /** Halted Threads List */
 671     std::list<ThreadID> haltedThreads;
 672
 673     /** Thread Status Functions */
 674     bool isThreadActive(ThreadID tid);
 675     bool isThreadReady(ThreadID tid);
 676     bool isThreadSuspended(ThreadID tid);
 677
 678   private:
 679     /** The activity recorder; used to tell if the CPU has any
 680      * activity remaining or if it can go to idle and deschedule
 681      * itself.
 682      */
 683     ActivityRecorder activityRec;
 684
 685   public:
 686     /** Number of Active Threads in the CPU */
 687     ThreadID numActiveThreads() { return activeThreads.size(); }
 688
 689     /** Thread id of active thread
 690      *  Only used for SwitchOnCacheMiss model.
 691      *  Assumes only 1 thread active
 692      */
 693     ThreadID activeThreadId()
 694     {
 695         if (numActiveThreads() > 0)
 696             return activeThreads.front();
 697         else
 698             return InvalidThreadID;
 699     }
 700
 701
 702     /** Records that there was time buffer activity this cycle. */
 703     void activityThisCycle() { activityRec.activity(); }
 704
 705     /** Changes a stage's status to active within the activity recorder. */
 706     void activateStage(const int idx)
 707     { activityRec.activateStage(idx); }
 708
 709     /** Changes a stage's status to inactive within the activity recorder. */
 710     void deactivateStage(const int idx)
 711     { activityRec.deactivateStage(idx); }
 712
 713     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 714     void wakeCPU();
 715
 716 #if FULL_SYSTEM
 717     virtual void wakeup();
 718 #endif
 719
 720     // LL/SC debug functionality
 721     unsigned stCondFails;
 722
 723     unsigned readStCondFailures()
 724     { return stCondFails; }
 725
 726     unsigned setStCondFailures(unsigned st_fails)
 727     { return stCondFails = st_fails; }
 728
 729     /** Returns a pointer to a thread context. */
 730     ThreadContext *tcBase(ThreadID tid = 0)
 731     {
 732         return thread[tid]->getTC();
 733     }
 734
 735     /** Count the Total Instructions Committed in the CPU. */
 736     virtual Counter totalInstructions() const
 737     {
 738         Counter total(0);
 739
 740         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 741             total += thread[tid]->numInst;
 742
 743         return total;
 744     }
 745
 746 #if FULL_SYSTEM
 747     /** Pointer to the system. */
 748     System *system;
 749
 750     /** Pointer to physical memory. */
 751     PhysicalMemory *physmem;
 752 #endif
 753
 754     /** The global sequence number counter. */
 755     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 756
 757 #ifdef DEBUG
 758     /** The global event number counter. */
 759     InstSeqNum cpuEventNum;
 760
 761     /** Number of resource requests active in CPU **/
 762     unsigned resReqCount;
 763 #endif
 764
 765     /** Counter of how many stages have completed switching out. */
 766     int switchCount;
 767
 768     /** Pointers to all of the threads in the CPU. */
 769     std::vector<Thread *> thread;
 770
 771     /** Pointer to the icache interface. */
 772     MemInterface *icacheInterface;
 773
 774     /** Pointer to the dcache interface. */
 775     MemInterface *dcacheInterface;
 776
 777     /** Whether or not the CPU should defer its registration. */
 778     bool deferRegistration;
 779
 780     /** Per-Stage Instruction Tracing */
 781     bool stageTracing;
 782
 783     /** The cycle that the CPU was last running, used for statistics. */
 784     Tick lastRunningCycle;
 785
 786     void updateContextSwitchStats();
 787     unsigned instsPerSwitch;
 788     Stats::Average instsPerCtxtSwitch;
 789     Stats::Scalar numCtxtSwitches;
 790
 791     /** Update Thread , used for statistic purposes*/
 792     inline void tickThreadStats();
 793
 794     /** Per-Thread Tick */
 795     Stats::Vector threadCycles;
 796
 797     /** Tick for SMT */
 798     Stats::Scalar smtCycles;
 799
 800     /** Stat for total number of times the CPU is descheduled. */
 801     Stats::Scalar timesIdled;
 802
 803     /** Stat for total number of cycles the CPU spends descheduled or no
 804      *  stages active.
 805      */
 806     Stats::Scalar idleCycles;
 807
 808     /** Stat for total number of cycles the CPU is active. */
 809     Stats::Scalar runCycles;
 810
 811     /** Percentage of cycles a stage was active */
 812     Stats::Formula activity;
 813
 814     /** Instruction Mix Stats */
 815     Stats::Scalar comLoads;
 816     Stats::Scalar comStores;
 817     Stats::Scalar comBranches;
 818     Stats::Scalar comNops;
 819     Stats::Scalar comNonSpec;
 820     Stats::Scalar comInts;
 821     Stats::Scalar comFloats;
 822
 823     /** Stat for the number of committed instructions per thread. */
 824     Stats::Vector committedInsts;
 825
 826     /** Stat for the number of committed instructions per thread. */
 827     Stats::Vector smtCommittedInsts;
 828
 829     /** Stat for the total number of committed instructions. */
 830     Stats::Scalar totalCommittedInsts;
 831
 832     /** Stat for the CPI per thread. */
 833     Stats::Formula cpi;
 834
 835     /** Stat for the SMT-CPI per thread. */
 836     Stats::Formula smtCpi;
 837
 838     /** Stat for the total CPI. */
 839     Stats::Formula totalCpi;
 840
 841     /** Stat for the IPC per thread. */
 842     Stats::Formula ipc;
 843
 844     /** Stat for the total IPC. */
 845     Stats::Formula smtIpc;
 846
 847     /** Stat for the total IPC. */
 848     Stats::Formula totalIpc;
 849 };
 850
 851 #endif // __CPU_O3_CPU_HH__