src/cpu/inorder/cpu.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_CPU_HH__
  33 #define __CPU_INORDER_CPU_HH__
  34
  35 #include <iostream>
  36 #include <list>
  37 #include <queue>
  38 #include <set>
  39 #include <vector>
  40
  41 #include "arch/isa_traits.hh"
  42 #include "arch/registers.hh"
  43 #include "arch/types.hh"
  44 #include "base/statistics.hh"
  45 #include "base/types.hh"
  46 #include "config/full_system.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/inorder/inorder_dyn_inst.hh"
  49 #include "cpu/inorder/pipeline_stage.hh"
  50 #include "cpu/inorder/pipeline_traits.hh"
  51 #include "cpu/inorder/reg_dep_map.hh"
  52 #include "cpu/inorder/thread_state.hh"
  53 #include "cpu/o3/dep_graph.hh"
  54 #include "cpu/o3/rename_map.hh"
  55 #include "cpu/activity.hh"
  56 #include "cpu/base.hh"
  57 #include "cpu/simple_thread.hh"
  58 #include "cpu/timebuf.hh"
  59 #include "mem/packet.hh"
  60 #include "mem/port.hh"
  61 #include "mem/request.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64
  65 class ThreadContext;
  66 class MemInterface;
  67 class MemObject;
  68 class Process;
  69 class ResourcePool;
  70
  71 class InOrderCPU : public BaseCPU
  72 {
  73
  74   protected:
  75     typedef ThePipeline::Params Params;
  76     typedef InOrderThreadState Thread;
  77
  78    //ISA TypeDefs
  79     typedef TheISA::IntReg IntReg;
  80     typedef TheISA::FloatReg FloatReg;
  81     typedef TheISA::FloatRegBits FloatRegBits;
  82     typedef TheISA::MiscReg MiscReg;
  83     typedef TheISA::RegIndex RegIndex;
  84
  85     //DynInstPtr TypeDefs
  86     typedef ThePipeline::DynInstPtr DynInstPtr;
  87     typedef std::list<DynInstPtr>::iterator ListIt;
  88
  89     //TimeBuffer TypeDefs
  90     typedef TimeBuffer<InterStageStruct> StageQueue;
  91
  92     friend class Resource;
  93
  94   public:
  95     /** Constructs a CPU with the given parameters. */
  96     InOrderCPU(Params *params);
  97     /* Destructor */
  98     ~InOrderCPU();
  99
 100     /** CPU ID */
 101     int cpu_id;
 102
 103     // SE Mode ASIDs
 104     ThreadID asid[ThePipeline::MaxThreads];
 105
 106     /** Type of core that this is */
 107     std::string coreType;
 108
 109     // Only need for SE MODE
 110     enum ThreadModel {
 111         Single,
 112         SMT,
 113         SwitchOnCacheMiss
 114     };
 115
 116     ThreadModel threadModel;
 117
 118     int readCpuId() { return cpu_id; }
 119
 120     void setCpuId(int val) { cpu_id = val; }
 121
 122     Params *cpu_params;
 123
 124   public:
 125     enum Status {
 126         Running,
 127         Idle,
 128         Halted,
 129         Blocked,
 130         SwitchedOut
 131     };
 132
 133     /** Overall CPU status. */
 134     Status _status;
 135   private:
 136     /** Define TickEvent for the CPU */
 137     class TickEvent : public Event
 138     {
 139       private:
 140         /** Pointer to the CPU. */
 141         InOrderCPU *cpu;
 142
 143       public:
 144         /** Constructs a tick event. */
 145         TickEvent(InOrderCPU *c);
 146
 147         /** Processes a tick event, calling tick() on the CPU. */
 148         void process();
 149
 150         /** Returns the description of the tick event. */
 151         const char *description();
 152     };
 153
 154     /** The tick event used for scheduling CPU ticks. */
 155     TickEvent tickEvent;
 156
 157     /** Schedule tick event, regardless of its current state. */
 158     void scheduleTickEvent(int delay)
 159     {
 160         assert(!tickEvent.scheduled() || tickEvent.squashed());
 161         reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
 162     }
 163
 164     /** Unschedule tick event, regardless of its current state. */
 165     void unscheduleTickEvent()
 166     {
 167         if (tickEvent.scheduled())
 168             tickEvent.squash();
 169     }
 170
 171   public:
 172     // List of Events That can be scheduled from
 173     // within the CPU.
 174     // NOTE(1): The Resource Pool also uses this event list
 175     // to schedule events broadcast to all resources interfaces
 176     // NOTE(2): CPU Events usually need to schedule a corresponding resource
 177     // pool event.
 178     enum CPUEventType {
 179         ActivateThread,
 180         ActivateNextReadyThread,
 181         DeactivateThread,
 182         HaltThread,
 183         SuspendThread,
 184         Trap,
 185         Syscall,
 186         SquashFromMemStall,
 187         UpdatePCs,
 188         NumCPUEvents
 189     };
 190
 191     static std::string eventNames[NumCPUEvents];
 192
 193     enum CPUEventPri {
 194         InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
 195         Syscall_Pri                    = Event::CPU_Tick_Pri + 9,
 196         ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
 197     };
 198
 199     /** Define CPU Event */
 200     class CPUEvent : public Event
 201     {
 202       protected:
 203         InOrderCPU *cpu;
 204
 205       public:
 206         CPUEventType cpuEventType;
 207         ThreadID tid;
 208         DynInstPtr inst;
 209         Fault fault;
 210         unsigned vpe;
 211         short syscall_num;
 212
 213       public:
 214         /** Constructs a CPU event. */
 215         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
 216                  ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 217
 218         /** Set Type of Event To Be Scheduled */
 219         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
 220                       DynInstPtr _inst)
 221         {
 222             fault = _fault;
 223             cpuEventType = e_type;
 224             tid = _tid;
 225             inst = _inst;
 226             vpe = 0;
 227         }
 228
 229         /** Processes a CPU event. */
 230         void process();
 231
 232         /** Returns the description of the CPU event. */
 233         const char *description();
 234
 235         /** Schedule Event */
 236         void scheduleEvent(int delay);
 237
 238         /** Unschedule This Event */
 239         void unscheduleEvent();
 240     };
 241
 242     /** Schedule a CPU Event */
 243     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
 244                           DynInstPtr inst, unsigned delay = 0,
 245                           CPUEventPri event_pri = InOrderCPU_Pri);
 246
 247   public:
 248     /** Interface between the CPU and CPU resources. */
 249     ResourcePool *resPool;
 250
 251     /** Instruction used to signify that there is no *real* instruction in
 252         buffer slot */
 253     DynInstPtr dummyInst[ThePipeline::MaxThreads];
 254     DynInstPtr dummyBufferInst;
 255     DynInstPtr dummyReqInst;
 256     DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
 257
 258     /** Used by resources to signify a denied access to a resource. */
 259     ResourceRequest *dummyReq[ThePipeline::MaxThreads];
 260
 261     /** Identifies the resource id that identifies a fetch
 262      * access unit.
 263      */
 264     unsigned fetchPortIdx;
 265
 266     /** Identifies the resource id that identifies a data
 267      * access unit.
 268      */
 269     unsigned dataPortIdx;
 270
 271     /** The Pipeline Stages for the CPU */
 272     PipelineStage *pipelineStage[ThePipeline::NumStages];
 273
 274     /** Width (processing bandwidth) of each stage */
 275     int stageWidth;
 276
 277     /** Program Counters */
 278     TheISA::PCState pc[ThePipeline::MaxThreads];
 279
 280     /** Last Committed PC */
 281     TheISA::PCState lastCommittedPC[ThePipeline::MaxThreads];
 282
 283     /** The Register File for the CPU */
 284     union {
 285         FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 286         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
 287     } floatRegs;
 288     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 289
 290     /** ISA state */
 291     TheISA::ISA isa[ThePipeline::MaxThreads];
 292
 293     /** Dependency Tracker for Integer & Floating Point Regs */
 294     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 295
 296     /** Register Types Used in Dependency Tracking */
 297     enum RegType { IntType, FloatType, MiscType, NumRegTypes};
 298
 299     /** Global communication structure */
 300     TimeBuffer<TimeStruct> timeBuffer;
 301
 302     /** Communication structure that sits in between pipeline stages */
 303     StageQueue *stageQueue[ThePipeline::NumStages-1];
 304
 305     TheISA::TLB *getITBPtr();
 306     TheISA::TLB *getDTBPtr();
 307
 308     /** Accessor Type for the SkedCache */
 309     typedef uint32_t SkedID;
 310
 311     /** Cache of Instruction Schedule using the instruction's name as a key */
 312     static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache;
 313
 314     typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt;
 315
 316     /** Initialized to last iterator in map, signifying a invalid entry
 317         on map searches
 318     */
 319     SkedCacheIt endOfSkedIt;
 320
 321     ThePipeline::RSkedPtr frontEndSked;
 322
 323     /** Add a new instruction schedule to the schedule cache */
 324     void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
 325     {
 326         SkedID sked_id = genSkedID(inst);
 327         assert(skedCache.find(sked_id) == skedCache.end());
 328         skedCache[sked_id] = inst_sked;
 329     }
 330
 331
 332     /** Find a instruction schedule */
 333     ThePipeline::RSkedPtr lookupSked(DynInstPtr inst)
 334     {
 335         SkedID sked_id = genSkedID(inst);
 336         SkedCacheIt lookup_it = skedCache.find(sked_id);
 337
 338         if (lookup_it != endOfSkedIt) {
 339             return (*lookup_it).second;
 340         } else {
 341             return NULL;
 342         }
 343     }
 344
 345     static const uint8_t INST_OPCLASS                       = 26;
 346     static const uint8_t INST_LOAD                          = 25;
 347     static const uint8_t INST_STORE                         = 24;
 348     static const uint8_t INST_CONTROL                       = 23;
 349     static const uint8_t INST_NONSPEC                       = 22;
 350     static const uint8_t INST_DEST_REGS                     = 18;
 351     static const uint8_t INST_SRC_REGS                      = 14;
 352     static const uint8_t INST_SPLIT_DATA                    = 13;
 353
 354     inline SkedID genSkedID(DynInstPtr inst)
 355     {
 356         SkedID id = 0;
 357         id = (inst->opClass() << INST_OPCLASS) |
 358             (inst->isLoad() << INST_LOAD) |
 359             (inst->isStore() << INST_STORE) |
 360             (inst->isControl() << INST_CONTROL) |
 361             (inst->isNonSpeculative() << INST_NONSPEC) |
 362             (inst->numDestRegs() << INST_DEST_REGS) |
 363             (inst->numSrcRegs() << INST_SRC_REGS) |
 364             (inst->splitInst << INST_SPLIT_DATA);
 365         return id;
 366     }
 367
 368     ThePipeline::RSkedPtr createFrontEndSked();
 369     ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
 370
 371     class StageScheduler {
 372       private:
 373         ThePipeline::RSkedPtr rsked;
 374         int stageNum;
 375         int nextTaskPriority;
 376
 377       public:
 378         StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
 379             : rsked(_rsked), stageNum(stage_num),
 380               nextTaskPriority(0)
 381         { }
 382
 383         void needs(int unit, int request) {
 384             rsked->push(new ScheduleEntry(
 385                             stageNum, nextTaskPriority++, unit, request
 386                             ));
 387         }
 388
 389         void needs(int unit, int request, int param) {
 390             rsked->push(new ScheduleEntry(
 391                             stageNum, nextTaskPriority++, unit, request, param
 392                             ));
 393         }
 394     };
 395
 396   public:
 397
 398     /** Registers statistics. */
 399     void regStats();
 400
 401     /** Ticks CPU, calling tick() on each stage, and checking the overall
 402      *  activity to see if the CPU should deschedule itself.
 403      */
 404     void tick();
 405
 406     /** Initialize the CPU */
 407     void init();
 408
 409     /** Get a Memory Port */
 410     Port* getPort(const std::string &if_name, int idx = 0);
 411
 412 #if FULL_SYSTEM
 413     /** HW return from error interrupt. */
 414     Fault hwrei(ThreadID tid);
 415
 416     bool simPalCheck(int palFunc, ThreadID tid);
 417
 418     void checkForInterrupts();
 419
 420     /** Returns the Fault for any valid interrupt. */
 421     Fault getInterrupts();
 422
 423     /** Processes any an interrupt fault. */
 424     void processInterrupts(Fault interrupt);
 425
 426     /** Halts the CPU. */
 427     void halt() { panic("Halt not implemented!\n"); }
 428
 429     /** Update the Virt and Phys ports of all ThreadContexts to
 430      * reflect change in memory connections. */
 431     void updateMemPorts();
 432
 433     /** Check if this address is a valid instruction address. */
 434     bool validInstAddr(Addr addr) { return true; }
 435
 436     /** Check if this address is a valid data address. */
 437     bool validDataAddr(Addr addr) { return true; }
 438 #else
 439     /** Schedule a syscall on the CPU */
 440     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
 441                         int delay = 0);
 442
 443     /** Executes a syscall.*/
 444     void syscall(int64_t callnum, ThreadID tid);
 445 #endif
 446
 447     /** Schedule a trap on the CPU */
 448     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
 449
 450     /** Perform trap to Handle Given Fault */
 451     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 452
 453     /** Schedule thread activation on the CPU */
 454     void activateContext(ThreadID tid, int delay = 0);
 455
 456     /** Add Thread to Active Threads List. */
 457     void activateThread(ThreadID tid);
 458
 459     /** Activate Thread In Each Pipeline Stage */
 460     void activateThreadInPipeline(ThreadID tid);
 461
 462     /** Schedule Thread Activation from Ready List */
 463     void activateNextReadyContext(int delay = 0);
 464
 465     /** Add Thread From Ready List to Active Threads List. */
 466     void activateNextReadyThread();
 467
 468     /** Schedule a thread deactivation on the CPU */
 469     void deactivateContext(ThreadID tid, int delay = 0);
 470
 471     /** Remove from Active Thread List */
 472     void deactivateThread(ThreadID tid);
 473
 474     /** Schedule a thread suspension on the CPU */
 475     void suspendContext(ThreadID tid, int delay = 0);
 476
 477     /** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
 478     void suspendThread(ThreadID tid);
 479
 480     /** Schedule a thread halt on the CPU */
 481     void haltContext(ThreadID tid, int delay = 0);
 482
 483     /** Halt Thread, Remove from Active Thread List, Place Thread on Halted
 484      *  Threads List
 485      */
 486     void haltThread(ThreadID tid);
 487
 488     /** squashFromMemStall() - sets up a squash event
 489      *  squashDueToMemStall() - squashes pipeline
 490      *  @note: maybe squashContext/squashThread would be better?
 491      */
 492     void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
 493     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 494
 495     void removePipelineStalls(ThreadID tid);
 496     void squashThreadInPipeline(ThreadID tid);
 497     void squashBehindMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);
 498
 499     PipelineStage* getPipeStage(int stage_num);
 500
 501     int
 502     contextId()
 503     {
 504         hack_once("return a bogus context id");
 505         return 0;
 506     }
 507
 508     /** Update The Order In Which We Process Threads. */
 509     void updateThreadPriority();
 510
 511     /** Switches a Pipeline Stage to Active. (Unused currently) */
 512     void switchToActive(int stage_idx)
 513     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 514
 515     /** Get the current instruction sequence number, and increment it. */
 516     InstSeqNum getAndIncrementInstSeq(ThreadID tid)
 517     { return globalSeqNum[tid]++; }
 518
 519     /** Get the current instruction sequence number, and increment it. */
 520     InstSeqNum nextInstSeqNum(ThreadID tid)
 521     { return globalSeqNum[tid]; }
 522
 523     /** Increment Instruction Sequence Number */
 524     void incrInstSeqNum(ThreadID tid)
 525     { globalSeqNum[tid]++; }
 526
 527     /** Set Instruction Sequence Number */
 528     void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
 529     {
 530         globalSeqNum[tid] = seq_num;
 531     }
 532
 533     /** Get & Update Next Event Number */
 534     InstSeqNum getNextEventNum()
 535     {
 536 #ifdef DEBUG
 537         return cpuEventNum++;
 538 #else
 539         return 0;
 540 #endif
 541     }
 542
 543     /** Register file accessors  */
 544     uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
 545
 546     FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
 547
 548     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 549
 550     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 551
 552     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 553
 554     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 555
 556     RegType inline getRegType(RegIndex reg_idx)
 557     {
 558         if (reg_idx < TheISA::FP_Base_DepTag)
 559             return IntType;
 560         else if (reg_idx < TheISA::Ctrl_Base_DepTag)
 561             return FloatType;
 562         else
 563             return MiscType;
 564     }
 565
 566     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 567
 568     /** Reads a miscellaneous register. */
 569     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 570
 571     /** Reads a misc. register, including any side effects the read
 572      * might have as defined by the architecture.
 573      */
 574     MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 575
 576     /** Sets a miscellaneous register. */
 577     void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
 578                             ThreadID tid = 0);
 579
 580     /** Sets a misc. register, including any side effects the write
 581      * might have as defined by the architecture.
 582      */
 583     void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 584
 585     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
 586      *  target thread
 587      */
 588     uint64_t readRegOtherThread(unsigned misc_reg,
 589                                 ThreadID tid = InvalidThreadID);
 590
 591     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
 592      * target thread
 593      */
 594     void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
 595                            ThreadID tid);
 596
 597     /** Reads the commit PC of a specific thread. */
 598     TheISA::PCState
 599     pcState(ThreadID tid)
 600     {
 601         return pc[tid];
 602     }
 603
 604     /** Sets the commit PC of a specific thread. */
 605     void
 606     pcState(const TheISA::PCState &newPC, ThreadID tid)
 607     {
 608         pc[tid] = newPC;
 609     }
 610
 611     Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
 612     Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
 613     MicroPC microPC(ThreadID tid) { return pc[tid].microPC(); }
 614
 615     /** Function to add instruction onto the head of the list of the
 616      *  instructions.  Used when new instructions are fetched.
 617      */
 618     ListIt addInst(DynInstPtr inst);
 619
 620     /** Find instruction on instruction list */
 621     ListIt findInst(InstSeqNum seq_num, ThreadID tid);
 622
 623     /** Function to tell the CPU that an instruction has completed. */
 624     void instDone(DynInstPtr inst, ThreadID tid);
 625
 626     /** Add Instructions to the CPU Remove List*/
 627     void addToRemoveList(DynInstPtr inst);
 628
 629     /** Remove an instruction from CPU */
 630     void removeInst(DynInstPtr inst);
 631
 632     /** Remove all instructions younger than the given sequence number. */
 633     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 634
 635     /** Removes the instruction pointed to by the iterator. */
 636     inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 637
 638     /** Cleans up all instructions on the instruction remove list. */
 639     void cleanUpRemovedInsts();
 640
 641     /** Cleans up all events on the CPU event remove list. */
 642     void cleanUpRemovedEvents();
 643
 644     /** Debug function to print all instructions on the list. */
 645     void dumpInsts();
 646
 647     /** Forwards an instruction read to the appropriate data
 648      *  resource (indexes into Resource Pool thru "dataPortIdx")
 649      */
 650     Fault read(DynInstPtr inst, Addr addr,
 651                uint8_t *data, unsigned size, unsigned flags);
 652
 653     /** Forwards an instruction write. to the appropriate data
 654      *  resource (indexes into Resource Pool thru "dataPortIdx")
 655      */
 656     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
 657                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 658
 659   public:
 660     /** Per-Thread List of all the instructions in flight. */
 661     std::list<DynInstPtr> instList[ThePipeline::MaxThreads];
 662
 663     /** List of all the instructions that will be removed at the end of this
 664      *  cycle.
 665      */
 666     std::queue<ListIt> removeList;
 667
 668     /** List of all the cpu event requests that will be removed at the end of
 669      *  the current cycle.
 670      */
 671     std::queue<Event*> cpuEventRemoveList;
 672
 673     /** Records if instructions need to be removed this cycle due to
 674      *  being retired or squashed.
 675      */
 676     bool removeInstsThisCycle;
 677
 678     /** True if there is non-speculative Inst Active In Pipeline. Lets any
 679      * execution unit know, NOT to execute while the instruction is active.
 680      */
 681     bool nonSpecInstActive[ThePipeline::MaxThreads];
 682
 683     /** Instruction Seq. Num of current non-speculative instruction. */
 684     InstSeqNum nonSpecSeqNum[ThePipeline::MaxThreads];
 685
 686     /** Instruction Seq. Num of last instruction squashed in pipeline */
 687     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 688
 689     /** Last Cycle that the CPU squashed instruction end. */
 690     Tick lastSquashCycle[ThePipeline::MaxThreads];
 691
 692     std::list<ThreadID> fetchPriorityList;
 693
 694   protected:
 695     /** Active Threads List */
 696     std::list<ThreadID> activeThreads;
 697
 698     /** Ready Threads List */
 699     std::list<ThreadID> readyThreads;
 700
 701     /** Suspended Threads List */
 702     std::list<ThreadID> suspendedThreads;
 703
 704     /** Halted Threads List */
 705     std::list<ThreadID> haltedThreads;
 706
 707     /** Thread Status Functions */
 708     bool isThreadActive(ThreadID tid);
 709     bool isThreadReady(ThreadID tid);
 710     bool isThreadSuspended(ThreadID tid);
 711
 712   private:
 713     /** The activity recorder; used to tell if the CPU has any
 714      * activity remaining or if it can go to idle and deschedule
 715      * itself.
 716      */
 717     ActivityRecorder activityRec;
 718
 719   public:
 720     /** Number of Active Threads in the CPU */
 721     ThreadID numActiveThreads() { return activeThreads.size(); }
 722
 723     /** Thread id of active thread
 724      *  Only used for SwitchOnCacheMiss model.
 725      *  Assumes only 1 thread active
 726      */
 727     ThreadID activeThreadId()
 728     {
 729         if (numActiveThreads() > 0)
 730             return activeThreads.front();
 731         else
 732             return InvalidThreadID;
 733     }
 734
 735
 736     /** Records that there was time buffer activity this cycle. */
 737     void activityThisCycle() { activityRec.activity(); }
 738
 739     /** Changes a stage's status to active within the activity recorder. */
 740     void activateStage(const int idx)
 741     { activityRec.activateStage(idx); }
 742
 743     /** Changes a stage's status to inactive within the activity recorder. */
 744     void deactivateStage(const int idx)
 745     { activityRec.deactivateStage(idx); }
 746
 747     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
 748     void wakeCPU();
 749
 750 #if FULL_SYSTEM
 751     virtual void wakeup();
 752 #endif
 753
 754     // LL/SC debug functionality
 755     unsigned stCondFails;
 756
 757     unsigned readStCondFailures()
 758     { return stCondFails; }
 759
 760     unsigned setStCondFailures(unsigned st_fails)
 761     { return stCondFails = st_fails; }
 762
 763     /** Returns a pointer to a thread context. */
 764     ThreadContext *tcBase(ThreadID tid = 0)
 765     {
 766         return thread[tid]->getTC();
 767     }
 768
 769     /** Count the Total Instructions Committed in the CPU. */
 770     virtual Counter totalInstructions() const
 771     {
 772         Counter total(0);
 773
 774         for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
 775             total += thread[tid]->numInst;
 776
 777         return total;
 778     }
 779
 780 #if FULL_SYSTEM
 781     /** Pointer to the system. */
 782     System *system;
 783 #endif
 784
 785     /** The global sequence number counter. */
 786     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
 787
 788 #ifdef DEBUG
 789     /** The global event number counter. */
 790     InstSeqNum cpuEventNum;
 791
 792     /** Number of resource requests active in CPU **/
 793     unsigned resReqCount;
 794 #endif
 795
 796     Addr lockAddr;
 797
 798     /** Temporary fix for the lock flag, works in the UP case. */
 799     bool lockFlag;
 800
 801     /** Counter of how many stages have completed draining */
 802     int drainCount;
 803
 804     /** Pointers to all of the threads in the CPU. */
 805     std::vector<Thread *> thread;
 806
 807     /** Pointer to the icache interface. */
 808     MemInterface *icacheInterface;
 809
 810     /** Pointer to the dcache interface. */
 811     MemInterface *dcacheInterface;
 812
 813     /** Whether or not the CPU should defer its registration. */
 814     bool deferRegistration;
 815
 816     /** Per-Stage Instruction Tracing */
 817     bool stageTracing;
 818
 819     /** The cycle that the CPU was last running, used for statistics. */
 820     Tick lastRunningCycle;
 821
 822     void updateContextSwitchStats();
 823     unsigned instsPerSwitch;
 824     Stats::Average instsPerCtxtSwitch;
 825     Stats::Scalar numCtxtSwitches;
 826
 827     /** Update Thread , used for statistic purposes*/
 828     inline void tickThreadStats();
 829
 830     /** Per-Thread Tick */
 831     Stats::Vector threadCycles;
 832
 833     /** Tick for SMT */
 834     Stats::Scalar smtCycles;
 835
 836     /** Stat for total number of times the CPU is descheduled. */
 837     Stats::Scalar timesIdled;
 838
 839     /** Stat for total number of cycles the CPU spends descheduled or no
 840      *  stages active.
 841      */
 842     Stats::Scalar idleCycles;
 843
 844     /** Stat for total number of cycles the CPU is active. */
 845     Stats::Scalar runCycles;
 846
 847     /** Percentage of cycles a stage was active */
 848     Stats::Formula activity;
 849
 850     /** Instruction Mix Stats */
 851     Stats::Scalar comLoads;
 852     Stats::Scalar comStores;
 853     Stats::Scalar comBranches;
 854     Stats::Scalar comNops;
 855     Stats::Scalar comNonSpec;
 856     Stats::Scalar comInts;
 857     Stats::Scalar comFloats;
 858
 859     /** Stat for the number of committed instructions per thread. */
 860     Stats::Vector committedInsts;
 861
 862     /** Stat for the number of committed instructions per thread. */
 863     Stats::Vector smtCommittedInsts;
 864
 865     /** Stat for the total number of committed instructions. */
 866     Stats::Scalar totalCommittedInsts;
 867
 868     /** Stat for the CPI per thread. */
 869     Stats::Formula cpi;
 870
 871     /** Stat for the SMT-CPI per thread. */
 872     Stats::Formula smtCpi;
 873
 874     /** Stat for the total CPI. */
 875     Stats::Formula totalCpi;
 876
 877     /** Stat for the IPC per thread. */
 878     Stats::Formula ipc;
 879
 880     /** Stat for the total IPC. */
 881     Stats::Formula smtIpc;
 882
 883     /** Stat for the total IPC. */
 884     Stats::Formula totalIpc;
 885 };
 886
 887 #endif // __CPU_O3_CPU_HH__