cpu: Refactor memory system checks
[gem5.git] / src / cpu / inorder / first_stage.hh
1 /*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 *
30 */
31
32 #ifndef __CPU_INORDER_FIRST_STAGE_HH__
33 #define __CPU_INORDER_FIRST_STAGE_HH__
34
35 #include <queue>
36 #include <vector>
37
38 #include "base/statistics.hh"
39 #include "cpu/inorder/comm.hh"
40 #include "cpu/inorder/inorder_dyn_inst.hh"
41 #include "cpu/inorder/pipeline_stage.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/timebuf.hh"
44
45 class InOrderCPU;
46
47 class FirstStage : public PipelineStage {
48 public:
49 FirstStage(ThePipeline::Params *params, unsigned stage_num);
50
51 /** Set Pointer to CPU */
52 void setCPU(InOrderCPU *cpu_ptr);
53
54 /** Evaluate Stage Info. & Execute Stage */
55 void processStage(bool &status_change);
56
57 /** Process All Instructions Available */
58 void processInsts(ThreadID tid);
59
60 /** Squash Instructions Above a Seq. Num */
61 void squash(InstSeqNum squash_seq_num, ThreadID tid);
62
63 void squashDueToMemStall(InstSeqNum seq_num, ThreadID tid);
64
65 /** There are no insts. coming from previous stages, so there is
66 * no need to sort insts here
67 */
68 void sortInsts() {}
69
70 /** The number of fetching threads in the CPU */
71 int numFetchingThreads;
72
73 //@TODO: Add fetch priority information to a resource class...
74 /** Fetching Policy, Add new policies here.*/
75 enum FetchPriority {
76 SingleThread,
77 RoundRobin
78 };
79
80 /** Fetch policy. */
81 FetchPriority fetchPolicy;
82
83 /** List that has the threads organized by priority. */
84 std::list<ThreadID> *fetchPriorityList;
85
86 /** Return the next fetching thread */
87 ThreadID getFetchingThread(FetchPriority &fetch_priority);
88
89 /** Return next thread given Round Robin Policy for Thread Fetching */
90 ThreadID roundRobin();
91 };
92
93 #endif // __CPU_INORDER_FIRST_STAGE_HH__