src/cpu/inorder/inorder_dyn_inst.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <iostream>
  33 #include <set>
  34 #include <string>
  35 #include <sstream>
  36
  37 #include "base/cprintf.hh"
  38 #include "base/trace.hh"
  39
  40 #include "arch/faults.hh"
  41 #include "cpu/exetrace.hh"
  42 #include "mem/request.hh"
  43
  44 #include "cpu/inorder/inorder_dyn_inst.hh"
  45 #include "cpu/inorder/cpu.hh"
  46
  47 using namespace std;
  48 using namespace TheISA;
  49 using namespace ThePipeline;
  50
  51 InOrderDynInst::InOrderDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
  52                                Addr pred_PC, InstSeqNum seq_num,
  53                                InOrderCPU *cpu)
  54   : staticInst(machInst, inst_PC), traceData(NULL), cpu(cpu)
  55 {
  56     seqNum = seq_num;
  57
  58     PC = inst_PC;
  59     nextPC = PC + sizeof(MachInst);
  60     nextNPC = nextPC + sizeof(MachInst);
  61     predPC = pred_PC;
  62
  63     initVars();
  64 }
  65
  66 InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
  67                            InOrderThreadState *state,
  68                            InstSeqNum seq_num,
  69                            unsigned tid)
  70     : traceData(NULL), cpu(cpu)
  71 {
  72     seqNum = seq_num;
  73     thread = state;
  74     threadNumber = tid;
  75     initVars();
  76 }
  77
  78 InOrderDynInst::InOrderDynInst(StaticInstPtr &_staticInst)
  79     : staticInst(_staticInst), traceData(NULL)
  80 {
  81     seqNum = 0;
  82     initVars();
  83 }
  84
  85 InOrderDynInst::InOrderDynInst()
  86     : traceData(NULL), cpu(cpu)
  87 {     initVars(); }
  88
  89 int InOrderDynInst::instcount = 0;
  90
  91
  92 void
  93 InOrderDynInst::setMachInst(ExtMachInst machInst)
  94 {
  95     staticInst = StaticInst::decode(machInst, PC);
  96
  97     for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
  98         _destRegIdx[i] = this->staticInst->destRegIdx(i);
  99     }
 100
 101     for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 102         _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 103         this->_readySrcRegIdx[i] = 0;
 104     }
 105 }
 106
 107 void
 108 InOrderDynInst::initVars()
 109 {
 110     req = NULL;
 111     effAddr = 0;
 112     physEffAddr = 0;
 113
 114     readyRegs = 0;
 115
 116     nextStage = 0;
 117     nextInstStageNum = 0;
 118
 119     for(int i = 0; i < MaxInstDestRegs; i++)
 120         instResult[i].val.integer = 0;
 121
 122     status.reset();
 123
 124     memAddrReady = false;
 125     eaCalcDone = false;
 126     memOpDone = false;
 127
 128     predictTaken = false;
 129     procDelaySlotOnMispred = false;
 130
 131     lqIdx = -1;
 132     sqIdx = -1;
 133
 134     // Also make this a parameter, or perhaps get it from xc or cpu.
 135     asid = 0;
 136
 137     virtProcNumber = 0;
 138
 139     // Initialize the fault to be NoFault.
 140     fault = NoFault;
 141
 142     // Make sure to have the renamed register entries set to the same
 143     // as the normal register entries.  It will allow the IQ to work
 144     // without any modifications.
 145     if (this->staticInst) {
 146         for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
 147             _destRegIdx[i] = this->staticInst->destRegIdx(i);
 148         }
 149
 150         for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 151             _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 152             this->_readySrcRegIdx[i] = 0;
 153         }
 154     }
 155
 156     // Update Instruction Count for this instruction
 157     ++instcount;
 158     if (instcount > 500) {
 159         fatal("Number of Active Instructions in CPU is too high. "
 160                 "(Not Dereferencing Ptrs. Correctly?)\n");
 161     }
 162
 163
 164
 165     DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created. (active insts: %i)\n",
 166             threadNumber, seqNum, instcount);
 167
 168 #ifdef DEBUG
 169     cpu->snList.insert(seqNum);
 170 #endif
 171 }
 172
 173
 174 InOrderDynInst::~InOrderDynInst()
 175 {
 176     if (req) {
 177         delete req;
 178     }
 179
 180     if (traceData) {
 181         delete traceData;
 182     }
 183
 184     fault = NoFault;
 185
 186     --instcount;
 187
 188     deleteStages();
 189
 190     DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed. (active insts: %i)\n",
 191             threadNumber, seqNum, instcount);
 192 #ifdef DEBUG
 193     cpu->snList.erase(seqNum);
 194 #endif
 195 }
 196
 197 void
 198 InOrderDynInst::setStaticInst(StaticInstPtr &static_inst)
 199 {
 200     this->staticInst = static_inst;
 201
 202     // Make sure to have the renamed register entries set to the same
 203     // as the normal register entries.  It will allow the IQ to work
 204     // without any modifications.
 205     if (this->staticInst) {
 206         for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
 207             _destRegIdx[i] = this->staticInst->destRegIdx(i);
 208         }
 209
 210         for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 211             _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 212             this->_readySrcRegIdx[i] = 0;
 213         }
 214     }
 215 }
 216
 217 Fault
 218 InOrderDynInst::execute()
 219 {
 220     // @todo: Pretty convoluted way to avoid squashing from happening
 221     // when using the TC during an instruction's execution
 222     // (specifically for instructions that have side-effects that use
 223     // the TC).  Fix this.
 224     bool in_syscall = this->thread->inSyscall;
 225     this->thread->inSyscall = true;
 226
 227     this->fault = this->staticInst->execute(this, this->traceData);
 228
 229     this->thread->inSyscall = in_syscall;
 230
 231     return this->fault;
 232 }
 233
 234 Fault
 235 InOrderDynInst::initiateAcc()
 236 {
 237     // @todo: Pretty convoluted way to avoid squashing from happening
 238     // when using the TC during an instruction's execution
 239     // (specifically for instructions that have side-effects that use
 240     // the TC).  Fix this.
 241     bool in_syscall = this->thread->inSyscall;
 242     this->thread->inSyscall = true;
 243
 244     this->fault = this->staticInst->initiateAcc(this, this->traceData);
 245
 246     this->thread->inSyscall = in_syscall;
 247
 248     return this->fault;
 249 }
 250
 251
 252 Fault
 253 InOrderDynInst::completeAcc(Packet *pkt)
 254 {
 255     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 256
 257     return this->fault;
 258 }
 259
 260 InstStage *InOrderDynInst::addStage()
 261 {
 262     this->currentInstStage = new InstStage(this, nextInstStageNum++);
 263     instStageList.push_back( this->currentInstStage );
 264     return this->currentInstStage;
 265 }
 266
 267 InstStage *InOrderDynInst::addStage(int stage_num)
 268 {
 269     nextInstStageNum = stage_num;
 270     return InOrderDynInst::addStage();
 271 }
 272
 273 void InOrderDynInst::deleteStages() {
 274     std::list<InstStage*>::iterator list_it = instStageList.begin();
 275     std::list<InstStage*>::iterator list_end = instStageList.end();
 276
 277     while(list_it != list_end) {
 278         delete *list_it;
 279         list_it++;
 280     }
 281 }
 282
 283 Fault
 284 InOrderDynInst::calcEA()
 285 {
 286     return staticInst->eaCompInst()->execute(this, this->traceData);
 287 }
 288
 289 Fault
 290 InOrderDynInst::memAccess()
 291 {
 292     //return staticInst->memAccInst()->execute(this, this->traceData);
 293     return initiateAcc( );
 294 }
 295
 296 void
 297 InOrderDynInst::syscall(int64_t callnum)
 298 {
 299     cpu->syscall(callnum, this->threadNumber);
 300 }
 301
 302 void
 303 InOrderDynInst::prefetch(Addr addr, unsigned flags)
 304 {
 305     // This is the "functional" implementation of prefetch.  Not much
 306     // happens here since prefetches don't affect the architectural
 307     // state.
 308 /*
 309     // Generate a MemReq so we can translate the effective address.
 310     MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
 311     req->asid = asid;
 312
 313     // Prefetches never cause faults.
 314     fault = NoFault;
 315
 316     // note this is a local, not InOrderDynInst::fault
 317     Fault trans_fault = cpu->translateDataReadReq(req);
 318
 319     if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
 320         // It's a valid address to cacheable space.  Record key MemReq
 321         // parameters so we can generate another one just like it for
 322         // the timing access without calling translate() again (which
 323         // might mess up the TLB).
 324         effAddr = req->vaddr;
 325         physEffAddr = req->paddr;
 326         memReqFlags = req->flags;
 327     } else {
 328         // Bogus address (invalid or uncacheable space).  Mark it by
 329         // setting the eff_addr to InvalidAddr.
 330         effAddr = physEffAddr = MemReq::inval_addr;
 331     }
 332
 333     if (traceData) {
 334         traceData->setAddr(addr);
 335     }
 336 */
 337 }
 338
 339 void
 340 InOrderDynInst::writeHint(Addr addr, int size, unsigned flags)
 341 {
 342     // Not currently supported.
 343 }
 344
 345 /**
 346  * @todo Need to find a way to get the cache block size here.
 347  */
 348 Fault
 349 InOrderDynInst::copySrcTranslate(Addr src)
 350 {
 351     // Not currently supported.
 352     return NoFault;
 353 }
 354
 355 /**
 356  * @todo Need to find a way to get the cache block size here.
 357  */
 358 Fault
 359 InOrderDynInst::copy(Addr dest)
 360 {
 361     // Not currently supported.
 362     return NoFault;
 363 }
 364
 365 void
 366 InOrderDynInst::releaseReq(ResourceRequest* req)
 367 {
 368     std::list<ResourceRequest*>::iterator list_it = reqList.begin();
 369     std::list<ResourceRequest*>::iterator list_end = reqList.end();
 370
 371     while(list_it != list_end) {
 372         if((*list_it)->getResIdx() == req->getResIdx() &&
 373            (*list_it)->getSlot() == req->getSlot()) {
 374             DPRINTF(InOrderDynInst, "[tid:%u]: [sn:%i] Done with request to %s.\n",
 375                     threadNumber, seqNum, req->res->name());
 376             reqList.erase(list_it);
 377             return;
 378         }
 379         list_it++;
 380     }
 381
 382     panic("Releasing Res. Request That Isnt There!\n");
 383 }
 384
 385 /** Records an integer source register being set to a value. */
 386 void
 387 InOrderDynInst::setIntSrc(int idx, uint64_t val)
 388 {
 389     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set to %#x.\n",
 390             threadNumber, seqNum, idx, val);
 391     instSrc[idx].integer = val;
 392 }
 393
 394 /** Records an fp register being set to a value. */
 395 void
 396 InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width)
 397 {
 398     if (width == 32)
 399         instSrc[idx].fp = val;
 400     else if (width == 64)
 401         instSrc[idx].dbl = val;
 402     else
 403         panic("Unsupported width!");
 404 }
 405
 406 /** Records an fp register being set to an integer value. */
 407 void
 408 InOrderDynInst::setFloatRegBitsSrc(int idx, uint64_t val)
 409 {
 410     instSrc[idx].integer = val;
 411 }
 412
 413 /** Reads a integer register. */
 414 IntReg
 415 InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, unsigned tid)
 416 {
 417     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
 418             threadNumber, seqNum, idx, instSrc[idx].integer);
 419     return instSrc[idx].integer;
 420 }
 421
 422 /** Reads a FP register. */
 423 FloatReg
 424 InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width)
 425 {
 426    return instSrc[idx].fp;
 427 }
 428
 429
 430 /** Reads a FP register as a integer. */
 431 FloatRegBits
 432 InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx, int width)
 433 {
 434     return instSrc[idx].integer;
 435 }
 436
 437 /** Reads a miscellaneous register. */
 438 MiscReg
 439 InOrderDynInst::readMiscReg(int misc_reg)
 440 {
 441     return this->cpu->readMiscReg(misc_reg, threadNumber);
 442 }
 443
 444 /** Reads a misc. register, including any side-effects the read
 445  * might have as defined by the architecture.
 446  */
 447 MiscReg
 448 InOrderDynInst::readMiscRegNoEffect(int misc_reg)
 449 {
 450     return this->cpu->readMiscRegNoEffect(misc_reg, threadNumber);
 451 }
 452
 453 /** Reads a miscellaneous register. */
 454 MiscReg
 455 InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
 456 {
 457     int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
 458     return cpu->readMiscRegNoEffect(reg, this->threadNumber);
 459 }
 460
 461 /** Reads a misc. register, including any side-effects the read
 462  * might have as defined by the architecture.
 463  */
 464 MiscReg
 465 InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
 466 {
 467     int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
 468     return this->cpu->readMiscReg(reg, this->threadNumber);
 469 }
 470
 471 /** Sets a misc. register. */
 472 void
 473 InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
 474 {
 475     instResult[si->destRegIdx(idx)].val.integer = val;
 476     instResult[si->destRegIdx(idx)].tick = curTick;
 477
 478     this->cpu->setMiscRegNoEffect(
 479         si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
 480         val, this->threadNumber);
 481 }
 482
 483 /** Sets a misc. register, including any side-effects the write
 484  * might have as defined by the architecture.
 485  */
 486 void
 487 InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
 488                        const MiscReg &val)
 489 {
 490     instResult[si->destRegIdx(idx)].val.integer = val;
 491     instResult[si->destRegIdx(idx)].tick = curTick;
 492
 493     this->cpu->setMiscReg(
 494         si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
 495         val, this->threadNumber);
 496 }
 497
 498 MiscReg
 499 InOrderDynInst::readRegOtherThread(unsigned reg_idx, int tid)
 500 {
 501     if (tid == -1) {
 502         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
 503     }
 504
 505     if (reg_idx < FP_Base_DepTag) {                   // Integer Register File
 506         return this->cpu->readIntReg(reg_idx, tid);
 507     } else if (reg_idx < Ctrl_Base_DepTag) {          // Float Register File
 508         reg_idx -= FP_Base_DepTag;
 509         return this->cpu->readFloatRegBits(reg_idx, tid);
 510     } else {
 511         reg_idx -= Ctrl_Base_DepTag;
 512         return this->cpu->readMiscReg(reg_idx, tid);  // Misc. Register File
 513     }
 514 }
 515
 516 /** Sets a Integer register. */
 517 void
 518 InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
 519 {
 520     instResult[idx].val.integer = val;
 521     instResult[idx].tick = curTick;
 522 }
 523
 524 /** Sets a FP register. */
 525 void
 526 InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, int width)
 527 {
 528     if (width == 32)
 529         instResult[idx].val.fp = val;
 530     else if (width == 64)
 531         instResult[idx].val.dbl = val;
 532     else
 533         panic("Unsupported Floating Point Width!");
 534
 535     instResult[idx].tick = curTick;
 536 }
 537
 538 /** Sets a FP register as a integer. */
 539 void
 540 InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
 541                               FloatRegBits val, int width)
 542 {
 543     instResult[idx].val.integer = val;
 544     instResult[idx].tick = curTick;
 545 }
 546
 547 /** Sets a misc. register. */
 548 /* Alter this when wanting to *speculate* on Miscellaneous registers */
 549 void
 550 InOrderDynInst::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 551 {
 552     this->cpu->setMiscRegNoEffect(misc_reg, val, threadNumber);
 553 }
 554
 555 /** Sets a misc. register, including any side-effects the write
 556  * might have as defined by the architecture.
 557  */
 558 /* Alter this if/when wanting to *speculate* on Miscellaneous registers */
 559 void
 560 InOrderDynInst::setMiscReg(int misc_reg, const MiscReg &val)
 561 {
 562     this->cpu->setMiscReg(misc_reg, val, threadNumber);
 563 }
 564
 565 void
 566 InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val, int tid)
 567 {
 568     if (tid == -1) {
 569         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
 570     }
 571
 572     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
 573         this->cpu->setIntReg(reg_idx, val, tid);
 574     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
 575         reg_idx -= FP_Base_DepTag;
 576         this->cpu->setFloatRegBits(reg_idx, val, tid);
 577     } else {
 578         reg_idx -= Ctrl_Base_DepTag;
 579         this->cpu->setMiscReg(reg_idx, val, tid); // Misc. Register File
 580     }
 581 }
 582
 583 void
 584 InOrderDynInst::deallocateContext(int thread_num)
 585 {
 586     this->cpu->deallocateContext(thread_num);
 587 }
 588
 589 void
 590 InOrderDynInst::enableVirtProcElement(unsigned vpe)
 591 {
 592     this->cpu->enableVirtProcElement(vpe);
 593 }
 594
 595 void
 596 InOrderDynInst::disableVirtProcElement(unsigned vpe)
 597 {
 598     this->cpu->disableVirtProcElement(threadNumber, vpe);
 599 }
 600
 601 void
 602 InOrderDynInst::enableMultiThreading(unsigned vpe)
 603 {
 604     this->cpu->enableMultiThreading(vpe);
 605 }
 606
 607 void
 608 InOrderDynInst::disableMultiThreading(unsigned vpe)
 609 {
 610     this->cpu->disableMultiThreading(threadNumber, vpe);
 611 }
 612
 613 void
 614 InOrderDynInst::setThreadRescheduleCondition(uint32_t cond)
 615 {
 616     this->cpu->setThreadRescheduleCondition(cond);
 617 }
 618
 619 template<class T>
 620 inline Fault
 621 InOrderDynInst::read(Addr addr, T &data, unsigned flags)
 622 {
 623     return cpu->read(this);
 624 }
 625
 626 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 627
 628 template
 629 Fault
 630 InOrderDynInst::read(Addr addr, uint64_t &data, unsigned flags);
 631
 632 template
 633 Fault
 634 InOrderDynInst::read(Addr addr, uint32_t &data, unsigned flags);
 635
 636 template
 637 Fault
 638 InOrderDynInst::read(Addr addr, uint16_t &data, unsigned flags);
 639
 640 template
 641 Fault
 642 InOrderDynInst::read(Addr addr, uint8_t &data, unsigned flags);
 643
 644 #endif //DOXYGEN_SHOULD_SKIP_THIS
 645
 646 template<>
 647 Fault
 648 InOrderDynInst::read(Addr addr, double &data, unsigned flags)
 649 {
 650     return read(addr, *(uint64_t*)&data, flags);
 651 }
 652
 653 template<>
 654 Fault
 655 InOrderDynInst::read(Addr addr, float &data, unsigned flags)
 656 {
 657     return read(addr, *(uint32_t*)&data, flags);
 658 }
 659
 660 template<>
 661 Fault
 662 InOrderDynInst::read(Addr addr, int32_t &data, unsigned flags)
 663 {
 664     return read(addr, (uint32_t&)data, flags);
 665 }
 666
 667 template<class T>
 668 inline Fault
 669 InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
 670 {
 671     //memcpy(memData, gtoh(data), sizeof(T));
 672     storeData  = data;
 673
 674     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting store data to %#x.\n",
 675             threadNumber, seqNum, memData);
 676     return cpu->write(this);
 677 }
 678
 679 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 680 template
 681 Fault
 682 InOrderDynInst::write(uint64_t data, Addr addr,
 683                        unsigned flags, uint64_t *res);
 684
 685 template
 686 Fault
 687 InOrderDynInst::write(uint32_t data, Addr addr,
 688                        unsigned flags, uint64_t *res);
 689
 690 template
 691 Fault
 692 InOrderDynInst::write(uint16_t data, Addr addr,
 693                        unsigned flags, uint64_t *res);
 694
 695 template
 696 Fault
 697 InOrderDynInst::write(uint8_t data, Addr addr,
 698                        unsigned flags, uint64_t *res);
 699
 700 #endif //DOXYGEN_SHOULD_SKIP_THIS
 701
 702 template<>
 703 Fault
 704 InOrderDynInst::write(double data, Addr addr, unsigned flags, uint64_t *res)
 705 {
 706     return write(*(uint64_t*)&data, addr, flags, res);
 707 }
 708
 709 template<>
 710 Fault
 711 InOrderDynInst::write(float data, Addr addr, unsigned flags, uint64_t *res)
 712 {
 713     return write(*(uint32_t*)&data, addr, flags, res);
 714 }
 715
 716
 717 template<>
 718 Fault
 719 InOrderDynInst::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 720 {
 721     return write((uint32_t)data, addr, flags, res);
 722 }
 723
 724
 725 void
 726 InOrderDynInst::dump()
 727 {
 728     cprintf("T%d : %#08d `", threadNumber, PC);
 729     cout << staticInst->disassemble(PC);
 730     cprintf("'\n");
 731 }
 732
 733 void
 734 InOrderDynInst::dump(std::string &outstring)
 735 {
 736     std::ostringstream s;
 737     s << "T" << threadNumber << " : 0x" << PC << " "
 738       << staticInst->disassemble(PC);
 739
 740     outstring = s.str();
 741 }
 742
 743
 744 #define NOHASH
 745 #ifndef NOHASH
 746
 747 #include "base/hashmap.hh"
 748
 749 unsigned int MyHashFunc(const InOrderDynInst *addr)
 750 {
 751     unsigned a = (unsigned)addr;
 752     unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
 753
 754     return hash;
 755 }
 756
 757 typedef m5::hash_map<const InOrderDynInst *, const InOrderDynInst *, MyHashFunc>
 758 my_hash_t;
 759
 760 my_hash_t thishash;
 761 #endif
 762
 763 #ifdef DEBUG
 764
 765 void
 766 InOrderDynInst::dumpSNList()
 767 {
 768     std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
 769
 770     int count = 0;
 771     while (sn_it != cpu->snList.end()) {
 772         cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
 773         count++;
 774         sn_it++;
 775     }
 776 }
 777 #endif
 778