src/cpu/inorder/inorder_dyn_inst.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <iostream>
  33 #include <set>
  34 #include <string>
  35 #include <sstream>
  36
  37 #include "base/cprintf.hh"
  38 #include "base/trace.hh"
  39
  40 #include "arch/faults.hh"
  41 #include "cpu/exetrace.hh"
  42 #include "mem/request.hh"
  43
  44 #include "cpu/inorder/inorder_dyn_inst.hh"
  45 #include "cpu/inorder/cpu.hh"
  46
  47 using namespace std;
  48 using namespace TheISA;
  49 using namespace ThePipeline;
  50
  51 InOrderDynInst::InOrderDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
  52                                Addr pred_PC, InstSeqNum seq_num,
  53                                InOrderCPU *cpu)
  54   : staticInst(machInst, inst_PC), traceData(NULL), cpu(cpu)
  55 {
  56     seqNum = seq_num;
  57
  58     PC = inst_PC;
  59     nextPC = PC + sizeof(MachInst);
  60     nextNPC = nextPC + sizeof(MachInst);
  61     predPC = pred_PC;
  62
  63     initVars();
  64 }
  65
  66 InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
  67                            InOrderThreadState *state,
  68                            InstSeqNum seq_num,
  69                            unsigned tid)
  70     : traceData(NULL), cpu(cpu)
  71 {
  72     seqNum = seq_num;
  73     thread = state;
  74     threadNumber = tid;
  75     initVars();
  76 }
  77
  78 InOrderDynInst::InOrderDynInst(StaticInstPtr &_staticInst)
  79     : seqNum(0), staticInst(_staticInst), traceData(NULL)
  80 {
  81     initVars();
  82 }
  83
  84 InOrderDynInst::InOrderDynInst()
  85     : seqNum(0), traceData(NULL), cpu(cpu)
  86 {
  87     initVars();
  88 }
  89
  90 int InOrderDynInst::instcount = 0;
  91
  92
  93 void
  94 InOrderDynInst::setMachInst(ExtMachInst machInst)
  95 {
  96     staticInst = StaticInst::decode(machInst, PC);
  97
  98     for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
  99         _destRegIdx[i] = this->staticInst->destRegIdx(i);
 100     }
 101
 102     for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 103         _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 104         this->_readySrcRegIdx[i] = 0;
 105     }
 106 }
 107
 108 void
 109 InOrderDynInst::initVars()
 110 {
 111     req = NULL;
 112     effAddr = 0;
 113     physEffAddr = 0;
 114
 115     readyRegs = 0;
 116
 117     nextStage = 0;
 118     nextInstStageNum = 0;
 119
 120     for(int i = 0; i < MaxInstDestRegs; i++)
 121         instResult[i].val.integer = 0;
 122
 123     status.reset();
 124
 125     memAddrReady = false;
 126     eaCalcDone = false;
 127     memOpDone = false;
 128
 129     predictTaken = false;
 130     procDelaySlotOnMispred = false;
 131
 132     lqIdx = -1;
 133     sqIdx = -1;
 134
 135     // Also make this a parameter, or perhaps get it from xc or cpu.
 136     asid = 0;
 137
 138     virtProcNumber = 0;
 139
 140     // Initialize the fault to be NoFault.
 141     fault = NoFault;
 142
 143     // Make sure to have the renamed register entries set to the same
 144     // as the normal register entries.  It will allow the IQ to work
 145     // without any modifications.
 146     if (this->staticInst) {
 147         for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
 148             _destRegIdx[i] = this->staticInst->destRegIdx(i);
 149         }
 150
 151         for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 152             _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 153             this->_readySrcRegIdx[i] = 0;
 154         }
 155     }
 156
 157     // Update Instruction Count for this instruction
 158     ++instcount;
 159     if (instcount > 500) {
 160         fatal("Number of Active Instructions in CPU is too high. "
 161                 "(Not Dereferencing Ptrs. Correctly?)\n");
 162     }
 163
 164
 165
 166     DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created. (active insts: %i)\n",
 167             threadNumber, seqNum, instcount);
 168 }
 169
 170
 171 InOrderDynInst::~InOrderDynInst()
 172 {
 173     if (req) {
 174         delete req;
 175     }
 176
 177     if (traceData) {
 178         delete traceData;
 179     }
 180
 181     fault = NoFault;
 182
 183     --instcount;
 184
 185     deleteStages();
 186
 187     DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed. (active insts: %i)\n",
 188             threadNumber, seqNum, instcount);
 189 }
 190
 191 void
 192 InOrderDynInst::setStaticInst(StaticInstPtr &static_inst)
 193 {
 194     this->staticInst = static_inst;
 195
 196     // Make sure to have the renamed register entries set to the same
 197     // as the normal register entries.  It will allow the IQ to work
 198     // without any modifications.
 199     if (this->staticInst) {
 200         for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
 201             _destRegIdx[i] = this->staticInst->destRegIdx(i);
 202         }
 203
 204         for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 205             _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 206             this->_readySrcRegIdx[i] = 0;
 207         }
 208     }
 209 }
 210
 211 Fault
 212 InOrderDynInst::execute()
 213 {
 214     // @todo: Pretty convoluted way to avoid squashing from happening
 215     // when using the TC during an instruction's execution
 216     // (specifically for instructions that have side-effects that use
 217     // the TC).  Fix this.
 218     bool in_syscall = this->thread->inSyscall;
 219     this->thread->inSyscall = true;
 220
 221     this->fault = this->staticInst->execute(this, this->traceData);
 222
 223     this->thread->inSyscall = in_syscall;
 224
 225     return this->fault;
 226 }
 227
 228 Fault
 229 InOrderDynInst::initiateAcc()
 230 {
 231     // @todo: Pretty convoluted way to avoid squashing from happening
 232     // when using the TC during an instruction's execution
 233     // (specifically for instructions that have side-effects that use
 234     // the TC).  Fix this.
 235     bool in_syscall = this->thread->inSyscall;
 236     this->thread->inSyscall = true;
 237
 238     this->fault = this->staticInst->initiateAcc(this, this->traceData);
 239
 240     this->thread->inSyscall = in_syscall;
 241
 242     return this->fault;
 243 }
 244
 245
 246 Fault
 247 InOrderDynInst::completeAcc(Packet *pkt)
 248 {
 249     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 250
 251     return this->fault;
 252 }
 253
 254 InstStage *InOrderDynInst::addStage()
 255 {
 256     this->currentInstStage = new InstStage(this, nextInstStageNum++);
 257     instStageList.push_back( this->currentInstStage );
 258     return this->currentInstStage;
 259 }
 260
 261 InstStage *InOrderDynInst::addStage(int stage_num)
 262 {
 263     nextInstStageNum = stage_num;
 264     return InOrderDynInst::addStage();
 265 }
 266
 267 void InOrderDynInst::deleteStages() {
 268     std::list<InstStage*>::iterator list_it = instStageList.begin();
 269     std::list<InstStage*>::iterator list_end = instStageList.end();
 270
 271     while(list_it != list_end) {
 272         delete *list_it;
 273         list_it++;
 274     }
 275 }
 276
 277 Fault
 278 InOrderDynInst::calcEA()
 279 {
 280     return staticInst->eaCompInst()->execute(this, this->traceData);
 281 }
 282
 283 Fault
 284 InOrderDynInst::memAccess()
 285 {
 286     //return staticInst->memAccInst()->execute(this, this->traceData);
 287     return initiateAcc( );
 288 }
 289
 290 void
 291 InOrderDynInst::syscall(int64_t callnum)
 292 {
 293     cpu->syscall(callnum, this->threadNumber);
 294 }
 295
 296 void
 297 InOrderDynInst::prefetch(Addr addr, unsigned flags)
 298 {
 299     panic("Prefetch Unimplemented\n");
 300 }
 301
 302 void
 303 InOrderDynInst::writeHint(Addr addr, int size, unsigned flags)
 304 {
 305     panic("Write-Hint Unimplemented\n");
 306 }
 307
 308 /**
 309  * @todo Need to find a way to get the cache block size here.
 310  */
 311 Fault
 312 InOrderDynInst::copySrcTranslate(Addr src)
 313 {
 314     // Not currently supported.
 315     return NoFault;
 316 }
 317
 318 /**
 319  * @todo Need to find a way to get the cache block size here.
 320  */
 321 Fault
 322 InOrderDynInst::copy(Addr dest)
 323 {
 324     // Not currently supported.
 325     return NoFault;
 326 }
 327
 328 void
 329 InOrderDynInst::releaseReq(ResourceRequest* req)
 330 {
 331     std::list<ResourceRequest*>::iterator list_it = reqList.begin();
 332     std::list<ResourceRequest*>::iterator list_end = reqList.end();
 333
 334     while(list_it != list_end) {
 335         if((*list_it)->getResIdx() == req->getResIdx() &&
 336            (*list_it)->getSlot() == req->getSlot()) {
 337             DPRINTF(InOrderDynInst, "[tid:%u]: [sn:%i] Done with request to %s.\n",
 338                     threadNumber, seqNum, req->res->name());
 339             reqList.erase(list_it);
 340             return;
 341         }
 342         list_it++;
 343     }
 344
 345     panic("Releasing Res. Request That Isnt There!\n");
 346 }
 347
 348 /** Records an integer source register being set to a value. */
 349 void
 350 InOrderDynInst::setIntSrc(int idx, uint64_t val)
 351 {
 352     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set to %#x.\n",
 353             threadNumber, seqNum, idx, val);
 354     instSrc[idx].integer = val;
 355 }
 356
 357 /** Records an fp register being set to a value. */
 358 void
 359 InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width)
 360 {
 361     if (width == 32)
 362         instSrc[idx].fp = val;
 363     else if (width == 64)
 364         instSrc[idx].dbl = val;
 365     else
 366         panic("Unsupported width!");
 367 }
 368
 369 /** Records an fp register being set to an integer value. */
 370 void
 371 InOrderDynInst::setFloatRegBitsSrc(int idx, uint64_t val)
 372 {
 373     instSrc[idx].integer = val;
 374 }
 375
 376 /** Reads a integer register. */
 377 IntReg
 378 InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, unsigned tid)
 379 {
 380     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
 381             threadNumber, seqNum, idx, instSrc[idx].integer);
 382     return instSrc[idx].integer;
 383 }
 384
 385 /** Reads a FP register. */
 386 FloatReg
 387 InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width)
 388 {
 389    return instSrc[idx].fp;
 390 }
 391
 392
 393 /** Reads a FP register as a integer. */
 394 FloatRegBits
 395 InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx, int width)
 396 {
 397     return instSrc[idx].integer;
 398 }
 399
 400 /** Reads a miscellaneous register. */
 401 MiscReg
 402 InOrderDynInst::readMiscReg(int misc_reg)
 403 {
 404     return this->cpu->readMiscReg(misc_reg, threadNumber);
 405 }
 406
 407 /** Reads a misc. register, including any side-effects the read
 408  * might have as defined by the architecture.
 409  */
 410 MiscReg
 411 InOrderDynInst::readMiscRegNoEffect(int misc_reg)
 412 {
 413     return this->cpu->readMiscRegNoEffect(misc_reg, threadNumber);
 414 }
 415
 416 /** Reads a miscellaneous register. */
 417 MiscReg
 418 InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
 419 {
 420     int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
 421     return cpu->readMiscRegNoEffect(reg, this->threadNumber);
 422 }
 423
 424 /** Reads a misc. register, including any side-effects the read
 425  * might have as defined by the architecture.
 426  */
 427 MiscReg
 428 InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
 429 {
 430     int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
 431     return this->cpu->readMiscReg(reg, this->threadNumber);
 432 }
 433
 434 /** Sets a misc. register. */
 435 void
 436 InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
 437 {
 438     instResult[si->destRegIdx(idx)].val.integer = val;
 439     instResult[si->destRegIdx(idx)].tick = curTick;
 440
 441     this->cpu->setMiscRegNoEffect(
 442         si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
 443         val, this->threadNumber);
 444 }
 445
 446 /** Sets a misc. register, including any side-effects the write
 447  * might have as defined by the architecture.
 448  */
 449 void
 450 InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
 451                        const MiscReg &val)
 452 {
 453     instResult[si->destRegIdx(idx)].val.integer = val;
 454     instResult[si->destRegIdx(idx)].tick = curTick;
 455
 456     this->cpu->setMiscReg(
 457         si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
 458         val, this->threadNumber);
 459 }
 460
 461 MiscReg
 462 InOrderDynInst::readRegOtherThread(unsigned reg_idx, int tid)
 463 {
 464     if (tid == -1) {
 465         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
 466     }
 467
 468     if (reg_idx < FP_Base_DepTag) {                   // Integer Register File
 469         return this->cpu->readIntReg(reg_idx, tid);
 470     } else if (reg_idx < Ctrl_Base_DepTag) {          // Float Register File
 471         reg_idx -= FP_Base_DepTag;
 472         return this->cpu->readFloatRegBits(reg_idx, tid);
 473     } else {
 474         reg_idx -= Ctrl_Base_DepTag;
 475         return this->cpu->readMiscReg(reg_idx, tid);  // Misc. Register File
 476     }
 477 }
 478
 479 /** Sets a Integer register. */
 480 void
 481 InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
 482 {
 483     instResult[idx].val.integer = val;
 484     instResult[idx].tick = curTick;
 485 }
 486
 487 /** Sets a FP register. */
 488 void
 489 InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, int width)
 490 {
 491     if (width == 32)
 492         instResult[idx].val.fp = val;
 493     else if (width == 64)
 494         instResult[idx].val.dbl = val;
 495     else
 496         panic("Unsupported Floating Point Width!");
 497
 498     instResult[idx].tick = curTick;
 499 }
 500
 501 /** Sets a FP register as a integer. */
 502 void
 503 InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
 504                               FloatRegBits val, int width)
 505 {
 506     instResult[idx].val.integer = val;
 507     instResult[idx].tick = curTick;
 508 }
 509
 510 /** Sets a misc. register. */
 511 /* Alter this when wanting to *speculate* on Miscellaneous registers */
 512 void
 513 InOrderDynInst::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 514 {
 515     this->cpu->setMiscRegNoEffect(misc_reg, val, threadNumber);
 516 }
 517
 518 /** Sets a misc. register, including any side-effects the write
 519  * might have as defined by the architecture.
 520  */
 521 /* Alter this if/when wanting to *speculate* on Miscellaneous registers */
 522 void
 523 InOrderDynInst::setMiscReg(int misc_reg, const MiscReg &val)
 524 {
 525     this->cpu->setMiscReg(misc_reg, val, threadNumber);
 526 }
 527
 528 void
 529 InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val, int tid)
 530 {
 531     if (tid == -1) {
 532         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
 533     }
 534
 535     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
 536         this->cpu->setIntReg(reg_idx, val, tid);
 537     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
 538         reg_idx -= FP_Base_DepTag;
 539         this->cpu->setFloatRegBits(reg_idx, val, tid);
 540     } else {
 541         reg_idx -= Ctrl_Base_DepTag;
 542         this->cpu->setMiscReg(reg_idx, val, tid); // Misc. Register File
 543     }
 544 }
 545
 546 void
 547 InOrderDynInst::deallocateContext(int thread_num)
 548 {
 549     this->cpu->deallocateContext(thread_num);
 550 }
 551
 552 void
 553 InOrderDynInst::enableVirtProcElement(unsigned vpe)
 554 {
 555     this->cpu->enableVirtProcElement(vpe);
 556 }
 557
 558 void
 559 InOrderDynInst::disableVirtProcElement(unsigned vpe)
 560 {
 561     this->cpu->disableVirtProcElement(threadNumber, vpe);
 562 }
 563
 564 void
 565 InOrderDynInst::enableMultiThreading(unsigned vpe)
 566 {
 567     this->cpu->enableMultiThreading(vpe);
 568 }
 569
 570 void
 571 InOrderDynInst::disableMultiThreading(unsigned vpe)
 572 {
 573     this->cpu->disableMultiThreading(threadNumber, vpe);
 574 }
 575
 576 void
 577 InOrderDynInst::setThreadRescheduleCondition(uint32_t cond)
 578 {
 579     this->cpu->setThreadRescheduleCondition(cond);
 580 }
 581
 582 template<class T>
 583 inline Fault
 584 InOrderDynInst::read(Addr addr, T &data, unsigned flags)
 585 {
 586     return cpu->read(this);
 587 }
 588
 589 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 590
 591 template
 592 Fault
 593 InOrderDynInst::read(Addr addr, uint64_t &data, unsigned flags);
 594
 595 template
 596 Fault
 597 InOrderDynInst::read(Addr addr, uint32_t &data, unsigned flags);
 598
 599 template
 600 Fault
 601 InOrderDynInst::read(Addr addr, uint16_t &data, unsigned flags);
 602
 603 template
 604 Fault
 605 InOrderDynInst::read(Addr addr, uint8_t &data, unsigned flags);
 606
 607 #endif //DOXYGEN_SHOULD_SKIP_THIS
 608
 609 template<>
 610 Fault
 611 InOrderDynInst::read(Addr addr, double &data, unsigned flags)
 612 {
 613     return read(addr, *(uint64_t*)&data, flags);
 614 }
 615
 616 template<>
 617 Fault
 618 InOrderDynInst::read(Addr addr, float &data, unsigned flags)
 619 {
 620     return read(addr, *(uint32_t*)&data, flags);
 621 }
 622
 623 template<>
 624 Fault
 625 InOrderDynInst::read(Addr addr, int32_t &data, unsigned flags)
 626 {
 627     return read(addr, (uint32_t&)data, flags);
 628 }
 629
 630 template<class T>
 631 inline Fault
 632 InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
 633 {
 634     //memcpy(memData, gtoh(data), sizeof(T));
 635     storeData  = data;
 636
 637     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting store data to %#x.\n",
 638             threadNumber, seqNum, memData);
 639     return cpu->write(this);
 640 }
 641
 642 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 643 template
 644 Fault
 645 InOrderDynInst::write(uint64_t data, Addr addr,
 646                        unsigned flags, uint64_t *res);
 647
 648 template
 649 Fault
 650 InOrderDynInst::write(uint32_t data, Addr addr,
 651                        unsigned flags, uint64_t *res);
 652
 653 template
 654 Fault
 655 InOrderDynInst::write(uint16_t data, Addr addr,
 656                        unsigned flags, uint64_t *res);
 657
 658 template
 659 Fault
 660 InOrderDynInst::write(uint8_t data, Addr addr,
 661                        unsigned flags, uint64_t *res);
 662
 663 #endif //DOXYGEN_SHOULD_SKIP_THIS
 664
 665 template<>
 666 Fault
 667 InOrderDynInst::write(double data, Addr addr, unsigned flags, uint64_t *res)
 668 {
 669     return write(*(uint64_t*)&data, addr, flags, res);
 670 }
 671
 672 template<>
 673 Fault
 674 InOrderDynInst::write(float data, Addr addr, unsigned flags, uint64_t *res)
 675 {
 676     return write(*(uint32_t*)&data, addr, flags, res);
 677 }
 678
 679
 680 template<>
 681 Fault
 682 InOrderDynInst::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 683 {
 684     return write((uint32_t)data, addr, flags, res);
 685 }
 686
 687
 688 void
 689 InOrderDynInst::dump()
 690 {
 691     cprintf("T%d : %#08d `", threadNumber, PC);
 692     cout << staticInst->disassemble(PC);
 693     cprintf("'\n");
 694 }
 695
 696 void
 697 InOrderDynInst::dump(std::string &outstring)
 698 {
 699     std::ostringstream s;
 700     s << "T" << threadNumber << " : 0x" << PC << " "
 701       << staticInst->disassemble(PC);
 702
 703     outstring = s.str();
 704 }
 705
 706
 707 #define NOHASH
 708 #ifndef NOHASH
 709
 710 #include "base/hashmap.hh"
 711
 712 unsigned int MyHashFunc(const InOrderDynInst *addr)
 713 {
 714     unsigned a = (unsigned)addr;
 715     unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
 716
 717     return hash;
 718 }
 719
 720 typedef m5::hash_map<const InOrderDynInst *, const InOrderDynInst *, MyHashFunc>
 721 my_hash_t;
 722
 723 my_hash_t thishash;
 724 #endif