src/cpu/inorder/inorder_dyn_inst.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <iostream>
  33 #include <set>
  34 #include <sstream>
  35 #include <string>
  36
  37 #include "arch/faults.hh"
  38 #include "base/bigint.hh"
  39 #include "base/cprintf.hh"
  40 #include "base/trace.hh"
  41 #include "config/the_isa.hh"
  42 #include "cpu/inorder/cpu.hh"
  43 #include "cpu/inorder/inorder_dyn_inst.hh"
  44 #include "cpu/exetrace.hh"
  45 #include "debug/InOrderDynInst.hh"
  46 #include "mem/request.hh"
  47
  48 using namespace std;
  49 using namespace TheISA;
  50 using namespace ThePipeline;
  51
  52 InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
  53                                InOrderThreadState *state,
  54                                InstSeqNum seq_num,
  55                                ThreadID tid,
  56                                unsigned _asid)
  57   : seqNum(seq_num), squashSeqNum(0), threadNumber(tid), asid(_asid),
  58     virtProcNumber(0), staticInst(NULL), traceData(NULL), cpu(cpu),
  59     thread(state), fault(NoFault), memData(NULL), loadData(0),
  60     storeData(0), effAddr(0), physEffAddr(0), memReqFlags(0),
  61     readyRegs(0), pc(0), predPC(0), memAddr(0), nextStage(0),
  62     memTime(0), splitMemData(NULL), splitMemReq(NULL), totalSize(0),
  63     split2ndSize(0), split2ndAddr(0), split2ndAccess(false),
  64     split2ndDataPtr(NULL), split2ndFlags(0), splitInst(false),
  65     splitFinishCnt(0), split2ndStoreDataPtr(NULL), splitInstSked(false),
  66     inFrontEnd(true), frontSked(NULL), backSked(NULL),
  67     squashingStage(0), predictTaken(false), procDelaySlotOnMispred(false),
  68     fetchMemReq(NULL), dataMemReq(NULL), instEffAddr(0), eaCalcDone(false),
  69     lqIdx(0), sqIdx(0), instListIt(NULL), onInstList(false)
  70 {
  71     for(int i = 0; i < MaxInstSrcRegs; i++) {
  72         instSrc[i].integer = 0;
  73         instSrc[i].dbl = 0;
  74         _readySrcRegIdx[i] = false;
  75         _srcRegIdx[i] = 0;
  76     }
  77
  78     for(int j = 0; j < MaxInstDestRegs; j++) {
  79       _destRegIdx[j] = 0;
  80       _prevDestRegIdx[j] = 0;
  81     }
  82
  83     ++instcount;
  84     DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created."
  85             " (active insts: %i)\n", threadNumber, seqNum, instcount);
  86
  87 }
  88
  89 int InOrderDynInst::instcount = 0;
  90
  91 void
  92 InOrderDynInst::setMachInst(ExtMachInst machInst)
  93 {
  94     staticInst = StaticInst::decode(machInst, pc.instAddr());
  95
  96     for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
  97         _destRegIdx[i] = this->staticInst->destRegIdx(i);
  98     }
  99
 100     for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 101         _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 102         this->_readySrcRegIdx[i] = 0;
 103     }
 104 }
 105
 106 void
 107 InOrderDynInst::initVars()
 108 {
 109     inFrontEnd = true;
 110
 111     fetchMemReq = NULL;
 112     dataMemReq = NULL;
 113     splitMemData = NULL;
 114     split2ndAddr = 0;
 115     split2ndAccess = false;
 116     splitInst = false;
 117     splitInstSked = false;
 118     splitFinishCnt = 0;
 119
 120     effAddr = 0;
 121     physEffAddr = 0;
 122
 123     readyRegs = 0;
 124
 125     nextStage = 0;
 126
 127     for(int i = 0; i < MaxInstDestRegs; i++)
 128         instResult[i].val.integer = 0;
 129
 130     status.reset();
 131
 132     memAddrReady = false;
 133     eaCalcDone = false;
 134
 135     predictTaken = false;
 136     procDelaySlotOnMispred = false;
 137
 138     lqIdx = -1;
 139     sqIdx = -1;
 140
 141     // Also make this a parameter, or perhaps get it from xc or cpu.
 142     asid = 0;
 143
 144     virtProcNumber = 0;
 145
 146     // Initialize the fault to be NoFault.
 147     fault = NoFault;
 148
 149     // Make sure to have the renamed register entries set to the same
 150     // as the normal register entries.  It will allow the IQ to work
 151     // without any modifications.
 152     if (this->staticInst) {
 153         for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
 154             _destRegIdx[i] = this->staticInst->destRegIdx(i);
 155         }
 156
 157         for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 158             _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 159             this->_readySrcRegIdx[i] = 0;
 160         }
 161     }
 162
 163     // Update Instruction Count for this instruction
 164     if (instcount > 100) {
 165         fatal("Number of Active Instructions in CPU is too high. "
 166                 "(Not Dereferencing Ptrs. Correctly?)\n");
 167     }
 168 }
 169
 170 void
 171 InOrderDynInst::resetInstCount()
 172 {
 173     instcount = 0;
 174 }
 175
 176
 177 InOrderDynInst::~InOrderDynInst()
 178 {
 179     if (fetchMemReq != 0x0) {
 180         delete fetchMemReq;
 181         fetchMemReq = NULL;
 182     }
 183
 184     if (dataMemReq != 0x0) {
 185         delete dataMemReq;
 186         dataMemReq = NULL;
 187     }
 188
 189     if (splitMemReq != 0x0) {
 190         delete dataMemReq;
 191         dataMemReq = NULL;
 192     }
 193
 194     if (traceData)
 195         delete traceData;
 196
 197     if (splitMemData)
 198         delete [] splitMemData;
 199
 200     fault = NoFault;
 201
 202     --instcount;
 203
 204     DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed"
 205             " (active insts: %i)\n", threadNumber, seqNum, instcount);
 206 }
 207
 208 void
 209 InOrderDynInst::setStaticInst(StaticInstPtr &static_inst)
 210 {
 211     this->staticInst = static_inst;
 212
 213     // Make sure to have the renamed register entries set to the same
 214     // as the normal register entries.  It will allow the IQ to work
 215     // without any modifications.
 216     if (this->staticInst) {
 217         for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
 218             _destRegIdx[i] = this->staticInst->destRegIdx(i);
 219         }
 220
 221         for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 222             _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 223             this->_readySrcRegIdx[i] = 0;
 224         }
 225     }
 226 }
 227
 228 Fault
 229 InOrderDynInst::execute()
 230 {
 231     // @todo: Pretty convoluted way to avoid squashing from happening
 232     // when using the TC during an instruction's execution
 233     // (specifically for instructions that have side-effects that use
 234     // the TC).  Fix this.
 235     bool in_syscall = this->thread->inSyscall;
 236     this->thread->inSyscall = true;
 237
 238     this->fault = this->staticInst->execute(this, this->traceData);
 239
 240     this->thread->inSyscall = in_syscall;
 241
 242     return this->fault;
 243 }
 244
 245 Fault
 246 InOrderDynInst::calcEA()
 247 {
 248     this->fault = this->staticInst->eaComp(this, this->traceData);
 249     return this->fault;
 250 }
 251
 252 Fault
 253 InOrderDynInst::initiateAcc()
 254 {
 255     // @todo: Pretty convoluted way to avoid squashing from happening
 256     // when using the TC during an instruction's execution
 257     // (specifically for instructions that have side-effects that use
 258     // the TC).  Fix this.
 259     bool in_syscall = this->thread->inSyscall;
 260     this->thread->inSyscall = true;
 261
 262     this->fault = this->staticInst->initiateAcc(this, this->traceData);
 263
 264     this->thread->inSyscall = in_syscall;
 265
 266     return this->fault;
 267 }
 268
 269
 270 Fault
 271 InOrderDynInst::completeAcc(Packet *pkt)
 272 {
 273     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 274
 275     return this->fault;
 276 }
 277
 278 Fault
 279 InOrderDynInst::memAccess()
 280 {
 281     return initiateAcc();
 282 }
 283
 284
 285 #if FULL_SYSTEM
 286
 287 Fault
 288 InOrderDynInst::hwrei()
 289 {
 290     panic("InOrderDynInst: hwrei: unimplemented\n");
 291     return NoFault;
 292 }
 293
 294
 295 void
 296 InOrderDynInst::trap(Fault fault)
 297 {
 298     this->cpu->trap(fault, this->threadNumber, this);
 299 }
 300
 301
 302 bool
 303 InOrderDynInst::simPalCheck(int palFunc)
 304 {
 305 #if THE_ISA != ALPHA_ISA
 306     panic("simPalCheck called, but PAL only exists in Alpha!\n");
 307 #endif
 308     return this->cpu->simPalCheck(palFunc, this->threadNumber);
 309 }
 310 #else
 311 void
 312 InOrderDynInst::syscall(int64_t callnum)
 313 {
 314     cpu->syscall(callnum, this->threadNumber);
 315 }
 316 #endif
 317
 318 void
 319 InOrderDynInst::setSquashInfo(unsigned stage_num)
 320 {
 321     squashingStage = stage_num;
 322
 323     // If it's a fault, then we need to squash
 324     // the faulting instruction too. Squash
 325     // functions squash above a seqNum, so we
 326     // decrement here for that case
 327     if (fault != NoFault)
 328         squashSeqNum = seqNum - 1;
 329     else
 330         squashSeqNum = seqNum;
 331
 332 #if ISA_HAS_DELAY_SLOT
 333     if (isControl()) {
 334         TheISA::PCState nextPC = pc;
 335         TheISA::advancePC(nextPC, staticInst);
 336
 337         // Check to see if we should squash after the
 338         // branch or after a branch delay slot.
 339         if (pc.nextInstAddr() == pc.instAddr() + sizeof(MachInst))
 340             squashSeqNum = seqNum + 1;
 341         else
 342             squashSeqNum = seqNum;
 343     }
 344 #endif
 345 }
 346
 347 void
 348 InOrderDynInst::releaseReq(ResourceRequest* req)
 349 {
 350     std::list<ResourceRequest*>::iterator list_it = reqList.begin();
 351     std::list<ResourceRequest*>::iterator list_end = reqList.end();
 352
 353     while(list_it != list_end) {
 354         if((*list_it)->getResIdx() == req->getResIdx() &&
 355            (*list_it)->getSlot() == req->getSlot()) {
 356             DPRINTF(InOrderDynInst, "[tid:%u]: [sn:%i] Done with request "
 357                     "to %s.\n", threadNumber, seqNum, req->res->name());
 358             reqList.erase(list_it);
 359             return;
 360         }
 361         list_it++;
 362     }
 363
 364     panic("Releasing Res. Request That Isnt There!\n");
 365 }
 366
 367 /** Records an integer source register being set to a value. */
 368 void
 369 InOrderDynInst::setIntSrc(int idx, uint64_t val)
 370 {
 371     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set "
 372             "to %#x.\n", threadNumber, seqNum, idx, val);
 373     instSrc[idx].integer = val;
 374 }
 375
 376 /** Records an fp register being set to a value. */
 377 void
 378 InOrderDynInst::setFloatSrc(int idx, FloatReg val)
 379 {
 380     instSrc[idx].dbl = val;
 381 }
 382
 383 /** Records an fp register being set to an integer value. */
 384 void
 385 InOrderDynInst::setFloatRegBitsSrc(int idx, uint64_t val)
 386 {
 387     instSrc[idx].integer = val;
 388 }
 389
 390 /** Reads a integer register. */
 391 IntReg
 392 InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
 393 {
 394     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
 395             threadNumber, seqNum, idx, instSrc[idx].integer);
 396     return instSrc[idx].integer;
 397 }
 398
 399 /** Reads a FP register. */
 400 FloatReg
 401 InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
 402 {
 403     return instSrc[idx].dbl;
 404 }
 405
 406
 407 /** Reads a FP register as a integer. */
 408 FloatRegBits
 409 InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx)
 410 {
 411     return instSrc[idx].integer;
 412 }
 413
 414 /** Reads a miscellaneous register. */
 415 MiscReg
 416 InOrderDynInst::readMiscReg(int misc_reg)
 417 {
 418     return this->cpu->readMiscReg(misc_reg, threadNumber);
 419 }
 420
 421
 422 /** Reads a misc. register, including any side-effects the read
 423  * might have as defined by the architecture.
 424  */
 425 MiscReg
 426 InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
 427 {
 428     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
 429             " read as %#x.\n", threadNumber, seqNum, idx,
 430             instSrc[idx].integer);
 431     return instSrc[idx].integer;
 432 }
 433
 434
 435 /** Sets a misc. register, including any side-effects the write
 436  * might have as defined by the architecture.
 437  */
 438 void
 439 InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
 440                        const MiscReg &val)
 441 {
 442     instResult[idx].type = Integer;
 443     instResult[idx].val.integer = val;
 444     instResult[idx].tick = curTick();
 445
 446     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
 447             "being set to %#x.\n", threadNumber, seqNum, idx, val);
 448 }
 449
 450 MiscReg
 451 InOrderDynInst::readRegOtherThread(unsigned reg_idx, ThreadID tid)
 452 {
 453     if (tid == -1) {
 454         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
 455     }
 456
 457     if (reg_idx < FP_Base_DepTag) {                   // Integer Register File
 458         return this->cpu->readIntReg(reg_idx, tid);
 459     } else if (reg_idx < Ctrl_Base_DepTag) {          // Float Register File
 460         reg_idx -= FP_Base_DepTag;
 461         return this->cpu->readFloatRegBits(reg_idx, tid);
 462     } else {
 463         reg_idx -= Ctrl_Base_DepTag;
 464         return this->cpu->readMiscReg(reg_idx, tid);  // Misc. Register File
 465     }
 466 }
 467
 468 /** Sets a Integer register. */
 469 void
 470 InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
 471 {
 472     instResult[idx].type = Integer;
 473     instResult[idx].val.integer = val;
 474     instResult[idx].tick = curTick();
 475
 476     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Int Reg. %i "
 477             "being set to %#x (result-tick:%i).\n",
 478             threadNumber, seqNum, idx, val, instResult[idx].tick);
 479 }
 480
 481 /** Sets a FP register. */
 482 void
 483 InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
 484 {
 485     instResult[idx].val.dbl = val;
 486     instResult[idx].type = Float;
 487     instResult[idx].tick = curTick();
 488
 489     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
 490             "being set to %#x (result-tick:%i).\n",
 491             threadNumber, seqNum, idx, val, instResult[idx].tick);
 492 }
 493
 494 /** Sets a FP register as a integer. */
 495 void
 496 InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
 497                               FloatRegBits val)
 498 {
 499     instResult[idx].type = Integer;
 500     instResult[idx].val.integer = val;
 501     instResult[idx].tick = curTick();
 502
 503     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
 504             "being set to %#x (result-tick:%i).\n",
 505             threadNumber, seqNum, idx, val, instResult[idx].tick);
 506 }
 507
 508 /** Sets a misc. register, including any side-effects the write
 509  * might have as defined by the architecture.
 510  */
 511 /* Alter this if/when wanting to *speculate* on Miscellaneous registers */
 512 void
 513 InOrderDynInst::setMiscReg(int misc_reg, const MiscReg &val)
 514 {
 515     this->cpu->setMiscReg(misc_reg, val, threadNumber);
 516 }
 517
 518 void
 519 InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
 520                                   ThreadID tid)
 521 {
 522     if (tid == InvalidThreadID) {
 523         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
 524     }
 525
 526     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
 527         this->cpu->setIntReg(reg_idx, val, tid);
 528     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
 529         reg_idx -= FP_Base_DepTag;
 530         this->cpu->setFloatRegBits(reg_idx, val, tid);
 531     } else {
 532         reg_idx -= Ctrl_Base_DepTag;
 533         this->cpu->setMiscReg(reg_idx, val, tid); // Misc. Register File
 534     }
 535 }
 536
 537 void
 538 InOrderDynInst::deallocateContext(int thread_num)
 539 {
 540     this->cpu->deallocateContext(thread_num);
 541 }
 542
 543 Fault
 544 InOrderDynInst::readBytes(Addr addr, uint8_t *data,
 545                           unsigned size, unsigned flags)
 546 {
 547     return cpu->read(this, addr, data, size, flags);
 548 }
 549
 550 template<class T>
 551 inline Fault
 552 InOrderDynInst::read(Addr addr, T &data, unsigned flags)
 553 {
 554     if (traceData) {
 555         traceData->setAddr(addr);
 556         traceData->setData(data);
 557     }
 558     Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
 559     DPRINTF(InOrderDynInst, "[sn:%i] (1) Received Bytes %x\n", seqNum, data);
 560     data = TheISA::gtoh(data);
 561     DPRINTF(InOrderDynInst, "[sn%:i] (2) Received Bytes %x\n", seqNum, data);
 562
 563     if (traceData)
 564         traceData->setData(data);
 565     return fault;
 566 }
 567
 568 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 569
 570 template
 571 Fault
 572 InOrderDynInst::read(Addr addr, Twin32_t &data, unsigned flags);
 573
 574 template
 575 Fault
 576 InOrderDynInst::read(Addr addr, Twin64_t &data, unsigned flags);
 577
 578 template
 579 Fault
 580 InOrderDynInst::read(Addr addr, uint64_t &data, unsigned flags);
 581
 582 template
 583 Fault
 584 InOrderDynInst::read(Addr addr, uint32_t &data, unsigned flags);
 585
 586 template
 587 Fault
 588 InOrderDynInst::read(Addr addr, uint16_t &data, unsigned flags);
 589
 590 template
 591 Fault
 592 InOrderDynInst::read(Addr addr, uint8_t &data, unsigned flags);
 593
 594 #endif //DOXYGEN_SHOULD_SKIP_THIS
 595
 596 template<>
 597 Fault
 598 InOrderDynInst::read(Addr addr, double &data, unsigned flags)
 599 {
 600     return read(addr, *(uint64_t*)&data, flags);
 601 }
 602
 603 template<>
 604 Fault
 605 InOrderDynInst::read(Addr addr, float &data, unsigned flags)
 606 {
 607     return read(addr, *(uint32_t*)&data, flags);
 608 }
 609
 610 template<>
 611 Fault
 612 InOrderDynInst::read(Addr addr, int32_t &data, unsigned flags)
 613 {
 614     return read(addr, (uint32_t&)data, flags);
 615 }
 616
 617 Fault
 618 InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
 619                            Addr addr, unsigned flags, uint64_t *res)
 620 {
 621     assert(sizeof(storeData) >= size);
 622     memcpy(&storeData, data, size);
 623     DPRINTF(InOrderDynInst, "(2) [tid:%i]: [sn:%i] Setting store data to %#x.\n",
 624             threadNumber, seqNum, storeData);
 625     return cpu->write(this, (uint8_t *)&storeData, size, addr, flags, res);
 626 }
 627
 628 template<class T>
 629 inline Fault
 630 InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
 631 {
 632     if (traceData) {
 633         traceData->setAddr(addr);
 634         traceData->setData(data);
 635     }
 636     data = TheISA::htog(data);
 637     DPRINTF(InOrderDynInst, "(1) [tid:%i]: [sn:%i] Setting store data to %#x.\n",
 638             threadNumber, seqNum, data);
 639     return writeBytes((uint8_t*)&data, sizeof(T), addr, flags, res);
 640 }
 641
 642 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 643
 644 template
 645 Fault
 646 InOrderDynInst::write(Twin32_t data, Addr addr,
 647                       unsigned flags, uint64_t *res);
 648
 649 template
 650 Fault
 651 InOrderDynInst::write(Twin64_t data, Addr addr,
 652                       unsigned flags, uint64_t *res);
 653 template
 654 Fault
 655 InOrderDynInst::write(uint64_t data, Addr addr,
 656                        unsigned flags, uint64_t *res);
 657
 658 template
 659 Fault
 660 InOrderDynInst::write(uint32_t data, Addr addr,
 661                        unsigned flags, uint64_t *res);
 662
 663 template
 664 Fault
 665 InOrderDynInst::write(uint16_t data, Addr addr,
 666                        unsigned flags, uint64_t *res);
 667
 668 template
 669 Fault
 670 InOrderDynInst::write(uint8_t data, Addr addr,
 671                        unsigned flags, uint64_t *res);
 672
 673 #endif //DOXYGEN_SHOULD_SKIP_THIS
 674
 675 template<>
 676 Fault
 677 InOrderDynInst::write(double data, Addr addr, unsigned flags, uint64_t *res)
 678 {
 679     return write(*(uint64_t*)&data, addr, flags, res);
 680 }
 681
 682 template<>
 683 Fault
 684 InOrderDynInst::write(float data, Addr addr, unsigned flags, uint64_t *res)
 685 {
 686     return write(*(uint32_t*)&data, addr, flags, res);
 687 }
 688
 689
 690 template<>
 691 Fault
 692 InOrderDynInst::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 693 {
 694     return write((uint32_t)data, addr, flags, res);
 695 }
 696
 697
 698 void
 699 InOrderDynInst::dump()
 700 {
 701     cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
 702     cout << staticInst->disassemble(pc.instAddr());
 703     cprintf("'\n");
 704 }
 705
 706 void
 707 InOrderDynInst::dump(std::string &outstring)
 708 {
 709     std::ostringstream s;
 710     s << "T" << threadNumber << " : " << pc << " "
 711       << staticInst->disassemble(pc.instAddr());
 712
 713     outstring = s.str();
 714 }
 715
 716
 717 #define NOHASH
 718 #ifndef NOHASH
 719
 720 #include "base/hashmap.hh"
 721
 722 unsigned int MyHashFunc(const InOrderDynInst *addr)
 723 {
 724     unsigned a = (unsigned)addr;
 725     unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
 726
 727     return hash;
 728 }
 729
 730 typedef m5::hash_map<const InOrderDynInst *, const InOrderDynInst *,
 731                      MyHashFunc>
 732 my_hash_t;
 733
 734 my_hash_t thishash;
 735 #endif