src/cpu/inorder/inorder_dyn_inst.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <iostream>
  33 #include <set>
  34 #include <sstream>
  35 #include <string>
  36
  37 #include "arch/faults.hh"
  38 #include "base/bigint.hh"
  39 #include "base/cprintf.hh"
  40 #include "base/trace.hh"
  41 #include "config/the_isa.hh"
  42 #include "cpu/inorder/cpu.hh"
  43 #include "cpu/inorder/inorder_dyn_inst.hh"
  44 #include "cpu/exetrace.hh"
  45 #include "debug/InOrderDynInst.hh"
  46 #include "mem/request.hh"
  47
  48 using namespace std;
  49 using namespace TheISA;
  50 using namespace ThePipeline;
  51
  52 InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
  53                                InOrderThreadState *state,
  54                                InstSeqNum seq_num,
  55                                ThreadID tid,
  56                                unsigned _asid)
  57   : seqNum(seq_num), squashSeqNum(0), threadNumber(tid), asid(_asid),
  58     virtProcNumber(0), staticInst(NULL), traceData(NULL), cpu(cpu),
  59     thread(state), fault(NoFault), memData(NULL), loadData(0),
  60     storeData(0), effAddr(0), physEffAddr(0), memReqFlags(0),
  61     readyRegs(0), pc(0), predPC(0), memAddr(0), nextStage(0),
  62     memTime(0), splitMemData(NULL), splitMemReq(NULL), totalSize(0),
  63     split2ndSize(0), split2ndAddr(0), split2ndAccess(false),
  64     split2ndDataPtr(NULL), split2ndFlags(0), splitInst(false),
  65     splitFinishCnt(0), split2ndStoreDataPtr(NULL), splitInstSked(false),
  66     inFrontEnd(true), frontSked(NULL), backSked(NULL),
  67     squashingStage(0), predictTaken(false), procDelaySlotOnMispred(false),
  68     fetchMemReq(NULL), dataMemReq(NULL), instEffAddr(0), eaCalcDone(false),
  69     lqIdx(0), sqIdx(0), instListIt(NULL), onInstList(false)
  70 {
  71     for(int i = 0; i < MaxInstSrcRegs; i++) {
  72         instSrc[i].integer = 0;
  73         instSrc[i].dbl = 0;
  74         _readySrcRegIdx[i] = false;
  75         _srcRegIdx[i] = 0;
  76     }
  77
  78     for(int j = 0; j < MaxInstDestRegs; j++) {
  79       _destRegIdx[j] = 0;
  80       _prevDestRegIdx[j] = 0;
  81     }
  82
  83     ++instcount;
  84     DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created."
  85             " (active insts: %i)\n", threadNumber, seqNum, instcount);
  86
  87 }
  88
  89 int InOrderDynInst::instcount = 0;
  90
  91 void
  92 InOrderDynInst::setMachInst(ExtMachInst machInst)
  93 {
  94     staticInst = StaticInst::decode(machInst, pc.instAddr());
  95
  96     for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
  97         _destRegIdx[i] = this->staticInst->destRegIdx(i);
  98     }
  99
 100     for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 101         _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 102         this->_readySrcRegIdx[i] = 0;
 103     }
 104 }
 105
 106 void
 107 InOrderDynInst::initVars()
 108 {
 109     inFrontEnd = true;
 110
 111     fetchMemReq = NULL;
 112     dataMemReq = NULL;
 113     splitMemData = NULL;
 114     split2ndAddr = 0;
 115     split2ndAccess = false;
 116     splitInst = false;
 117     splitInstSked = false;
 118     splitFinishCnt = 0;
 119
 120     effAddr = 0;
 121     physEffAddr = 0;
 122
 123     readyRegs = 0;
 124
 125     nextStage = 0;
 126
 127     for(int i = 0; i < MaxInstDestRegs; i++)
 128         instResult[i].val.integer = 0;
 129
 130     status.reset();
 131
 132     memAddrReady = false;
 133     eaCalcDone = false;
 134
 135     predictTaken = false;
 136     procDelaySlotOnMispred = false;
 137
 138     lqIdx = -1;
 139     sqIdx = -1;
 140
 141     // Also make this a parameter, or perhaps get it from xc or cpu.
 142     asid = 0;
 143
 144     virtProcNumber = 0;
 145
 146     // Initialize the fault to be NoFault.
 147     fault = NoFault;
 148
 149     // Make sure to have the renamed register entries set to the same
 150     // as the normal register entries.  It will allow the IQ to work
 151     // without any modifications.
 152     if (this->staticInst) {
 153         for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
 154             _destRegIdx[i] = this->staticInst->destRegIdx(i);
 155         }
 156
 157         for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 158             _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 159             this->_readySrcRegIdx[i] = 0;
 160         }
 161     }
 162
 163     // Update Instruction Count for this instruction
 164     if (instcount > 100) {
 165         fatal("Number of Active Instructions in CPU is too high. "
 166                 "(Not Dereferencing Ptrs. Correctly?)\n");
 167     }
 168 }
 169
 170 void
 171 InOrderDynInst::resetInstCount()
 172 {
 173     instcount = 0;
 174 }
 175
 176
 177 InOrderDynInst::~InOrderDynInst()
 178 {
 179     if (traceData)
 180         delete traceData;
 181
 182     if (splitMemData)
 183         delete [] splitMemData;
 184
 185     fault = NoFault;
 186
 187     --instcount;
 188
 189     DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed"
 190             " (active insts: %i)\n", threadNumber, seqNum, instcount);
 191 }
 192
 193 void
 194 InOrderDynInst::setStaticInst(StaticInstPtr &static_inst)
 195 {
 196     this->staticInst = static_inst;
 197
 198     // Make sure to have the renamed register entries set to the same
 199     // as the normal register entries.  It will allow the IQ to work
 200     // without any modifications.
 201     if (this->staticInst) {
 202         for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
 203             _destRegIdx[i] = this->staticInst->destRegIdx(i);
 204         }
 205
 206         for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
 207             _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
 208             this->_readySrcRegIdx[i] = 0;
 209         }
 210     }
 211 }
 212
 213 Fault
 214 InOrderDynInst::execute()
 215 {
 216     // @todo: Pretty convoluted way to avoid squashing from happening
 217     // when using the TC during an instruction's execution
 218     // (specifically for instructions that have side-effects that use
 219     // the TC).  Fix this.
 220     bool in_syscall = this->thread->inSyscall;
 221     this->thread->inSyscall = true;
 222
 223     this->fault = this->staticInst->execute(this, this->traceData);
 224
 225     this->thread->inSyscall = in_syscall;
 226
 227     return this->fault;
 228 }
 229
 230 Fault
 231 InOrderDynInst::calcEA()
 232 {
 233     this->fault = this->staticInst->eaComp(this, this->traceData);
 234     return this->fault;
 235 }
 236
 237 Fault
 238 InOrderDynInst::initiateAcc()
 239 {
 240     // @todo: Pretty convoluted way to avoid squashing from happening
 241     // when using the TC during an instruction's execution
 242     // (specifically for instructions that have side-effects that use
 243     // the TC).  Fix this.
 244     bool in_syscall = this->thread->inSyscall;
 245     this->thread->inSyscall = true;
 246
 247     this->fault = this->staticInst->initiateAcc(this, this->traceData);
 248
 249     this->thread->inSyscall = in_syscall;
 250
 251     return this->fault;
 252 }
 253
 254
 255 Fault
 256 InOrderDynInst::completeAcc(Packet *pkt)
 257 {
 258     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 259
 260     return this->fault;
 261 }
 262
 263 Fault
 264 InOrderDynInst::memAccess()
 265 {
 266     return initiateAcc();
 267 }
 268
 269
 270 #if FULL_SYSTEM
 271
 272 Fault
 273 InOrderDynInst::hwrei()
 274 {
 275     panic("InOrderDynInst: hwrei: unimplemented\n");
 276     return NoFault;
 277 }
 278
 279
 280 void
 281 InOrderDynInst::trap(Fault fault)
 282 {
 283     this->cpu->trap(fault, this->threadNumber, this);
 284 }
 285
 286
 287 bool
 288 InOrderDynInst::simPalCheck(int palFunc)
 289 {
 290 #if THE_ISA != ALPHA_ISA
 291     panic("simPalCheck called, but PAL only exists in Alpha!\n");
 292 #endif
 293     return this->cpu->simPalCheck(palFunc, this->threadNumber);
 294 }
 295 #else
 296 void
 297 InOrderDynInst::syscall(int64_t callnum)
 298 {
 299     cpu->syscall(callnum, this->threadNumber);
 300 }
 301 #endif
 302
 303 void
 304 InOrderDynInst::setSquashInfo(unsigned stage_num)
 305 {
 306     squashingStage = stage_num;
 307
 308     // If it's a fault, then we need to squash
 309     // the faulting instruction too. Squash
 310     // functions squash above a seqNum, so we
 311     // decrement here for that case
 312     if (fault != NoFault) {
 313         squashSeqNum = seqNum - 1;
 314         return;
 315     } else
 316         squashSeqNum = seqNum;
 317
 318 #if ISA_HAS_DELAY_SLOT
 319     if (isControl()) {
 320         TheISA::PCState nextPC = pc;
 321         TheISA::advancePC(nextPC, staticInst);
 322
 323         // Check to see if we should squash after the
 324         // branch or after a branch delay slot.
 325         if (pc.nextInstAddr() == pc.instAddr() + sizeof(MachInst))
 326             squashSeqNum = seqNum + 1;
 327         else
 328             squashSeqNum = seqNum;
 329     }
 330 #endif
 331 }
 332
 333 void
 334 InOrderDynInst::releaseReq(ResourceRequest* req)
 335 {
 336     std::list<ResourceRequest*>::iterator list_it = reqList.begin();
 337     std::list<ResourceRequest*>::iterator list_end = reqList.end();
 338
 339     while(list_it != list_end) {
 340         if((*list_it)->getResIdx() == req->getResIdx() &&
 341            (*list_it)->getSlot() == req->getSlot()) {
 342             DPRINTF(InOrderDynInst, "[tid:%u]: [sn:%i] Done with request "
 343                     "to %s.\n", threadNumber, seqNum, req->res->name());
 344             reqList.erase(list_it);
 345             return;
 346         }
 347         list_it++;
 348     }
 349
 350     panic("Releasing Res. Request That Isnt There!\n");
 351 }
 352
 353 /** Records an integer source register being set to a value. */
 354 void
 355 InOrderDynInst::setIntSrc(int idx, uint64_t val)
 356 {
 357     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set "
 358             "to %#x.\n", threadNumber, seqNum, idx, val);
 359     instSrc[idx].integer = val;
 360 }
 361
 362 /** Records an fp register being set to a value. */
 363 void
 364 InOrderDynInst::setFloatSrc(int idx, FloatReg val)
 365 {
 366     instSrc[idx].dbl = val;
 367 }
 368
 369 /** Records an fp register being set to an integer value. */
 370 void
 371 InOrderDynInst::setFloatRegBitsSrc(int idx, uint64_t val)
 372 {
 373     instSrc[idx].integer = val;
 374 }
 375
 376 /** Reads a integer register. */
 377 IntReg
 378 InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
 379 {
 380     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
 381             threadNumber, seqNum, idx, instSrc[idx].integer);
 382     return instSrc[idx].integer;
 383 }
 384
 385 /** Reads a FP register. */
 386 FloatReg
 387 InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
 388 {
 389     return instSrc[idx].dbl;
 390 }
 391
 392
 393 /** Reads a FP register as a integer. */
 394 FloatRegBits
 395 InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx)
 396 {
 397     return instSrc[idx].integer;
 398 }
 399
 400 /** Reads a miscellaneous register. */
 401 MiscReg
 402 InOrderDynInst::readMiscReg(int misc_reg)
 403 {
 404     return this->cpu->readMiscReg(misc_reg, threadNumber);
 405 }
 406
 407
 408 /** Reads a misc. register, including any side-effects the read
 409  * might have as defined by the architecture.
 410  */
 411 MiscReg
 412 InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
 413 {
 414     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
 415             " read as %#x.\n", threadNumber, seqNum, idx,
 416             instSrc[idx].integer);
 417     return instSrc[idx].integer;
 418 }
 419
 420
 421 /** Sets a misc. register, including any side-effects the write
 422  * might have as defined by the architecture.
 423  */
 424 void
 425 InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
 426                        const MiscReg &val)
 427 {
 428     instResult[idx].type = Integer;
 429     instResult[idx].val.integer = val;
 430     instResult[idx].tick = curTick();
 431
 432     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
 433             "being set to %#x.\n", threadNumber, seqNum, idx, val);
 434 }
 435
 436 MiscReg
 437 InOrderDynInst::readRegOtherThread(unsigned reg_idx, ThreadID tid)
 438 {
 439     if (tid == -1) {
 440         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
 441     }
 442
 443     if (reg_idx < FP_Base_DepTag) {                   // Integer Register File
 444         return this->cpu->readIntReg(reg_idx, tid);
 445     } else if (reg_idx < Ctrl_Base_DepTag) {          // Float Register File
 446         reg_idx -= FP_Base_DepTag;
 447         return this->cpu->readFloatRegBits(reg_idx, tid);
 448     } else {
 449         reg_idx -= Ctrl_Base_DepTag;
 450         return this->cpu->readMiscReg(reg_idx, tid);  // Misc. Register File
 451     }
 452 }
 453
 454 /** Sets a Integer register. */
 455 void
 456 InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
 457 {
 458     instResult[idx].type = Integer;
 459     instResult[idx].val.integer = val;
 460     instResult[idx].tick = curTick();
 461
 462     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Int Reg. %i "
 463             "being set to %#x (result-tick:%i).\n",
 464             threadNumber, seqNum, idx, val, instResult[idx].tick);
 465 }
 466
 467 /** Sets a FP register. */
 468 void
 469 InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
 470 {
 471     instResult[idx].val.dbl = val;
 472     instResult[idx].type = Float;
 473     instResult[idx].tick = curTick();
 474
 475     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
 476             "being set to %#x (result-tick:%i).\n",
 477             threadNumber, seqNum, idx, val, instResult[idx].tick);
 478 }
 479
 480 /** Sets a FP register as a integer. */
 481 void
 482 InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
 483                               FloatRegBits val)
 484 {
 485     instResult[idx].type = Integer;
 486     instResult[idx].val.integer = val;
 487     instResult[idx].tick = curTick();
 488
 489     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
 490             "being set to %#x (result-tick:%i).\n",
 491             threadNumber, seqNum, idx, val, instResult[idx].tick);
 492 }
 493
 494 /** Sets a misc. register, including any side-effects the write
 495  * might have as defined by the architecture.
 496  */
 497 /* Alter this if/when wanting to *speculate* on Miscellaneous registers */
 498 void
 499 InOrderDynInst::setMiscReg(int misc_reg, const MiscReg &val)
 500 {
 501     this->cpu->setMiscReg(misc_reg, val, threadNumber);
 502 }
 503
 504 void
 505 InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
 506                                   ThreadID tid)
 507 {
 508     if (tid == InvalidThreadID) {
 509         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
 510     }
 511
 512     if (reg_idx < FP_Base_DepTag) {            // Integer Register File
 513         this->cpu->setIntReg(reg_idx, val, tid);
 514     } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
 515         reg_idx -= FP_Base_DepTag;
 516         this->cpu->setFloatRegBits(reg_idx, val, tid);
 517     } else {
 518         reg_idx -= Ctrl_Base_DepTag;
 519         this->cpu->setMiscReg(reg_idx, val, tid); // Misc. Register File
 520     }
 521 }
 522
 523 void
 524 InOrderDynInst::deallocateContext(int thread_num)
 525 {
 526     this->cpu->deallocateContext(thread_num);
 527 }
 528
 529 Fault
 530 InOrderDynInst::readBytes(Addr addr, uint8_t *data,
 531                           unsigned size, unsigned flags)
 532 {
 533     return cpu->read(this, addr, data, size, flags);
 534 }
 535
 536 template<class T>
 537 inline Fault
 538 InOrderDynInst::read(Addr addr, T &data, unsigned flags)
 539 {
 540     if (traceData) {
 541         traceData->setAddr(addr);
 542         traceData->setData(data);
 543     }
 544     Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
 545     //@todo: the below lines should be unnecessary, timing access
 546     // wont have valid data right here
 547     DPRINTF(InOrderDynInst, "[sn:%i] (1) Received Bytes %x\n", seqNum, data);
 548     data = TheISA::gtoh(data);
 549     DPRINTF(InOrderDynInst, "[sn%:i] (2) Received Bytes %x\n", seqNum, data);
 550
 551     if (traceData)
 552         traceData->setData(data);
 553     return fault;
 554 }
 555
 556 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 557
 558 template
 559 Fault
 560 InOrderDynInst::read(Addr addr, Twin32_t &data, unsigned flags);
 561
 562 template
 563 Fault
 564 InOrderDynInst::read(Addr addr, Twin64_t &data, unsigned flags);
 565
 566 template
 567 Fault
 568 InOrderDynInst::read(Addr addr, uint64_t &data, unsigned flags);
 569
 570 template
 571 Fault
 572 InOrderDynInst::read(Addr addr, uint32_t &data, unsigned flags);
 573
 574 template
 575 Fault
 576 InOrderDynInst::read(Addr addr, uint16_t &data, unsigned flags);
 577
 578 template
 579 Fault
 580 InOrderDynInst::read(Addr addr, uint8_t &data, unsigned flags);
 581
 582 #endif //DOXYGEN_SHOULD_SKIP_THIS
 583
 584 template<>
 585 Fault
 586 InOrderDynInst::read(Addr addr, double &data, unsigned flags)
 587 {
 588     return read(addr, *(uint64_t*)&data, flags);
 589 }
 590
 591 template<>
 592 Fault
 593 InOrderDynInst::read(Addr addr, float &data, unsigned flags)
 594 {
 595     return read(addr, *(uint32_t*)&data, flags);
 596 }
 597
 598 template<>
 599 Fault
 600 InOrderDynInst::read(Addr addr, int32_t &data, unsigned flags)
 601 {
 602     return read(addr, (uint32_t&)data, flags);
 603 }
 604
 605 Fault
 606 InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
 607                            Addr addr, unsigned flags, uint64_t *res)
 608 {
 609     return cpu->write(this, data, size, addr, flags, res);
 610 }
 611
 612 template<class T>
 613 inline Fault
 614 InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
 615 {
 616     if (traceData) {
 617         traceData->setAddr(addr);
 618         traceData->setData(data);
 619     }
 620     data = TheISA::htog(data);
 621     return writeBytes((uint8_t*)&data, sizeof(T), addr, flags, res);
 622 }
 623
 624 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 625
 626 template
 627 Fault
 628 InOrderDynInst::write(Twin32_t data, Addr addr,
 629                       unsigned flags, uint64_t *res);
 630
 631 template
 632 Fault
 633 InOrderDynInst::write(Twin64_t data, Addr addr,
 634                       unsigned flags, uint64_t *res);
 635 template
 636 Fault
 637 InOrderDynInst::write(uint64_t data, Addr addr,
 638                        unsigned flags, uint64_t *res);
 639
 640 template
 641 Fault
 642 InOrderDynInst::write(uint32_t data, Addr addr,
 643                        unsigned flags, uint64_t *res);
 644
 645 template
 646 Fault
 647 InOrderDynInst::write(uint16_t data, Addr addr,
 648                        unsigned flags, uint64_t *res);
 649
 650 template
 651 Fault
 652 InOrderDynInst::write(uint8_t data, Addr addr,
 653                        unsigned flags, uint64_t *res);
 654
 655 #endif //DOXYGEN_SHOULD_SKIP_THIS
 656
 657 template<>
 658 Fault
 659 InOrderDynInst::write(double data, Addr addr, unsigned flags, uint64_t *res)
 660 {
 661     return write(*(uint64_t*)&data, addr, flags, res);
 662 }
 663
 664 template<>
 665 Fault
 666 InOrderDynInst::write(float data, Addr addr, unsigned flags, uint64_t *res)
 667 {
 668     return write(*(uint32_t*)&data, addr, flags, res);
 669 }
 670
 671
 672 template<>
 673 Fault
 674 InOrderDynInst::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 675 {
 676     return write((uint32_t)data, addr, flags, res);
 677 }
 678
 679
 680 void
 681 InOrderDynInst::dump()
 682 {
 683     cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
 684     cout << staticInst->disassemble(pc.instAddr());
 685     cprintf("'\n");
 686 }
 687
 688 void
 689 InOrderDynInst::dump(std::string &outstring)
 690 {
 691     std::ostringstream s;
 692     s << "T" << threadNumber << " : " << pc << " "
 693       << staticInst->disassemble(pc.instAddr());
 694
 695     outstring = s.str();
 696 }
 697
 698
 699 #define NOHASH
 700 #ifndef NOHASH
 701
 702 #include "base/hashmap.hh"
 703
 704 unsigned int MyHashFunc(const InOrderDynInst *addr)
 705 {
 706     unsigned a = (unsigned)addr;
 707     unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
 708
 709     return hash;
 710 }
 711
 712 typedef m5::hash_map<const InOrderDynInst *, const InOrderDynInst *,
 713                      MyHashFunc>
 714 my_hash_t;
 715
 716 my_hash_t thishash;
 717 #endif