2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
37 #include "arch/faults.hh"
38 #include "base/cprintf.hh"
39 #include "base/trace.hh"
40 #include "config/the_isa.hh"
41 #include "cpu/exetrace.hh"
42 #include "cpu/inorder/cpu.hh"
43 #include "cpu/inorder/inorder_dyn_inst.hh"
44 #include "mem/request.hh"
47 using namespace TheISA
;
48 using namespace ThePipeline
;
50 InOrderDynInst::InOrderDynInst(TheISA::ExtMachInst machInst
, Addr inst_PC
,
51 Addr pred_PC
, InstSeqNum seq_num
,
53 : staticInst(machInst
, inst_PC
), traceData(NULL
), cpu(cpu
)
58 nextPC
= PC
+ sizeof(MachInst
);
59 nextNPC
= nextPC
+ sizeof(MachInst
);
65 InOrderDynInst::InOrderDynInst(InOrderCPU
*cpu
,
66 InOrderThreadState
*state
,
70 : traceData(NULL
), cpu(cpu
)
79 InOrderDynInst::InOrderDynInst(StaticInstPtr
&_staticInst
)
80 : seqNum(0), staticInst(_staticInst
), traceData(NULL
)
85 InOrderDynInst::InOrderDynInst()
86 : seqNum(0), traceData(NULL
), cpu(cpu
)
91 int InOrderDynInst::instcount
= 0;
95 InOrderDynInst::setMachInst(ExtMachInst machInst
)
97 staticInst
= StaticInst::decode(machInst
, PC
);
99 for (int i
= 0; i
< this->staticInst
->numDestRegs(); i
++) {
100 _destRegIdx
[i
] = this->staticInst
->destRegIdx(i
);
103 for (int i
= 0; i
< this->staticInst
->numSrcRegs(); i
++) {
104 _srcRegIdx
[i
] = this->staticInst
->srcRegIdx(i
);
105 this->_readySrcRegIdx
[i
] = 0;
110 InOrderDynInst::initVars()
121 nextInstStageNum
= 0;
123 for(int i
= 0; i
< MaxInstDestRegs
; i
++)
124 instResult
[i
].val
.integer
= 0;
128 memAddrReady
= false;
132 predictTaken
= false;
133 procDelaySlotOnMispred
= false;
138 // Also make this a parameter, or perhaps get it from xc or cpu.
143 // Initialize the fault to be NoFault.
146 // Make sure to have the renamed register entries set to the same
147 // as the normal register entries. It will allow the IQ to work
148 // without any modifications.
149 if (this->staticInst
) {
150 for (int i
= 0; i
< this->staticInst
->numDestRegs(); i
++) {
151 _destRegIdx
[i
] = this->staticInst
->destRegIdx(i
);
154 for (int i
= 0; i
< this->staticInst
->numSrcRegs(); i
++) {
155 _srcRegIdx
[i
] = this->staticInst
->srcRegIdx(i
);
156 this->_readySrcRegIdx
[i
] = 0;
160 // Update Instruction Count for this instruction
162 if (instcount
> 500) {
163 fatal("Number of Active Instructions in CPU is too high. "
164 "(Not Dereferencing Ptrs. Correctly?)\n");
169 DPRINTF(InOrderDynInst
, "DynInst: [tid:%i] [sn:%lli] Instruction created. (active insts: %i)\n",
170 threadNumber
, seqNum
, instcount
);
174 InOrderDynInst::~InOrderDynInst()
176 if (fetchMemReq
!= 0x0) {
181 if (dataMemReq
!= 0x0) {
196 DPRINTF(InOrderDynInst
, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed. (active insts: %i)\n",
197 threadNumber
, seqNum
, instcount
);
201 InOrderDynInst::setStaticInst(StaticInstPtr
&static_inst
)
203 this->staticInst
= static_inst
;
205 // Make sure to have the renamed register entries set to the same
206 // as the normal register entries. It will allow the IQ to work
207 // without any modifications.
208 if (this->staticInst
) {
209 for (int i
= 0; i
< this->staticInst
->numDestRegs(); i
++) {
210 _destRegIdx
[i
] = this->staticInst
->destRegIdx(i
);
213 for (int i
= 0; i
< this->staticInst
->numSrcRegs(); i
++) {
214 _srcRegIdx
[i
] = this->staticInst
->srcRegIdx(i
);
215 this->_readySrcRegIdx
[i
] = 0;
221 InOrderDynInst::execute()
223 // @todo: Pretty convoluted way to avoid squashing from happening
224 // when using the TC during an instruction's execution
225 // (specifically for instructions that have side-effects that use
226 // the TC). Fix this.
227 bool in_syscall
= this->thread
->inSyscall
;
228 this->thread
->inSyscall
= true;
230 this->fault
= this->staticInst
->execute(this, this->traceData
);
232 this->thread
->inSyscall
= in_syscall
;
238 InOrderDynInst::calcEA()
240 this->fault
= this->staticInst
->eaComp(this, this->traceData
);
245 InOrderDynInst::initiateAcc()
247 // @todo: Pretty convoluted way to avoid squashing from happening
248 // when using the TC during an instruction's execution
249 // (specifically for instructions that have side-effects that use
250 // the TC). Fix this.
251 bool in_syscall
= this->thread
->inSyscall
;
252 this->thread
->inSyscall
= true;
254 this->fault
= this->staticInst
->initiateAcc(this, this->traceData
);
256 this->thread
->inSyscall
= in_syscall
;
263 InOrderDynInst::completeAcc(Packet
*pkt
)
265 this->fault
= this->staticInst
->completeAcc(pkt
, this, this->traceData
);
270 InstStage
*InOrderDynInst::addStage()
272 this->currentInstStage
= new InstStage(this, nextInstStageNum
++);
273 instStageList
.push_back( this->currentInstStage
);
274 return this->currentInstStage
;
277 InstStage
*InOrderDynInst::addStage(int stage_num
)
279 nextInstStageNum
= stage_num
;
280 return InOrderDynInst::addStage();
283 void InOrderDynInst::deleteStages() {
284 std::list
<InstStage
*>::iterator list_it
= instStageList
.begin();
285 std::list
<InstStage
*>::iterator list_end
= instStageList
.end();
287 while(list_it
!= list_end
) {
294 InOrderDynInst::memAccess()
296 return initiateAcc();
303 InOrderDynInst::hwrei()
305 panic("InOrderDynInst: hwrei: unimplemented\n");
311 InOrderDynInst::trap(Fault fault
)
313 this->cpu
->trap(fault
, this->threadNumber
);
318 InOrderDynInst::simPalCheck(int palFunc
)
320 #if THE_ISA != ALPHA_ISA
321 panic("simPalCheck called, but PAL only exists in Alpha!\n");
323 return this->cpu
->simPalCheck(palFunc
, this->threadNumber
);
327 InOrderDynInst::syscall(int64_t callnum
)
329 cpu
->syscall(callnum
, this->threadNumber
);
334 InOrderDynInst::prefetch(Addr addr
, unsigned flags
)
340 InOrderDynInst::writeHint(Addr addr
, int size
, unsigned flags
)
342 cpu
->writeHint(this);
346 * @todo Need to find a way to get the cache block size here.
349 InOrderDynInst::copySrcTranslate(Addr src
)
351 // Not currently supported.
356 * @todo Need to find a way to get the cache block size here.
359 InOrderDynInst::copy(Addr dest
)
361 // Not currently supported.
366 InOrderDynInst::releaseReq(ResourceRequest
* req
)
368 std::list
<ResourceRequest
*>::iterator list_it
= reqList
.begin();
369 std::list
<ResourceRequest
*>::iterator list_end
= reqList
.end();
371 while(list_it
!= list_end
) {
372 if((*list_it
)->getResIdx() == req
->getResIdx() &&
373 (*list_it
)->getSlot() == req
->getSlot()) {
374 DPRINTF(InOrderDynInst
, "[tid:%u]: [sn:%i] Done with request to %s.\n",
375 threadNumber
, seqNum
, req
->res
->name());
376 reqList
.erase(list_it
);
382 panic("Releasing Res. Request That Isnt There!\n");
385 /** Records an integer source register being set to a value. */
387 InOrderDynInst::setIntSrc(int idx
, uint64_t val
)
389 DPRINTF(InOrderDynInst
, "[tid:%i]: [sn:%i] Source Value %i being set to %#x.\n",
390 threadNumber
, seqNum
, idx
, val
);
391 instSrc
[idx
].integer
= val
;
394 /** Records an fp register being set to a value. */
396 InOrderDynInst::setFloatSrc(int idx
, FloatReg val
)
398 instSrc
[idx
].dbl
= val
;
401 /** Records an fp register being set to an integer value. */
403 InOrderDynInst::setFloatRegBitsSrc(int idx
, uint64_t val
)
405 instSrc
[idx
].integer
= val
;
408 /** Reads a integer register. */
410 InOrderDynInst::readIntRegOperand(const StaticInst
*si
, int idx
, ThreadID tid
)
412 DPRINTF(InOrderDynInst
, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
413 threadNumber
, seqNum
, idx
, instSrc
[idx
].integer
);
414 return instSrc
[idx
].integer
;
417 /** Reads a FP register. */
419 InOrderDynInst::readFloatRegOperand(const StaticInst
*si
, int idx
)
421 return instSrc
[idx
].dbl
;
425 /** Reads a FP register as a integer. */
427 InOrderDynInst::readFloatRegOperandBits(const StaticInst
*si
, int idx
)
429 return instSrc
[idx
].integer
;
432 /** Reads a miscellaneous register. */
434 InOrderDynInst::readMiscReg(int misc_reg
)
436 return this->cpu
->readMiscReg(misc_reg
, threadNumber
);
439 /** Reads a misc. register, including any side-effects the read
440 * might have as defined by the architecture.
443 InOrderDynInst::readMiscRegNoEffect(int misc_reg
)
445 return this->cpu
->readMiscRegNoEffect(misc_reg
, threadNumber
);
448 /** Reads a miscellaneous register. */
450 InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst
*si
, int idx
)
452 DPRINTF(InOrderDynInst
, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
453 " read as %#x.\n", threadNumber
, seqNum
, idx
,
454 instSrc
[idx
].integer
);
455 return instSrc
[idx
].integer
;
458 /** Reads a misc. register, including any side-effects the read
459 * might have as defined by the architecture.
462 InOrderDynInst::readMiscRegOperand(const StaticInst
*si
, int idx
)
464 // For In-Order, the side-effect of reading a register happens
465 // when explicitly executing a "ReadSrc" command. This simply returns
467 return readMiscRegOperandNoEffect(si
, idx
);
470 /** Sets a misc. register. */
472 InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst
* si
, int idx
,
475 instResult
[idx
].type
= Integer
;
476 instResult
[idx
].val
.integer
= val
;
477 instResult
[idx
].tick
= curTick
;
479 DPRINTF(InOrderDynInst
, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
480 "being set to %#x.\n", threadNumber
, seqNum
, idx
, val
);
483 /** Sets a misc. register, including any side-effects the write
484 * might have as defined by the architecture.
487 InOrderDynInst::setMiscRegOperand(const StaticInst
*si
, int idx
,
490 // For In-Order, the side-effect of setting a register happens
491 // when explicitly writing back the register value. This
492 // simply maintains the operand value.
493 setMiscRegOperandNoEffect(si
, idx
, val
);
497 InOrderDynInst::readRegOtherThread(unsigned reg_idx
, ThreadID tid
)
500 tid
= TheISA::getTargetThread(this->cpu
->tcBase(threadNumber
));
503 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
504 return this->cpu
->readIntReg(reg_idx
, tid
);
505 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
506 reg_idx
-= FP_Base_DepTag
;
507 return this->cpu
->readFloatRegBits(reg_idx
, tid
);
509 reg_idx
-= Ctrl_Base_DepTag
;
510 return this->cpu
->readMiscReg(reg_idx
, tid
); // Misc. Register File
514 /** Sets a Integer register. */
516 InOrderDynInst::setIntRegOperand(const StaticInst
*si
, int idx
, IntReg val
)
518 instResult
[idx
].type
= Integer
;
519 instResult
[idx
].val
.integer
= val
;
520 instResult
[idx
].tick
= curTick
;
523 /** Sets a FP register. */
525 InOrderDynInst::setFloatRegOperand(const StaticInst
*si
, int idx
, FloatReg val
)
527 instResult
[idx
].val
.dbl
= val
;
528 instResult
[idx
].type
= Float
;
530 instResult
[idx
].tick
= curTick
;
533 /** Sets a FP register as a integer. */
535 InOrderDynInst::setFloatRegOperandBits(const StaticInst
*si
, int idx
,
538 instResult
[idx
].type
= Integer
;
539 instResult
[idx
].val
.integer
= val
;
540 instResult
[idx
].tick
= curTick
;
543 /** Sets a misc. register. */
544 /* Alter this when wanting to *speculate* on Miscellaneous registers */
546 InOrderDynInst::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
548 this->cpu
->setMiscRegNoEffect(misc_reg
, val
, threadNumber
);
551 /** Sets a misc. register, including any side-effects the write
552 * might have as defined by the architecture.
554 /* Alter this if/when wanting to *speculate* on Miscellaneous registers */
556 InOrderDynInst::setMiscReg(int misc_reg
, const MiscReg
&val
)
558 this->cpu
->setMiscReg(misc_reg
, val
, threadNumber
);
562 InOrderDynInst::setRegOtherThread(unsigned reg_idx
, const MiscReg
&val
,
565 if (tid
== InvalidThreadID
) {
566 tid
= TheISA::getTargetThread(this->cpu
->tcBase(threadNumber
));
569 if (reg_idx
< FP_Base_DepTag
) { // Integer Register File
570 this->cpu
->setIntReg(reg_idx
, val
, tid
);
571 } else if (reg_idx
< Ctrl_Base_DepTag
) { // Float Register File
572 reg_idx
-= FP_Base_DepTag
;
573 this->cpu
->setFloatRegBits(reg_idx
, val
, tid
);
575 reg_idx
-= Ctrl_Base_DepTag
;
576 this->cpu
->setMiscReg(reg_idx
, val
, tid
); // Misc. Register File
581 InOrderDynInst::deallocateContext(int thread_num
)
583 this->cpu
->deallocateContext(thread_num
);
587 InOrderDynInst::enableVirtProcElement(unsigned vpe
)
589 this->cpu
->enableVirtProcElement(vpe
);
593 InOrderDynInst::disableVirtProcElement(unsigned vpe
)
595 this->cpu
->disableVirtProcElement(threadNumber
, vpe
);
599 InOrderDynInst::enableMultiThreading(unsigned vpe
)
601 this->cpu
->enableMultiThreading(vpe
);
605 InOrderDynInst::disableMultiThreading(unsigned vpe
)
607 this->cpu
->disableMultiThreading(threadNumber
, vpe
);
612 InOrderDynInst::read(Addr addr
, T
&data
, unsigned flags
)
614 return cpu
->read(this, addr
, data
, flags
);
617 #ifndef DOXYGEN_SHOULD_SKIP_THIS
621 InOrderDynInst::read(Addr addr
, uint64_t &data
, unsigned flags
);
625 InOrderDynInst::read(Addr addr
, uint32_t &data
, unsigned flags
);
629 InOrderDynInst::read(Addr addr
, uint16_t &data
, unsigned flags
);
633 InOrderDynInst::read(Addr addr
, uint8_t &data
, unsigned flags
);
635 #endif //DOXYGEN_SHOULD_SKIP_THIS
639 InOrderDynInst::read(Addr addr
, double &data
, unsigned flags
)
641 return read(addr
, *(uint64_t*)&data
, flags
);
646 InOrderDynInst::read(Addr addr
, float &data
, unsigned flags
)
648 return read(addr
, *(uint32_t*)&data
, flags
);
653 InOrderDynInst::read(Addr addr
, int32_t &data
, unsigned flags
)
655 return read(addr
, (uint32_t&)data
, flags
);
660 InOrderDynInst::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
662 //memcpy(memData, gtoh(data), sizeof(T));
665 DPRINTF(InOrderDynInst
, "[tid:%i]: [sn:%i] Setting store data to %#x.\n",
666 threadNumber
, seqNum
, memData
);
667 return cpu
->write(this, data
, addr
, flags
, res
);
670 #ifndef DOXYGEN_SHOULD_SKIP_THIS
673 InOrderDynInst::write(uint64_t data
, Addr addr
,
674 unsigned flags
, uint64_t *res
);
678 InOrderDynInst::write(uint32_t data
, Addr addr
,
679 unsigned flags
, uint64_t *res
);
683 InOrderDynInst::write(uint16_t data
, Addr addr
,
684 unsigned flags
, uint64_t *res
);
688 InOrderDynInst::write(uint8_t data
, Addr addr
,
689 unsigned flags
, uint64_t *res
);
691 #endif //DOXYGEN_SHOULD_SKIP_THIS
695 InOrderDynInst::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
697 return write(*(uint64_t*)&data
, addr
, flags
, res
);
702 InOrderDynInst::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
704 return write(*(uint32_t*)&data
, addr
, flags
, res
);
710 InOrderDynInst::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
712 return write((uint32_t)data
, addr
, flags
, res
);
717 InOrderDynInst::dump()
719 cprintf("T%d : %#08d `", threadNumber
, PC
);
720 cout
<< staticInst
->disassemble(PC
);
725 InOrderDynInst::dump(std::string
&outstring
)
727 std::ostringstream s
;
728 s
<< "T" << threadNumber
<< " : 0x" << PC
<< " "
729 << staticInst
->disassemble(PC
);
738 #include "base/hashmap.hh"
740 unsigned int MyHashFunc(const InOrderDynInst
*addr
)
742 unsigned a
= (unsigned)addr
;
743 unsigned hash
= (((a
>> 14) ^ ((a
>> 2) & 0xffff))) & 0x7FFFFFFF;
748 typedef m5::hash_map
<const InOrderDynInst
*, const InOrderDynInst
*, MyHashFunc
>