inorder: add flatDestReg member to dyninst
[gem5.git] / src / cpu / inorder / inorder_dyn_inst.cc
1 /*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 *
30 */
31
32 #include <iostream>
33 #include <set>
34 #include <sstream>
35 #include <string>
36
37 #include "arch/faults.hh"
38 #include "base/bigint.hh"
39 #include "base/cprintf.hh"
40 #include "base/trace.hh"
41 #include "config/the_isa.hh"
42 #include "cpu/inorder/cpu.hh"
43 #include "cpu/inorder/inorder_dyn_inst.hh"
44 #include "cpu/exetrace.hh"
45 #include "debug/InOrderDynInst.hh"
46 #include "mem/request.hh"
47
48 using namespace std;
49 using namespace TheISA;
50 using namespace ThePipeline;
51
52 InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
53 InOrderThreadState *state,
54 InstSeqNum seq_num,
55 ThreadID tid,
56 unsigned _asid)
57 : seqNum(seq_num), squashSeqNum(0), threadNumber(tid), asid(_asid),
58 virtProcNumber(0), staticInst(NULL), traceData(NULL), cpu(cpu),
59 thread(state), fault(NoFault), memData(NULL), loadData(0),
60 storeData(0), effAddr(0), physEffAddr(0), memReqFlags(0),
61 readyRegs(0), pc(0), predPC(0), memAddr(0), nextStage(0),
62 memTime(0), splitMemData(NULL), splitMemReq(NULL), totalSize(0),
63 split2ndSize(0), split2ndAddr(0), split2ndAccess(false),
64 split2ndDataPtr(NULL), split2ndFlags(0), splitInst(false),
65 splitFinishCnt(0), split2ndStoreDataPtr(NULL), splitInstSked(false),
66 inFrontEnd(true), frontSked(NULL), backSked(NULL),
67 squashingStage(0), predictTaken(false), procDelaySlotOnMispred(false),
68 fetchMemReq(NULL), dataMemReq(NULL), instEffAddr(0), eaCalcDone(false),
69 lqIdx(0), sqIdx(0), instListIt(NULL), onInstList(false)
70 {
71 for(int i = 0; i < MaxInstSrcRegs; i++) {
72 instSrc[i].integer = 0;
73 instSrc[i].dbl = 0;
74 _readySrcRegIdx[i] = false;
75 _srcRegIdx[i] = 0;
76 }
77
78 for(int j = 0; j < MaxInstDestRegs; j++) {
79 _destRegIdx[j] = 0;
80 _prevDestRegIdx[j] = 0;
81 }
82
83 ++instcount;
84 DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created."
85 " (active insts: %i)\n", threadNumber, seqNum, instcount);
86
87 }
88
89 int InOrderDynInst::instcount = 0;
90
91 void
92 InOrderDynInst::setMachInst(ExtMachInst machInst)
93 {
94 staticInst = StaticInst::decode(machInst, pc.instAddr());
95
96 for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
97 _destRegIdx[i] = this->staticInst->destRegIdx(i);
98 }
99
100 for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
101 _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
102 this->_readySrcRegIdx[i] = 0;
103 }
104 }
105
106 void
107 InOrderDynInst::initVars()
108 {
109 inFrontEnd = true;
110
111 fetchMemReq = NULL;
112 dataMemReq = NULL;
113 splitMemData = NULL;
114 split2ndAddr = 0;
115 split2ndAccess = false;
116 splitInst = false;
117 splitInstSked = false;
118 splitFinishCnt = 0;
119
120 effAddr = 0;
121 physEffAddr = 0;
122
123 readyRegs = 0;
124
125 nextStage = 0;
126
127 for(int i = 0; i < MaxInstDestRegs; i++)
128 instResult[i].val.integer = 0;
129
130 status.reset();
131
132 memAddrReady = false;
133 eaCalcDone = false;
134
135 predictTaken = false;
136 procDelaySlotOnMispred = false;
137
138 lqIdx = -1;
139 sqIdx = -1;
140
141 // Also make this a parameter, or perhaps get it from xc or cpu.
142 asid = 0;
143
144 virtProcNumber = 0;
145
146 // Initialize the fault to be NoFault.
147 fault = NoFault;
148
149 // Make sure to have the renamed register entries set to the same
150 // as the normal register entries. It will allow the IQ to work
151 // without any modifications.
152 if (this->staticInst) {
153 for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
154 _destRegIdx[i] = this->staticInst->destRegIdx(i);
155 }
156
157 for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
158 _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
159 this->_readySrcRegIdx[i] = 0;
160 }
161 }
162
163 // Update Instruction Count for this instruction
164 if (instcount > 100) {
165 fatal("Number of Active Instructions in CPU is too high. "
166 "(Not Dereferencing Ptrs. Correctly?)\n");
167 }
168 }
169
170 void
171 InOrderDynInst::resetInstCount()
172 {
173 instcount = 0;
174 }
175
176
177 InOrderDynInst::~InOrderDynInst()
178 {
179 if (fetchMemReq != 0x0) {
180 delete fetchMemReq;
181 fetchMemReq = NULL;
182 }
183
184 if (dataMemReq != 0x0) {
185 delete dataMemReq;
186 dataMemReq = NULL;
187 }
188
189 if (splitMemReq != 0x0) {
190 delete dataMemReq;
191 dataMemReq = NULL;
192 }
193
194 if (traceData)
195 delete traceData;
196
197 if (splitMemData)
198 delete [] splitMemData;
199
200 fault = NoFault;
201
202 --instcount;
203
204 DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed"
205 " (active insts: %i)\n", threadNumber, seqNum, instcount);
206 }
207
208 void
209 InOrderDynInst::setStaticInst(StaticInstPtr &static_inst)
210 {
211 this->staticInst = static_inst;
212
213 // Make sure to have the renamed register entries set to the same
214 // as the normal register entries. It will allow the IQ to work
215 // without any modifications.
216 if (this->staticInst) {
217 for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
218 _destRegIdx[i] = this->staticInst->destRegIdx(i);
219 }
220
221 for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
222 _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
223 this->_readySrcRegIdx[i] = 0;
224 }
225 }
226 }
227
228 Fault
229 InOrderDynInst::execute()
230 {
231 // @todo: Pretty convoluted way to avoid squashing from happening
232 // when using the TC during an instruction's execution
233 // (specifically for instructions that have side-effects that use
234 // the TC). Fix this.
235 bool in_syscall = this->thread->inSyscall;
236 this->thread->inSyscall = true;
237
238 this->fault = this->staticInst->execute(this, this->traceData);
239
240 this->thread->inSyscall = in_syscall;
241
242 return this->fault;
243 }
244
245 Fault
246 InOrderDynInst::calcEA()
247 {
248 this->fault = this->staticInst->eaComp(this, this->traceData);
249 return this->fault;
250 }
251
252 Fault
253 InOrderDynInst::initiateAcc()
254 {
255 // @todo: Pretty convoluted way to avoid squashing from happening
256 // when using the TC during an instruction's execution
257 // (specifically for instructions that have side-effects that use
258 // the TC). Fix this.
259 bool in_syscall = this->thread->inSyscall;
260 this->thread->inSyscall = true;
261
262 this->fault = this->staticInst->initiateAcc(this, this->traceData);
263
264 this->thread->inSyscall = in_syscall;
265
266 return this->fault;
267 }
268
269
270 Fault
271 InOrderDynInst::completeAcc(Packet *pkt)
272 {
273 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
274
275 return this->fault;
276 }
277
278 Fault
279 InOrderDynInst::memAccess()
280 {
281 return initiateAcc();
282 }
283
284
285 #if FULL_SYSTEM
286
287 Fault
288 InOrderDynInst::hwrei()
289 {
290 panic("InOrderDynInst: hwrei: unimplemented\n");
291 return NoFault;
292 }
293
294
295 void
296 InOrderDynInst::trap(Fault fault)
297 {
298 this->cpu->trap(fault, this->threadNumber, this);
299 }
300
301
302 bool
303 InOrderDynInst::simPalCheck(int palFunc)
304 {
305 #if THE_ISA != ALPHA_ISA
306 panic("simPalCheck called, but PAL only exists in Alpha!\n");
307 #endif
308 return this->cpu->simPalCheck(palFunc, this->threadNumber);
309 }
310 #else
311 void
312 InOrderDynInst::syscall(int64_t callnum)
313 {
314 cpu->syscall(callnum, this->threadNumber);
315 }
316 #endif
317
318 void
319 InOrderDynInst::setSquashInfo(unsigned stage_num)
320 {
321 squashingStage = stage_num;
322
323 // If it's a fault, then we need to squash
324 // the faulting instruction too. Squash
325 // functions squash above a seqNum, so we
326 // decrement here for that case
327 if (fault != NoFault) {
328 squashSeqNum = seqNum - 1;
329 return;
330 } else
331 squashSeqNum = seqNum;
332
333 #if ISA_HAS_DELAY_SLOT
334 if (isControl()) {
335 TheISA::PCState nextPC = pc;
336 TheISA::advancePC(nextPC, staticInst);
337
338 // Check to see if we should squash after the
339 // branch or after a branch delay slot.
340 if (pc.nextInstAddr() == pc.instAddr() + sizeof(MachInst))
341 squashSeqNum = seqNum + 1;
342 else
343 squashSeqNum = seqNum;
344 }
345 #endif
346 }
347
348 void
349 InOrderDynInst::releaseReq(ResourceRequest* req)
350 {
351 std::list<ResourceRequest*>::iterator list_it = reqList.begin();
352 std::list<ResourceRequest*>::iterator list_end = reqList.end();
353
354 while(list_it != list_end) {
355 if((*list_it)->getResIdx() == req->getResIdx() &&
356 (*list_it)->getSlot() == req->getSlot()) {
357 DPRINTF(InOrderDynInst, "[tid:%u]: [sn:%i] Done with request "
358 "to %s.\n", threadNumber, seqNum, req->res->name());
359 reqList.erase(list_it);
360 return;
361 }
362 list_it++;
363 }
364
365 panic("Releasing Res. Request That Isnt There!\n");
366 }
367
368 /** Records an integer source register being set to a value. */
369 void
370 InOrderDynInst::setIntSrc(int idx, uint64_t val)
371 {
372 DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set "
373 "to %#x.\n", threadNumber, seqNum, idx, val);
374 instSrc[idx].integer = val;
375 }
376
377 /** Records an fp register being set to a value. */
378 void
379 InOrderDynInst::setFloatSrc(int idx, FloatReg val)
380 {
381 instSrc[idx].dbl = val;
382 }
383
384 /** Records an fp register being set to an integer value. */
385 void
386 InOrderDynInst::setFloatRegBitsSrc(int idx, uint64_t val)
387 {
388 instSrc[idx].integer = val;
389 }
390
391 /** Reads a integer register. */
392 IntReg
393 InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
394 {
395 DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
396 threadNumber, seqNum, idx, instSrc[idx].integer);
397 return instSrc[idx].integer;
398 }
399
400 /** Reads a FP register. */
401 FloatReg
402 InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
403 {
404 return instSrc[idx].dbl;
405 }
406
407
408 /** Reads a FP register as a integer. */
409 FloatRegBits
410 InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx)
411 {
412 return instSrc[idx].integer;
413 }
414
415 /** Reads a miscellaneous register. */
416 MiscReg
417 InOrderDynInst::readMiscReg(int misc_reg)
418 {
419 return this->cpu->readMiscReg(misc_reg, threadNumber);
420 }
421
422
423 /** Reads a misc. register, including any side-effects the read
424 * might have as defined by the architecture.
425 */
426 MiscReg
427 InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
428 {
429 DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
430 " read as %#x.\n", threadNumber, seqNum, idx,
431 instSrc[idx].integer);
432 return instSrc[idx].integer;
433 }
434
435
436 /** Sets a misc. register, including any side-effects the write
437 * might have as defined by the architecture.
438 */
439 void
440 InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
441 const MiscReg &val)
442 {
443 instResult[idx].type = Integer;
444 instResult[idx].val.integer = val;
445 instResult[idx].tick = curTick();
446
447 DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
448 "being set to %#x.\n", threadNumber, seqNum, idx, val);
449 }
450
451 MiscReg
452 InOrderDynInst::readRegOtherThread(unsigned reg_idx, ThreadID tid)
453 {
454 if (tid == -1) {
455 tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
456 }
457
458 if (reg_idx < FP_Base_DepTag) { // Integer Register File
459 return this->cpu->readIntReg(reg_idx, tid);
460 } else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
461 reg_idx -= FP_Base_DepTag;
462 return this->cpu->readFloatRegBits(reg_idx, tid);
463 } else {
464 reg_idx -= Ctrl_Base_DepTag;
465 return this->cpu->readMiscReg(reg_idx, tid); // Misc. Register File
466 }
467 }
468
469 /** Sets a Integer register. */
470 void
471 InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
472 {
473 instResult[idx].type = Integer;
474 instResult[idx].val.integer = val;
475 instResult[idx].tick = curTick();
476
477 DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Int Reg. %i "
478 "being set to %#x (result-tick:%i).\n",
479 threadNumber, seqNum, idx, val, instResult[idx].tick);
480 }
481
482 /** Sets a FP register. */
483 void
484 InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
485 {
486 instResult[idx].val.dbl = val;
487 instResult[idx].type = Float;
488 instResult[idx].tick = curTick();
489
490 DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
491 "being set to %#x (result-tick:%i).\n",
492 threadNumber, seqNum, idx, val, instResult[idx].tick);
493 }
494
495 /** Sets a FP register as a integer. */
496 void
497 InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
498 FloatRegBits val)
499 {
500 instResult[idx].type = Integer;
501 instResult[idx].val.integer = val;
502 instResult[idx].tick = curTick();
503
504 DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
505 "being set to %#x (result-tick:%i).\n",
506 threadNumber, seqNum, idx, val, instResult[idx].tick);
507 }
508
509 /** Sets a misc. register, including any side-effects the write
510 * might have as defined by the architecture.
511 */
512 /* Alter this if/when wanting to *speculate* on Miscellaneous registers */
513 void
514 InOrderDynInst::setMiscReg(int misc_reg, const MiscReg &val)
515 {
516 this->cpu->setMiscReg(misc_reg, val, threadNumber);
517 }
518
519 void
520 InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
521 ThreadID tid)
522 {
523 if (tid == InvalidThreadID) {
524 tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
525 }
526
527 if (reg_idx < FP_Base_DepTag) { // Integer Register File
528 this->cpu->setIntReg(reg_idx, val, tid);
529 } else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
530 reg_idx -= FP_Base_DepTag;
531 this->cpu->setFloatRegBits(reg_idx, val, tid);
532 } else {
533 reg_idx -= Ctrl_Base_DepTag;
534 this->cpu->setMiscReg(reg_idx, val, tid); // Misc. Register File
535 }
536 }
537
538 void
539 InOrderDynInst::deallocateContext(int thread_num)
540 {
541 this->cpu->deallocateContext(thread_num);
542 }
543
544 Fault
545 InOrderDynInst::readBytes(Addr addr, uint8_t *data,
546 unsigned size, unsigned flags)
547 {
548 return cpu->read(this, addr, data, size, flags);
549 }
550
551 template<class T>
552 inline Fault
553 InOrderDynInst::read(Addr addr, T &data, unsigned flags)
554 {
555 if (traceData) {
556 traceData->setAddr(addr);
557 traceData->setData(data);
558 }
559 Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
560 DPRINTF(InOrderDynInst, "[sn:%i] (1) Received Bytes %x\n", seqNum, data);
561 data = TheISA::gtoh(data);
562 DPRINTF(InOrderDynInst, "[sn%:i] (2) Received Bytes %x\n", seqNum, data);
563
564 if (traceData)
565 traceData->setData(data);
566 return fault;
567 }
568
569 #ifndef DOXYGEN_SHOULD_SKIP_THIS
570
571 template
572 Fault
573 InOrderDynInst::read(Addr addr, Twin32_t &data, unsigned flags);
574
575 template
576 Fault
577 InOrderDynInst::read(Addr addr, Twin64_t &data, unsigned flags);
578
579 template
580 Fault
581 InOrderDynInst::read(Addr addr, uint64_t &data, unsigned flags);
582
583 template
584 Fault
585 InOrderDynInst::read(Addr addr, uint32_t &data, unsigned flags);
586
587 template
588 Fault
589 InOrderDynInst::read(Addr addr, uint16_t &data, unsigned flags);
590
591 template
592 Fault
593 InOrderDynInst::read(Addr addr, uint8_t &data, unsigned flags);
594
595 #endif //DOXYGEN_SHOULD_SKIP_THIS
596
597 template<>
598 Fault
599 InOrderDynInst::read(Addr addr, double &data, unsigned flags)
600 {
601 return read(addr, *(uint64_t*)&data, flags);
602 }
603
604 template<>
605 Fault
606 InOrderDynInst::read(Addr addr, float &data, unsigned flags)
607 {
608 return read(addr, *(uint32_t*)&data, flags);
609 }
610
611 template<>
612 Fault
613 InOrderDynInst::read(Addr addr, int32_t &data, unsigned flags)
614 {
615 return read(addr, (uint32_t&)data, flags);
616 }
617
618 Fault
619 InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
620 Addr addr, unsigned flags, uint64_t *res)
621 {
622 assert(sizeof(storeData) >= size);
623 memcpy(&storeData, data, size);
624 DPRINTF(InOrderDynInst, "(2) [tid:%i]: [sn:%i] Setting store data to %#x.\n",
625 threadNumber, seqNum, storeData);
626 return cpu->write(this, (uint8_t *)&storeData, size, addr, flags, res);
627 }
628
629 template<class T>
630 inline Fault
631 InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
632 {
633 if (traceData) {
634 traceData->setAddr(addr);
635 traceData->setData(data);
636 }
637 data = TheISA::htog(data);
638 DPRINTF(InOrderDynInst, "(1) [tid:%i]: [sn:%i] Setting store data to %#x.\n",
639 threadNumber, seqNum, data);
640 return writeBytes((uint8_t*)&data, sizeof(T), addr, flags, res);
641 }
642
643 #ifndef DOXYGEN_SHOULD_SKIP_THIS
644
645 template
646 Fault
647 InOrderDynInst::write(Twin32_t data, Addr addr,
648 unsigned flags, uint64_t *res);
649
650 template
651 Fault
652 InOrderDynInst::write(Twin64_t data, Addr addr,
653 unsigned flags, uint64_t *res);
654 template
655 Fault
656 InOrderDynInst::write(uint64_t data, Addr addr,
657 unsigned flags, uint64_t *res);
658
659 template
660 Fault
661 InOrderDynInst::write(uint32_t data, Addr addr,
662 unsigned flags, uint64_t *res);
663
664 template
665 Fault
666 InOrderDynInst::write(uint16_t data, Addr addr,
667 unsigned flags, uint64_t *res);
668
669 template
670 Fault
671 InOrderDynInst::write(uint8_t data, Addr addr,
672 unsigned flags, uint64_t *res);
673
674 #endif //DOXYGEN_SHOULD_SKIP_THIS
675
676 template<>
677 Fault
678 InOrderDynInst::write(double data, Addr addr, unsigned flags, uint64_t *res)
679 {
680 return write(*(uint64_t*)&data, addr, flags, res);
681 }
682
683 template<>
684 Fault
685 InOrderDynInst::write(float data, Addr addr, unsigned flags, uint64_t *res)
686 {
687 return write(*(uint32_t*)&data, addr, flags, res);
688 }
689
690
691 template<>
692 Fault
693 InOrderDynInst::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
694 {
695 return write((uint32_t)data, addr, flags, res);
696 }
697
698
699 void
700 InOrderDynInst::dump()
701 {
702 cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
703 cout << staticInst->disassemble(pc.instAddr());
704 cprintf("'\n");
705 }
706
707 void
708 InOrderDynInst::dump(std::string &outstring)
709 {
710 std::ostringstream s;
711 s << "T" << threadNumber << " : " << pc << " "
712 << staticInst->disassemble(pc.instAddr());
713
714 outstring = s.str();
715 }
716
717
718 #define NOHASH
719 #ifndef NOHASH
720
721 #include "base/hashmap.hh"
722
723 unsigned int MyHashFunc(const InOrderDynInst *addr)
724 {
725 unsigned a = (unsigned)addr;
726 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
727
728 return hash;
729 }
730
731 typedef m5::hash_map<const InOrderDynInst *, const InOrderDynInst *,
732 MyHashFunc>
733 my_hash_t;
734
735 my_hash_t thishash;
736 #endif