2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/isa_traits.hh"
41 #include "arch/faults.hh"
42 #include "arch/types.hh"
44 #include "base/fast_alloc.hh"
45 #include "base/trace.hh"
46 #include "cpu/inorder/inorder_trace.hh"
47 #include "config/full_system.hh"
48 #include "cpu/thread_context.hh"
49 #include "cpu/exetrace.hh"
50 #include "cpu/inst_seq.hh"
51 #include "cpu/op_class.hh"
52 #include "cpu/static_inst.hh"
53 #include "cpu/inorder/thread_state.hh"
54 #include "cpu/inorder/resource.hh"
55 #include "cpu/inorder/pipeline_traits.hh"
56 #include "mem/packet.hh"
57 #include "sim/system.hh"
61 * Defines a dynamic instruction context for a inorder CPU model.
64 // Forward declaration.
66 class ResourceRequest;
68 class InOrderDynInst : public FastAlloc, public RefCounted
71 // Binary machine instruction type.
72 typedef TheISA::MachInst MachInst;
73 // Extended machine instruction type
74 typedef TheISA::ExtMachInst ExtMachInst;
75 // Logical register index type.
76 typedef TheISA::RegIndex RegIndex;
77 // Integer register type.
78 typedef TheISA::IntReg IntReg;
79 // Floating point register type.
80 typedef TheISA::FloatReg FloatReg;
81 // Floating point register type.
82 typedef TheISA::MiscReg MiscReg;
84 typedef short int PhysRegIndex;
86 /** The refcounted DynInst pointer to be used. In most cases this is
87 * what should be used, and not DynInst*.
89 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
91 // The list of instructions iterator type.
92 typedef std::list<DynInstPtr>::iterator ListIt;
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
100 /** BaseDynInst constructor given a binary instruction.
101 * @param inst The binary instruction.
102 * @param PC The PC of the instruction.
103 * @param pred_PC The predicted next PC.
104 * @param seq_num The sequence number of the instruction.
105 * @param cpu Pointer to the instruction's CPU.
107 InOrderDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
110 /** BaseDynInst constructor given a binary instruction.
111 * @param seq_num The sequence number of the instruction.
112 * @param cpu Pointer to the instruction's CPU.
113 * NOTE: Must set Binary Instrution through Member Function
115 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
116 InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
118 /** BaseDynInst constructor given a StaticInst pointer.
119 * @param _staticInst The StaticInst for this BaseDynInst.
121 InOrderDynInst(StaticInstPtr &_staticInst);
123 /** Skeleton Constructor. */
126 /** InOrderDynInst destructor. */
130 /** The sequence number of the instruction. */
133 /** The sequence number of the instruction. */
134 InstSeqNum bdelaySeqNum;
137 RegDepMapEntry, /// Instruction has been entered onto the RegDepMap
138 IqEntry, /// Instruction is in the IQ
139 RobEntry, /// Instruction is in the ROB
140 LsqEntry, /// Instruction is in the LSQ
141 Completed, /// Instruction has completed
142 ResultReady, /// Instruction has its result
143 CanIssue, /// Instruction can issue and execute
144 Issued, /// Instruction has issued
145 Executed, /// Instruction has executed
146 CanCommit, /// Instruction can commit
147 AtCommit, /// Instruction has reached commit
148 Committed, /// Instruction has committed
149 Squashed, /// Instruction is squashed
150 SquashedInIQ, /// Instruction is squashed in the IQ
151 SquashedInLSQ, /// Instruction is squashed in the LSQ
152 SquashedInROB, /// Instruction is squashed in the ROB
153 RecoverInst, /// Is a recover instruction
154 BlockingInst, /// Is a blocking instruction
155 ThreadsyncWait, /// Is a thread synchronization instruction
156 SerializeBefore, /// Needs to serialize on
157 /// instructions ahead of it
158 SerializeAfter, /// Needs to serialize instructions behind it
159 SerializeHandled, /// Serialization has been handled
163 /** The status of this BaseDynInst. Several bits can be set. */
164 std::bitset<NumStatus> status;
166 /** The thread this instruction is from. */
169 /** data address space ID, for loads & stores. */
172 /** The virtual processor number */
173 short virtProcNumber;
175 /** The StaticInst used by this BaseDynInst. */
176 StaticInstPtr staticInst;
178 /** InstRecord that tracks this instructions. */
179 Trace::InOrderTraceRecord *traceData;
181 /** Pointer to the Impl's CPU object. */
184 /** Pointer to the thread state. */
185 InOrderThreadState *thread;
187 /** The kind of fault this instruction has generated. */
190 /** The memory request. */
193 /** Pointer to the data for the memory access. */
196 /** Data used for a store for operation. */
199 /** Data used for a store for operation. */
202 /** The resource schedule for this inst */
203 ThePipeline::ResSchedule resSched;
205 /** List of active resource requests for this instruction */
206 std::list<ResourceRequest*> reqList;
208 /** The effective virtual address (lds & stores only). */
211 /** The effective physical address. */
214 /** Effective virtual address for a copy source. */
217 /** Effective physical address for a copy source. */
218 Addr copySrcPhysEffAddr;
220 /** The memory request flags (from translation). */
221 unsigned memReqFlags;
223 /** How many source registers are ready. */
226 /** An instruction src/dest has to be one of these types */
232 //@TODO: Naming Convention for Enums?
241 /** Result of an instruction execution */
249 : type(None), tick(0), width(0)
253 /** The source of the instruction; assumes for now that there's only one
254 * destination register.
256 InstValue instSrc[MaxInstSrcRegs];
258 /** The result of the instruction; assumes for now that there's only one
259 * destination register.
261 InstResult instResult[MaxInstDestRegs];
263 /** PC of this instruction. */
266 /** Next non-speculative PC. It is not filled in at fetch, but rather
267 * once the target of the branch is truly known (either decode or
272 /** Next next non-speculative PC. It is not filled in at fetch, but rather
273 * once the target of the branch is truly known (either decode or
278 /** Predicted next PC. */
281 /** Predicted next NPC. */
284 /** Predicted next microPC */
287 /** Address to fetch from */
290 /** Address to get/write data from/to */
293 /** Whether or not the source register is ready.
294 * @todo: Not sure this should be here vs the derived class.
296 bool _readySrcRegIdx[MaxInstSrcRegs];
298 /** Physical register index of the destination registers of this
301 PhysRegIndex _destRegIdx[MaxInstDestRegs];
303 /** Physical register index of the source registers of this
306 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
308 /** Physical register index of the previous producers of the
309 * architected destinations.
311 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
315 /* vars to keep track of InstStage's - used for resource sched defn */
316 int nextInstStageNum;
317 ThePipeline::InstStage *currentInstStage;
318 std::list<ThePipeline::InstStage*> instStageList;
321 /** Function to initialize variables in the constructors. */
327 ////////////////////////////////////////////////////////////
329 // BASE INSTRUCTION INFORMATION.
331 ////////////////////////////////////////////////////////////
332 std::string instName() { return staticInst->getName(); }
335 void setMachInst(ExtMachInst inst);
337 /** Sets the StaticInst. */
338 void setStaticInst(StaticInstPtr &static_inst);
340 /** Sets the sequence number. */
341 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
343 /** Sets the ASID. */
344 void setASID(short addr_space_id) { asid = addr_space_id; }
346 /** Reads the thread id. */
347 short readTid() { return threadNumber; }
349 /** Sets the thread id. */
350 void setTid(ThreadID tid) { threadNumber = tid; }
352 void setVpn(int id) { virtProcNumber = id; }
354 int readVpn() { return virtProcNumber; }
356 /** Sets the pointer to the thread state. */
357 void setThreadState(InOrderThreadState *state) { thread = state; }
359 /** Returns the thread context. */
360 ThreadContext *tcBase() { return thread->getTC(); }
362 /** Returns the fault type. */
363 Fault getFault() { return fault; }
365 ////////////////////////////////////////////////////////////
367 // INSTRUCTION TYPES - Forward checks to StaticInst object.
369 ////////////////////////////////////////////////////////////
370 bool isNop() const { return staticInst->isNop(); }
371 bool isMemRef() const { return staticInst->isMemRef(); }
372 bool isLoad() const { return staticInst->isLoad(); }
373 bool isStore() const { return staticInst->isStore(); }
374 bool isStoreConditional() const
375 { return staticInst->isStoreConditional(); }
376 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
377 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
378 bool isCopy() const { return staticInst->isCopy(); }
379 bool isInteger() const { return staticInst->isInteger(); }
380 bool isFloating() const { return staticInst->isFloating(); }
381 bool isControl() const { return staticInst->isControl(); }
382 bool isCall() const { return staticInst->isCall(); }
383 bool isReturn() const { return staticInst->isReturn(); }
384 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
385 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
386 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
387 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
388 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
390 bool isThreadSync() const { return staticInst->isThreadSync(); }
391 bool isSerializing() const { return staticInst->isSerializing(); }
392 bool isSerializeBefore() const
393 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
394 bool isSerializeAfter() const
395 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
396 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
397 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
398 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
399 bool isQuiesce() const { return staticInst->isQuiesce(); }
400 bool isIprAccess() const { return staticInst->isIprAccess(); }
401 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
403 /////////////////////////////////////////////
405 // RESOURCE SCHEDULING
407 /////////////////////////////////////////////
409 void setNextStage(int stage_num) { nextStage = stage_num; }
410 int getNextStage() { return nextStage; }
412 ThePipeline::InstStage *addStage();
413 ThePipeline::InstStage *addStage(int stage);
414 ThePipeline::InstStage *currentStage() { return currentInstStage; }
417 /** Add A Entry To Reource Schedule */
418 void addToSched(ThePipeline::ScheduleEntry* sched_entry)
419 { resSched.push(sched_entry); }
422 /** Print Resource Schedule */
423 /** @NOTE: DEBUG ONLY */
426 ThePipeline::ResSchedule tempSched;
427 std::cerr << "\tInst. Res. Schedule: ";
428 while (!resSched.empty()) {
429 std::cerr << '\t' << resSched.top()->stageNum << "-"
430 << resSched.top()->resNum << ", ";
432 tempSched.push(resSched.top());
436 std::cerr << std::endl;
437 resSched = tempSched;
440 /** Return Next Resource Stage To Be Used */
443 if (resSched.empty())
446 return resSched.top()->stageNum;
450 /** Return Next Resource To Be Used */
453 if (resSched.empty())
456 return resSched.top()->resNum;
459 /** Remove & Deallocate a schedule entry */
462 if (!resSched.empty()) {
463 ThePipeline::ScheduleEntry* sked = resSched.top();
469 /** Release a Resource Request (Currently Unused) */
470 void releaseReq(ResourceRequest* req);
472 ////////////////////////////////////////////
474 // INSTRUCTION EXECUTION
476 ////////////////////////////////////////////
477 /** Returns the opclass of this instruction. */
478 OpClass opClass() const { return staticInst->opClass(); }
480 /** Executes the instruction.*/
485 unsigned getCurResSlot() { return curResSlot; }
487 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
489 /** Calls a syscall. */
490 void syscall(int64_t callnum);
491 void prefetch(Addr addr, unsigned flags);
492 void writeHint(Addr addr, int size, unsigned flags);
493 Fault copySrcTranslate(Addr src);
494 Fault copy(Addr dest);
496 ////////////////////////////////////////////////////////////
498 // MULTITHREADING INTERFACE TO CPU MODELS
500 ////////////////////////////////////////////////////////////
501 virtual void deallocateContext(int thread_num);
503 virtual void enableVirtProcElement(unsigned vpe);
504 virtual void disableVirtProcElement(unsigned vpe);
506 virtual void enableMultiThreading(unsigned vpe);
507 virtual void disableMultiThreading(unsigned vpe);
509 ////////////////////////////////////////////////////////////
511 // PROGRAM COUNTERS - PC/NPC/NPC
513 ////////////////////////////////////////////////////////////
514 /** Read the PC of this instruction. */
515 const Addr readPC() const { return PC; }
517 /** Sets the PC of this instruction. */
518 void setPC(Addr pc) { PC = pc; }
520 /** Returns the next PC. This could be the speculative next PC if it is
521 * called prior to the actual branch target being calculated.
523 Addr readNextPC() { return nextPC; }
525 /** Set the next PC of this instruction (its actual target). */
526 void setNextPC(uint64_t val) { nextPC = val; }
528 /** Returns the next NPC. This could be the speculative next NPC if it is
529 * called prior to the actual branch target being calculated.
533 #if ISA_HAS_DELAY_SLOT
536 return nextPC + sizeof(TheISA::MachInst);
540 /** Set the next PC of this instruction (its actual target). */
541 void setNextNPC(uint64_t val) { nextNPC = val; }
543 ////////////////////////////////////////////////////////////
547 ////////////////////////////////////////////////////////////
548 /** Set the predicted target of this current instruction. */
549 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
551 /** Returns the predicted target of the branch. */
552 Addr readPredTarg() { return predPC; }
554 /** Returns the predicted PC immediately after the branch. */
555 Addr readPredPC() { return predPC; }
557 /** Returns the predicted PC two instructions after the branch */
558 Addr readPredNPC() { return predNPC; }
560 /** Returns the predicted micro PC after the branch */
561 Addr readPredMicroPC() { return predMicroPC; }
563 /** Returns whether the instruction was predicted taken or not. */
564 bool predTaken() { return predictTaken; }
566 /** Returns whether the instruction mispredicted. */
569 #if ISA_HAS_DELAY_SLOT
570 return predPC != nextNPC;
572 return predPC != nextPC;
576 /** Returns whether the instruction mispredicted. */
577 bool mistargeted() { return predPC != nextNPC; }
579 /** Returns the branch target address. */
580 Addr branchTarget() const { return staticInst->branchTarget(PC); }
582 /** Checks whether or not this instruction has had its branch target
583 * calculated yet. For now it is not utilized and is hacked to be
585 * @todo: Actually use this instruction.
587 bool doneTargCalc() { return false; }
589 void setBranchPred(bool prediction) { predictTaken = prediction; }
595 bool procDelaySlotOnMispred;
597 ////////////////////////////////////////////
601 ////////////////////////////////////////////
603 * Does a read to a given address.
604 * @param addr The address to read.
605 * @param data The read's data is written into this parameter.
606 * @param flags The request's flags.
607 * @return Returns any fault due to the read.
610 Fault read(Addr addr, T &data, unsigned flags);
613 * Does a write to a given address.
614 * @param data The data to be written.
615 * @param addr The address to write to.
616 * @param flags The request's flags.
617 * @param res The result of the write (for load locked/store conditionals).
618 * @return Returns any fault due to the write.
621 Fault write(T data, Addr addr, unsigned flags,
624 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory Access
625 * Only valid for memory operations.
629 /** Completes a memory access - Only valid for memory operations. */
630 Fault completeAcc(Packet *pkt);
632 /** Calculates Eff. Addr. part of a memory instruction. */
635 /** Read Effective Address from instruction & do memory access */
638 RequestPtr fetchMemReq;
639 RequestPtr dataMemReq;
644 { return memAddrReady; }
646 void setMemAddr(Addr addr)
647 { memAddr = addr; memAddrReady = true;}
650 { memAddrReady = false;}
655 /** Sets the effective address. */
656 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
658 /** Returns the effective address. */
659 const Addr &getEA() const { return instEffAddr; }
661 /** Returns whether or not the eff. addr. calculation has been completed. */
662 bool doneEACalc() { return eaCalcDone; }
664 /** Returns whether or not the eff. addr. source registers are ready.
665 * Assume that src registers 1..n-1 are the ones that the
666 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
671 for (int i = 1; i < numSrcRegs(); ++i) {
672 if (!_readySrcRegIdx[i])
679 //////////////////////////////////////////////////
681 // SOURCE-DESTINATION REGISTER INDEXING
683 //////////////////////////////////////////////////
684 /** Returns the number of source registers. */
685 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
687 /** Returns the number of destination registers. */
688 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
690 // the following are used to track physical register usage
691 // for machines with separate int & FP reg files
692 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
693 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
695 /** Returns the logical register index of the i'th destination register. */
696 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
698 /** Returns the logical register index of the i'th source register. */
699 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
701 //////////////////////////////////////////////////
703 // RENAME/PHYSICAL REGISTER FILE SUPPORT
705 //////////////////////////////////////////////////
706 /** Returns the physical register index of the i'th destination
709 PhysRegIndex renamedDestRegIdx(int idx) const
711 return _destRegIdx[idx];
714 /** Returns the physical register index of the i'th source register. */
715 PhysRegIndex renamedSrcRegIdx(int idx) const
717 return _srcRegIdx[idx];
720 /** Returns the physical register index of the previous physical register
721 * that remapped to the same logical register index.
723 PhysRegIndex prevDestRegIdx(int idx) const
725 return _prevDestRegIdx[idx];
728 /** Returns if a source register is ready. */
729 bool isReadySrcRegIdx(int idx) const
731 return this->_readySrcRegIdx[idx];
734 /** Records that one of the source registers is ready. */
735 void markSrcRegReady()
737 if (++readyRegs == numSrcRegs()) {
738 status.set(CanIssue);
742 /** Marks a specific register as ready. */
743 void markSrcRegReady(RegIndex src_idx)
745 _readySrcRegIdx[src_idx] = true;
750 /** Renames a destination register to a physical register. Also records
751 * the previous physical register that the logical register mapped to.
753 void renameDestReg(int idx,
754 PhysRegIndex renamed_dest,
755 PhysRegIndex previous_rename)
757 _destRegIdx[idx] = renamed_dest;
758 _prevDestRegIdx[idx] = previous_rename;
761 /** Renames a source logical register to the physical register which
762 * has/will produce that logical register's result.
763 * @todo: add in whether or not the source register is ready.
765 void renameSrcReg(int idx, PhysRegIndex renamed_src)
767 _srcRegIdx[idx] = renamed_src;
771 PhysRegIndex readDestRegIdx(int idx)
773 return _destRegIdx[idx];
776 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
778 _destRegIdx[idx] = dest_idx;
781 int getDestIdxNum(PhysRegIndex dest_idx)
783 for (int i=0; i < staticInst->numDestRegs(); i++) {
784 if (_destRegIdx[i] == dest_idx)
791 PhysRegIndex readSrcRegIdx(int idx)
793 return _srcRegIdx[idx];
796 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
798 _srcRegIdx[idx] = src_idx;
801 int getSrcIdxNum(PhysRegIndex src_idx)
803 for (int i=0; i < staticInst->numSrcRegs(); i++) {
804 if (_srcRegIdx[i] == src_idx)
811 ////////////////////////////////////////////////////
813 // SOURCE-DESTINATION REGISTER VALUES
815 ////////////////////////////////////////////////////
817 /** Functions that sets an integer or floating point
818 * source register to a value. */
819 void setIntSrc(int idx, uint64_t val);
820 void setFloatSrc(int idx, FloatReg val, int width = 32);
821 void setFloatRegBitsSrc(int idx, uint64_t val);
823 uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
824 uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
826 /** These Instructions read a integer/float/misc. source register
827 * value in the instruction. The instruction's execute function will
828 * call these and it is the interface that is used by the ISA descr.
829 * language (which is why the name isnt readIntSrc(...)) Note: That
830 * the source reg. value is set using the setSrcReg() function.
832 IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
833 FloatReg readFloatRegOperand(const StaticInst *si, int idx,
834 int width = TheISA::SingleWidth);
835 TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
836 int width = TheISA::SingleWidth);
837 MiscReg readMiscReg(int misc_reg);
838 MiscReg readMiscRegNoEffect(int misc_reg);
839 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
840 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
842 /** Returns the result value instruction. */
843 ResultType resultType(int idx)
845 return instResult[idx].type;
848 uint64_t readIntResult(int idx)
850 return instResult[idx].val.integer;
853 /** Depending on type, return Float or Double */
854 double readFloatResult(int idx)
856 //Should this function have a parameter for what width of return?x
857 return (instResult[idx].type == Float) ?
858 (float) instResult[idx].val.dbl : instResult[idx].val.dbl;
861 double readDoubleResult(int idx)
863 assert(instResult[idx].type == Double);
864 return instResult[idx].val.dbl;
867 Tick readResultTime(int idx) { return instResult[idx].tick; }
869 uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
871 /** This is the interface that an instruction will use to write
872 * it's destination register.
874 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
875 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
876 int width = TheISA::SingleWidth);
877 void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val,
878 int width = TheISA::SingleWidth);
879 void setMiscReg(int misc_reg, const MiscReg &val);
880 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
881 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
882 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val);
884 virtual uint64_t readRegOtherThread(unsigned idx,
885 ThreadID tid = InvalidThreadID);
886 virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
887 ThreadID tid = InvalidThreadID);
889 /** Sets the number of consecutive store conditional failures. */
890 void setStCondFailures(unsigned sc_failures)
891 { thread->storeCondFailures = sc_failures; }
893 //////////////////////////////////////////////////////////////
895 // INSTRUCTION STATUS FLAGS (READ/SET)
897 //////////////////////////////////////////////////////////////
898 /** Sets this instruction as entered on the CPU Reg Dep Map */
899 void setRegDepEntry() { status.set(RegDepMapEntry); }
901 /** Returns whether or not the entry is on the CPU Reg Dep Map */
902 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
904 /** Sets this instruction as completed. */
905 void setCompleted() { status.set(Completed); }
907 /** Returns whether or not this instruction is completed. */
908 bool isCompleted() const { return status[Completed]; }
910 /** Marks the result as ready. */
911 void setResultReady() { status.set(ResultReady); }
913 /** Returns whether or not the result is ready. */
914 bool isResultReady() const { return status[ResultReady]; }
916 /** Sets this instruction as ready to issue. */
917 void setCanIssue() { status.set(CanIssue); }
919 /** Returns whether or not this instruction is ready to issue. */
920 bool readyToIssue() const { return status[CanIssue]; }
922 /** Sets this instruction as issued from the IQ. */
923 void setIssued() { status.set(Issued); }
925 /** Returns whether or not this instruction has issued. */
926 bool isIssued() const { return status[Issued]; }
928 /** Sets this instruction as executed. */
929 void setExecuted() { status.set(Executed); }
931 /** Returns whether or not this instruction has executed. */
932 bool isExecuted() const { return status[Executed]; }
934 /** Sets this instruction as ready to commit. */
935 void setCanCommit() { status.set(CanCommit); }
937 /** Clears this instruction as being ready to commit. */
938 void clearCanCommit() { status.reset(CanCommit); }
940 /** Returns whether or not this instruction is ready to commit. */
941 bool readyToCommit() const { return status[CanCommit]; }
943 void setAtCommit() { status.set(AtCommit); }
945 bool isAtCommit() { return status[AtCommit]; }
947 /** Sets this instruction as committed. */
948 void setCommitted() { status.set(Committed); }
950 /** Returns whether or not this instruction is committed. */
951 bool isCommitted() const { return status[Committed]; }
953 /** Sets this instruction as squashed. */
954 void setSquashed() { status.set(Squashed); }
956 /** Returns whether or not this instruction is squashed. */
957 bool isSquashed() const { return status[Squashed]; }
959 /** Temporarily sets this instruction as a serialize before instruction. */
960 void setSerializeBefore() { status.set(SerializeBefore); }
962 /** Clears the serializeBefore part of this instruction. */
963 void clearSerializeBefore() { status.reset(SerializeBefore); }
965 /** Checks if this serializeBefore is only temporarily set. */
966 bool isTempSerializeBefore() { return status[SerializeBefore]; }
968 /** Temporarily sets this instruction as a serialize after instruction. */
969 void setSerializeAfter() { status.set(SerializeAfter); }
971 /** Clears the serializeAfter part of this instruction.*/
972 void clearSerializeAfter() { status.reset(SerializeAfter); }
974 /** Checks if this serializeAfter is only temporarily set. */
975 bool isTempSerializeAfter() { return status[SerializeAfter]; }
977 /** Sets the serialization part of this instruction as handled. */
978 void setSerializeHandled() { status.set(SerializeHandled); }
980 /** Checks if the serialization part of this instruction has been
981 * handled. This does not apply to the temporary serializing
982 * state; it only applies to this instruction's own permanent
985 bool isSerializeHandled() { return status[SerializeHandled]; }
988 /** Instruction effective address.
989 * @todo: Consider if this is necessary or not.
993 /** Whether or not the effective address calculation is completed.
994 * @todo: Consider if this is necessary or not.
999 /** Whether or not the memory operation is done. */
1003 /** Load queue index. */
1006 /** Store queue index. */
1009 /** Iterator pointing to this BaseDynInst in the list of all insts. */
1012 /** Returns iterator to this instruction in the list of all insts. */
1013 ListIt &getInstListIt() { return instListIt; }
1015 /** Sets iterator for this instruction in the list of all insts. */
1016 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
1018 /** Count of total number of dynamic instructions. */
1019 static int instcount;
1021 /** Dumps out contents of this BaseDynInst. */
1024 /** Dumps out contents of this BaseDynInst into given string. */
1025 void dump(std::string &outstring);
1028 //inline int curCount() { return curCount(); }
1032 #endif // __CPU_BASE_DYN_INST_HH__