2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/faults.hh"
41 #include "arch/isa_traits.hh"
43 #include "arch/types.hh"
44 #include "base/fast_alloc.hh"
45 #include "base/trace.hh"
46 #include "base/types.hh"
47 #include "config/full_system.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/exetrace.hh"
50 #include "cpu/inorder/inorder_trace.hh"
51 #include "cpu/inorder/pipeline_traits.hh"
52 #include "cpu/inorder/resource.hh"
53 #include "cpu/inorder/resource_sked.hh"
54 #include "cpu/inorder/thread_state.hh"
55 #include "cpu/inst_seq.hh"
56 #include "cpu/op_class.hh"
57 #include "cpu/static_inst.hh"
58 #include "cpu/thread_context.hh"
59 #include "mem/packet.hh"
60 #include "sim/system.hh"
62 #if THE_ISA == ALPHA_ISA
63 #include "arch/alpha/ev5.hh"
68 * Defines a dynamic instruction context for a inorder CPU model.
71 // Forward declaration.
73 class ResourceRequest;
76 class InOrderDynInst : public FastAlloc, public RefCounted
79 // Binary machine instruction type.
80 typedef TheISA::MachInst MachInst;
81 // Extended machine instruction type
82 typedef TheISA::ExtMachInst ExtMachInst;
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
89 // Floating point register type.
90 typedef TheISA::MiscReg MiscReg;
92 typedef short int PhysRegIndex;
94 /** The refcounted DynInst pointer to be used. In most cases this is
95 * what should be used, and not DynInst*.
97 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
99 // The list of instructions iterator type.
100 typedef std::list<DynInstPtr>::iterator ListIt;
103 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
104 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
108 /** BaseDynInst constructor given a binary instruction.
109 * @param inst The binary instruction.
110 * @param PC The PC of the instruction.
111 * @param pred_PC The predicted next PC.
112 * @param seq_num The sequence number of the instruction.
113 * @param cpu Pointer to the instruction's CPU.
115 InOrderDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
118 /** BaseDynInst constructor given a binary instruction.
119 * @param seq_num The sequence number of the instruction.
120 * @param cpu Pointer to the instruction's CPU.
121 * NOTE: Must set Binary Instrution through Member Function
123 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
124 InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
126 /** BaseDynInst constructor given a StaticInst pointer.
127 * @param _staticInst The StaticInst for this BaseDynInst.
129 InOrderDynInst(StaticInstPtr &_staticInst);
131 /** Skeleton Constructor. */
134 /** InOrderDynInst destructor. */
138 /** The sequence number of the instruction. */
141 /** The sequence number of the instruction. */
142 InstSeqNum bdelaySeqNum;
145 RegDepMapEntry, /// Instruction is entered onto the RegDepMap
146 IqEntry, /// Instruction is in the IQ
147 RobEntry, /// Instruction is in the ROB
148 LsqEntry, /// Instruction is in the LSQ
149 Completed, /// Instruction has completed
150 ResultReady, /// Instruction has its result
151 CanIssue, /// Instruction can issue and execute
152 Issued, /// Instruction has issued
153 Executed, /// Instruction has executed
154 CanCommit, /// Instruction can commit
155 AtCommit, /// Instruction has reached commit
156 Committed, /// Instruction has committed
157 Squashed, /// Instruction is squashed
158 SquashedInIQ, /// Instruction is squashed in the IQ
159 SquashedInLSQ, /// Instruction is squashed in the LSQ
160 SquashedInROB, /// Instruction is squashed in the ROB
161 RecoverInst, /// Is a recover instruction
162 BlockingInst, /// Is a blocking instruction
163 ThreadsyncWait, /// Is a thread synchronization instruction
164 SerializeBefore, /// Needs to serialize on
165 /// instructions ahead of it
166 SerializeAfter, /// Needs to serialize instructions behind it
167 SerializeHandled, /// Serialization has been handled
168 RemoveList, /// Is Instruction on Remove List?
172 /** The status of this BaseDynInst. Several bits can be set. */
173 std::bitset<NumStatus> status;
175 /** The thread this instruction is from. */
178 /** data address space ID, for loads & stores. */
181 /** The virtual processor number */
182 short virtProcNumber;
184 /** The StaticInst used by this BaseDynInst. */
185 StaticInstPtr staticInst;
187 /** InstRecord that tracks this instructions. */
188 Trace::InOrderTraceRecord *traceData;
190 /** Pointer to the Impl's CPU object. */
193 /** Pointer to the thread state. */
194 InOrderThreadState *thread;
196 /** The kind of fault this instruction has generated. */
199 /** The memory request. */
202 /** Pointer to the data for the memory access. */
205 /** Data used for a store for operation. */
208 /** Data used for a store for operation. */
211 /** The resource schedule for this inst */
212 ThePipeline::ResSchedule resSched;
214 /** List of active resource requests for this instruction */
215 std::list<ResourceRequest*> reqList;
217 /** The effective virtual address (lds & stores only). */
220 /** The effective physical address. */
223 /** Effective virtual address for a copy source. */
226 /** Effective physical address for a copy source. */
227 Addr copySrcPhysEffAddr;
229 /** The memory request flags (from translation). */
230 unsigned memReqFlags;
232 /** How many source registers are ready. */
235 /** An instruction src/dest has to be one of these types */
241 //@TODO: Naming Convention for Enums?
250 /** Result of an instruction execution */
257 : type(None), tick(0)
261 /** The source of the instruction; assumes for now that there's only one
262 * destination register.
264 InstValue instSrc[MaxInstSrcRegs];
266 /** The result of the instruction; assumes for now that there's only one
267 * destination register.
269 InstResult instResult[MaxInstDestRegs];
271 /** PC of this instruction. */
274 /** Next non-speculative PC. It is not filled in at fetch, but rather
275 * once the target of the branch is truly known (either decode or
280 /** Next next non-speculative PC. It is not filled in at fetch, but rather
281 * once the target of the branch is truly known (either decode or
286 /** Predicted next PC. */
289 /** Predicted next NPC. */
292 /** Predicted next microPC */
295 /** Address to fetch from */
298 /** Address to get/write data from/to */
301 /** Whether or not the source register is ready.
302 * @todo: Not sure this should be here vs the derived class.
304 bool _readySrcRegIdx[MaxInstSrcRegs];
306 /** Physical register index of the destination registers of this
309 PhysRegIndex _destRegIdx[MaxInstDestRegs];
311 /** Physical register index of the source registers of this
314 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
316 /** Physical register index of the previous producers of the
317 * architected destinations.
319 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
323 /* vars to keep track of InstStage's - used for resource sched defn */
324 int nextInstStageNum;
325 ThePipeline::InstStage *currentInstStage;
326 std::list<ThePipeline::InstStage*> instStageList;
329 /** Function to initialize variables in the constructors. */
335 PacketDataPtr splitMemData;
336 RequestPtr splitMemReq;
341 uint8_t split2ndData;
342 PacketDataPtr split2ndDataPtr;
343 unsigned split2ndFlags;
346 uint64_t *split2ndStoreDataPtr;
349 ////////////////////////////////////////////////////////////
351 // BASE INSTRUCTION INFORMATION.
353 ////////////////////////////////////////////////////////////
354 std::string instName() { return staticInst->getName(); }
357 void setMachInst(ExtMachInst inst);
359 /** Sets the StaticInst. */
360 void setStaticInst(StaticInstPtr &static_inst);
362 /** Sets the sequence number. */
363 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
365 /** Sets the ASID. */
366 void setASID(short addr_space_id) { asid = addr_space_id; }
368 /** Reads the thread id. */
369 short readTid() { return threadNumber; }
371 /** Sets the thread id. */
372 void setTid(ThreadID tid) { threadNumber = tid; }
374 void setVpn(int id) { virtProcNumber = id; }
376 int readVpn() { return virtProcNumber; }
378 /** Sets the pointer to the thread state. */
379 void setThreadState(InOrderThreadState *state) { thread = state; }
381 /** Returns the thread context. */
382 ThreadContext *tcBase() { return thread->getTC(); }
384 /** Returns the fault type. */
385 Fault getFault() { return fault; }
387 ////////////////////////////////////////////////////////////
389 // INSTRUCTION TYPES - Forward checks to StaticInst object.
391 ////////////////////////////////////////////////////////////
392 bool isNop() const { return staticInst->isNop(); }
393 bool isMemRef() const { return staticInst->isMemRef(); }
394 bool isLoad() const { return staticInst->isLoad(); }
395 bool isStore() const { return staticInst->isStore(); }
396 bool isStoreConditional() const
397 { return staticInst->isStoreConditional(); }
398 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
399 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
400 bool isCopy() const { return staticInst->isCopy(); }
401 bool isInteger() const { return staticInst->isInteger(); }
402 bool isFloating() const { return staticInst->isFloating(); }
403 bool isControl() const { return staticInst->isControl(); }
404 bool isCall() const { return staticInst->isCall(); }
405 bool isReturn() const { return staticInst->isReturn(); }
406 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
407 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
408 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
409 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
410 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
412 bool isThreadSync() const { return staticInst->isThreadSync(); }
413 bool isSerializing() const { return staticInst->isSerializing(); }
414 bool isSerializeBefore() const
415 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
416 bool isSerializeAfter() const
417 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
418 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
419 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
420 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
421 bool isQuiesce() const { return staticInst->isQuiesce(); }
422 bool isIprAccess() const { return staticInst->isIprAccess(); }
423 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
425 /////////////////////////////////////////////
427 // RESOURCE SCHEDULING
429 /////////////////////////////////////////////
431 void setNextStage(int stage_num) { nextStage = stage_num; }
432 int getNextStage() { return nextStage; }
434 ThePipeline::InstStage *addStage();
435 ThePipeline::InstStage *addStage(int stage);
436 ThePipeline::InstStage *currentStage() { return currentInstStage; }
439 /** Add A Entry To Reource Schedule */
440 void addToSched(ScheduleEntry* sched_entry)
441 { resSched.push(sched_entry); }
444 /** Print Resource Schedule */
445 /** @NOTE: DEBUG ONLY */
448 ThePipeline::ResSchedule tempSched;
449 std::cerr << "\tInst. Res. Schedule: ";
450 while (!resSched.empty()) {
451 std::cerr << '\t' << resSched.top()->stageNum << "-"
452 << resSched.top()->resNum << ", ";
454 tempSched.push(resSched.top());
458 std::cerr << std::endl;
459 resSched = tempSched;
462 /** Return Next Resource Stage To Be Used */
465 if (resSched.empty())
468 return resSched.top()->stageNum;
472 /** Return Next Resource To Be Used */
475 if (resSched.empty())
478 return resSched.top()->resNum;
481 /** Remove & Deallocate a schedule entry */
484 if (!resSched.empty()) {
485 ScheduleEntry* sked = resSched.top();
494 /** Release a Resource Request (Currently Unused) */
495 void releaseReq(ResourceRequest* req);
497 ////////////////////////////////////////////
499 // INSTRUCTION EXECUTION
501 ////////////////////////////////////////////
502 /** Returns the opclass of this instruction. */
503 OpClass opClass() const { return staticInst->opClass(); }
505 /** Executes the instruction.*/
510 unsigned getCurResSlot() { return curResSlot; }
512 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
514 /** Calls a syscall. */
516 /** Calls hardware return from error interrupt. */
518 /** Traps to handle specified fault. */
519 void trap(Fault fault);
520 bool simPalCheck(int palFunc);
522 /** Calls a syscall. */
523 void syscall(int64_t callnum);
525 void prefetch(Addr addr, unsigned flags);
526 void writeHint(Addr addr, int size, unsigned flags);
527 Fault copySrcTranslate(Addr src);
528 Fault copy(Addr dest);
530 ////////////////////////////////////////////////////////////
532 // MULTITHREADING INTERFACE TO CPU MODELS
534 ////////////////////////////////////////////////////////////
535 virtual void deallocateContext(int thread_num);
537 ////////////////////////////////////////////////////////////
539 // PROGRAM COUNTERS - PC/NPC/NPC
541 ////////////////////////////////////////////////////////////
542 /** Read the PC of this instruction. */
543 const Addr readPC() const { return PC; }
545 /** Sets the PC of this instruction. */
546 void setPC(Addr pc) { PC = pc; }
548 /** Returns the next PC. This could be the speculative next PC if it is
549 * called prior to the actual branch target being calculated.
551 Addr readNextPC() { return nextPC; }
553 /** Set the next PC of this instruction (its actual target). */
554 void setNextPC(uint64_t val) { nextPC = val; }
556 /** Returns the next NPC. This could be the speculative next NPC if it is
557 * called prior to the actual branch target being calculated.
561 #if ISA_HAS_DELAY_SLOT
564 return nextPC + sizeof(TheISA::MachInst);
568 /** Set the next PC of this instruction (its actual target). */
569 void setNextNPC(uint64_t val) { nextNPC = val; }
571 ////////////////////////////////////////////////////////////
575 ////////////////////////////////////////////////////////////
576 /** Set the predicted target of this current instruction. */
577 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
579 /** Returns the predicted target of the branch. */
580 Addr readPredTarg() { return predPC; }
582 /** Returns the predicted PC immediately after the branch. */
583 Addr readPredPC() { return predPC; }
585 /** Returns the predicted PC two instructions after the branch */
586 Addr readPredNPC() { return predNPC; }
588 /** Returns the predicted micro PC after the branch */
589 Addr readPredMicroPC() { return predMicroPC; }
591 /** Returns whether the instruction was predicted taken or not. */
592 bool predTaken() { return predictTaken; }
594 /** Returns whether the instruction mispredicted. */
597 #if ISA_HAS_DELAY_SLOT
598 return predPC != nextNPC;
600 return predPC != nextPC;
604 /** Returns whether the instruction mispredicted. */
605 bool mistargeted() { return predPC != nextNPC; }
607 /** Returns the branch target address. */
608 Addr branchTarget() const { return staticInst->branchTarget(PC); }
610 /** Checks whether or not this instruction has had its branch target
611 * calculated yet. For now it is not utilized and is hacked to be
613 * @todo: Actually use this instruction.
615 bool doneTargCalc() { return false; }
617 void setBranchPred(bool prediction) { predictTaken = prediction; }
623 bool procDelaySlotOnMispred;
625 ////////////////////////////////////////////
629 ////////////////////////////////////////////
631 * Does a read to a given address.
632 * @param addr The address to read.
633 * @param data The read's data is written into this parameter.
634 * @param flags The request's flags.
635 * @return Returns any fault due to the read.
638 Fault read(Addr addr, T &data, unsigned flags);
640 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
643 * Does a write to a given address.
644 * @param data The data to be written.
645 * @param addr The address to write to.
646 * @param flags The request's flags.
647 * @param res The result of the write (for load locked/store conditionals).
648 * @return Returns any fault due to the write.
651 Fault write(T data, Addr addr, unsigned flags,
654 Fault writeBytes(uint8_t *data, unsigned size,
655 Addr addr, unsigned flags, uint64_t *res);
657 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
658 * Access Only valid for memory operations.
662 /** Completes a memory access - Only valid for memory operations. */
663 Fault completeAcc(Packet *pkt);
665 /** Calculates Eff. Addr. part of a memory instruction. */
668 /** Read Effective Address from instruction & do memory access */
671 RequestPtr fetchMemReq;
672 RequestPtr dataMemReq;
677 { return memAddrReady; }
679 void setMemAddr(Addr addr)
680 { memAddr = addr; memAddrReady = true;}
683 { memAddrReady = false;}
688 /** Sets the effective address. */
689 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
691 /** Returns the effective address. */
692 const Addr &getEA() const { return instEffAddr; }
694 /** Returns whether or not the eff. addr. calculation has been completed.*/
695 bool doneEACalc() { return eaCalcDone; }
697 /** Returns whether or not the eff. addr. source registers are ready.
698 * Assume that src registers 1..n-1 are the ones that the
699 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
704 for (int i = 1; i < numSrcRegs(); ++i) {
705 if (!_readySrcRegIdx[i])
712 //////////////////////////////////////////////////
714 // SOURCE-DESTINATION REGISTER INDEXING
716 //////////////////////////////////////////////////
717 /** Returns the number of source registers. */
718 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
720 /** Returns the number of destination registers. */
721 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
723 // the following are used to track physical register usage
724 // for machines with separate int & FP reg files
725 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
726 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
728 /** Returns the logical register index of the i'th destination register. */
729 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
731 /** Returns the logical register index of the i'th source register. */
732 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
734 //////////////////////////////////////////////////
736 // RENAME/PHYSICAL REGISTER FILE SUPPORT
738 //////////////////////////////////////////////////
739 /** Returns the physical register index of the i'th destination
742 PhysRegIndex renamedDestRegIdx(int idx) const
744 return _destRegIdx[idx];
747 /** Returns the physical register index of the i'th source register. */
748 PhysRegIndex renamedSrcRegIdx(int idx) const
750 return _srcRegIdx[idx];
753 /** Returns the physical register index of the previous physical register
754 * that remapped to the same logical register index.
756 PhysRegIndex prevDestRegIdx(int idx) const
758 return _prevDestRegIdx[idx];
761 /** Returns if a source register is ready. */
762 bool isReadySrcRegIdx(int idx) const
764 return this->_readySrcRegIdx[idx];
767 /** Records that one of the source registers is ready. */
768 void markSrcRegReady()
770 if (++readyRegs == numSrcRegs()) {
771 status.set(CanIssue);
775 /** Marks a specific register as ready. */
776 void markSrcRegReady(RegIndex src_idx)
778 _readySrcRegIdx[src_idx] = true;
783 /** Renames a destination register to a physical register. Also records
784 * the previous physical register that the logical register mapped to.
786 void renameDestReg(int idx,
787 PhysRegIndex renamed_dest,
788 PhysRegIndex previous_rename)
790 _destRegIdx[idx] = renamed_dest;
791 _prevDestRegIdx[idx] = previous_rename;
794 /** Renames a source logical register to the physical register which
795 * has/will produce that logical register's result.
796 * @todo: add in whether or not the source register is ready.
798 void renameSrcReg(int idx, PhysRegIndex renamed_src)
800 _srcRegIdx[idx] = renamed_src;
804 PhysRegIndex readDestRegIdx(int idx)
806 return _destRegIdx[idx];
809 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
811 _destRegIdx[idx] = dest_idx;
814 int getDestIdxNum(PhysRegIndex dest_idx)
816 for (int i=0; i < staticInst->numDestRegs(); i++) {
817 if (_destRegIdx[i] == dest_idx)
824 PhysRegIndex readSrcRegIdx(int idx)
826 return _srcRegIdx[idx];
829 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
831 _srcRegIdx[idx] = src_idx;
834 int getSrcIdxNum(PhysRegIndex src_idx)
836 for (int i=0; i < staticInst->numSrcRegs(); i++) {
837 if (_srcRegIdx[i] == src_idx)
844 ////////////////////////////////////////////////////
846 // SOURCE-DESTINATION REGISTER VALUES
848 ////////////////////////////////////////////////////
850 /** Functions that sets an integer or floating point
851 * source register to a value. */
852 void setIntSrc(int idx, uint64_t val);
853 void setFloatSrc(int idx, FloatReg val);
854 void setFloatRegBitsSrc(int idx, uint64_t val);
856 uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
857 uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
859 /** These Instructions read a integer/float/misc. source register
860 * value in the instruction. The instruction's execute function will
861 * call these and it is the interface that is used by the ISA descr.
862 * language (which is why the name isnt readIntSrc(...)) Note: That
863 * the source reg. value is set using the setSrcReg() function.
865 IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
866 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
867 TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
868 MiscReg readMiscReg(int misc_reg);
869 MiscReg readMiscRegNoEffect(int misc_reg);
870 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
871 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
873 /** Returns the result value instruction. */
874 ResultType resultType(int idx)
876 return instResult[idx].type;
879 uint64_t readIntResult(int idx)
881 return instResult[idx].val.integer;
884 /** Depending on type, return Float or Double */
885 double readFloatResult(int idx)
887 return instResult[idx].val.dbl;
890 Tick readResultTime(int idx) { return instResult[idx].tick; }
892 uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
894 /** This is the interface that an instruction will use to write
895 * it's destination register.
897 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
898 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
899 void setFloatRegOperandBits(const StaticInst *si, int idx,
900 TheISA::FloatRegBits val);
901 void setMiscReg(int misc_reg, const MiscReg &val);
902 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
903 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
904 void setMiscRegOperandNoEffect(const StaticInst *si, int idx,
907 virtual uint64_t readRegOtherThread(unsigned idx,
908 ThreadID tid = InvalidThreadID);
909 virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
910 ThreadID tid = InvalidThreadID);
912 /** Sets the number of consecutive store conditional failures. */
913 void setStCondFailures(unsigned sc_failures)
914 { thread->storeCondFailures = sc_failures; }
916 //////////////////////////////////////////////////////////////
918 // INSTRUCTION STATUS FLAGS (READ/SET)
920 //////////////////////////////////////////////////////////////
921 /** Sets this instruction as entered on the CPU Reg Dep Map */
922 void setRegDepEntry() { status.set(RegDepMapEntry); }
924 /** Returns whether or not the entry is on the CPU Reg Dep Map */
925 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
927 /** Sets this instruction as entered on the CPU Reg Dep Map */
928 void setRemoveList() { status.set(RemoveList); }
930 /** Returns whether or not the entry is on the CPU Reg Dep Map */
931 bool isRemoveList() const { return status[RemoveList]; }
933 /** Sets this instruction as completed. */
934 void setCompleted() { status.set(Completed); }
936 /** Returns whether or not this instruction is completed. */
937 bool isCompleted() const { return status[Completed]; }
939 /** Marks the result as ready. */
940 void setResultReady() { status.set(ResultReady); }
942 /** Returns whether or not the result is ready. */
943 bool isResultReady() const { return status[ResultReady]; }
945 /** Sets this instruction as ready to issue. */
946 void setCanIssue() { status.set(CanIssue); }
948 /** Returns whether or not this instruction is ready to issue. */
949 bool readyToIssue() const { return status[CanIssue]; }
951 /** Sets this instruction as issued from the IQ. */
952 void setIssued() { status.set(Issued); }
954 /** Returns whether or not this instruction has issued. */
955 bool isIssued() const { return status[Issued]; }
957 /** Sets this instruction as executed. */
958 void setExecuted() { status.set(Executed); }
960 /** Returns whether or not this instruction has executed. */
961 bool isExecuted() const { return status[Executed]; }
963 /** Sets this instruction as ready to commit. */
964 void setCanCommit() { status.set(CanCommit); }
966 /** Clears this instruction as being ready to commit. */
967 void clearCanCommit() { status.reset(CanCommit); }
969 /** Returns whether or not this instruction is ready to commit. */
970 bool readyToCommit() const { return status[CanCommit]; }
972 void setAtCommit() { status.set(AtCommit); }
974 bool isAtCommit() { return status[AtCommit]; }
976 /** Sets this instruction as committed. */
977 void setCommitted() { status.set(Committed); }
979 /** Returns whether or not this instruction is committed. */
980 bool isCommitted() const { return status[Committed]; }
982 /** Sets this instruction as squashed. */
983 void setSquashed() { status.set(Squashed); }
985 /** Returns whether or not this instruction is squashed. */
986 bool isSquashed() const { return status[Squashed]; }
988 /** Temporarily sets this instruction as a serialize before instruction. */
989 void setSerializeBefore() { status.set(SerializeBefore); }
991 /** Clears the serializeBefore part of this instruction. */
992 void clearSerializeBefore() { status.reset(SerializeBefore); }
994 /** Checks if this serializeBefore is only temporarily set. */
995 bool isTempSerializeBefore() { return status[SerializeBefore]; }
997 /** Temporarily sets this instruction as a serialize after instruction. */
998 void setSerializeAfter() { status.set(SerializeAfter); }
1000 /** Clears the serializeAfter part of this instruction.*/
1001 void clearSerializeAfter() { status.reset(SerializeAfter); }
1003 /** Checks if this serializeAfter is only temporarily set. */
1004 bool isTempSerializeAfter() { return status[SerializeAfter]; }
1006 /** Sets the serialization part of this instruction as handled. */
1007 void setSerializeHandled() { status.set(SerializeHandled); }
1009 /** Checks if the serialization part of this instruction has been
1010 * handled. This does not apply to the temporary serializing
1011 * state; it only applies to this instruction's own permanent
1012 * serializing state.
1014 bool isSerializeHandled() { return status[SerializeHandled]; }
1017 /** Instruction effective address.
1018 * @todo: Consider if this is necessary or not.
1022 /** Whether or not the effective address calculation is completed.
1023 * @todo: Consider if this is necessary or not.
1028 /** Whether or not the memory operation is done. */
1032 /** Load queue index. */
1035 /** Store queue index. */
1038 /** Iterator pointing to this BaseDynInst in the list of all insts. */
1041 /** Returns iterator to this instruction in the list of all insts. */
1042 ListIt &getInstListIt() { return instListIt; }
1044 /** Sets iterator for this instruction in the list of all insts. */
1045 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
1047 /** Count of total number of dynamic instructions. */
1048 static int instcount;
1050 void resetInstCount();
1052 /** Dumps out contents of this BaseDynInst. */
1055 /** Dumps out contents of this BaseDynInst into given string. */
1056 void dump(std::string &outstring);
1058 //inline int curCount() { return curCount(); }
1062 #endif // __CPU_BASE_DYN_INST_HH__