2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/faults.hh"
41 #include "arch/isa_traits.hh"
43 #include "arch/types.hh"
44 #include "base/fast_alloc.hh"
45 #include "base/trace.hh"
46 #include "base/types.hh"
47 #include "config/full_system.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/exetrace.hh"
50 #include "cpu/inorder/inorder_trace.hh"
51 #include "cpu/inorder/pipeline_traits.hh"
52 #include "cpu/inorder/resource.hh"
53 #include "cpu/inorder/thread_state.hh"
54 #include "cpu/inst_seq.hh"
55 #include "cpu/op_class.hh"
56 #include "cpu/static_inst.hh"
57 #include "cpu/thread_context.hh"
58 #include "mem/packet.hh"
59 #include "sim/system.hh"
61 #if THE_ISA == ALPHA_ISA
62 #include "arch/alpha/ev5.hh"
67 * Defines a dynamic instruction context for a inorder CPU model.
70 // Forward declaration.
72 class ResourceRequest;
75 class InOrderDynInst : public FastAlloc, public RefCounted
78 // Binary machine instruction type.
79 typedef TheISA::MachInst MachInst;
80 // Extended machine instruction type
81 typedef TheISA::ExtMachInst ExtMachInst;
82 // Logical register index type.
83 typedef TheISA::RegIndex RegIndex;
84 // Integer register type.
85 typedef TheISA::IntReg IntReg;
86 // Floating point register type.
87 typedef TheISA::FloatReg FloatReg;
88 // Floating point register type.
89 typedef TheISA::MiscReg MiscReg;
91 typedef short int PhysRegIndex;
93 /** The refcounted DynInst pointer to be used. In most cases this is
94 * what should be used, and not DynInst*.
96 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
98 // The list of instructions iterator type.
99 typedef std::list<DynInstPtr>::iterator ListIt;
102 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
103 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
107 /** BaseDynInst constructor given a binary instruction.
108 * @param inst The binary instruction.
109 * @param PC The PC of the instruction.
110 * @param pred_PC The predicted next PC.
111 * @param seq_num The sequence number of the instruction.
112 * @param cpu Pointer to the instruction's CPU.
114 InOrderDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
117 /** BaseDynInst constructor given a binary instruction.
118 * @param seq_num The sequence number of the instruction.
119 * @param cpu Pointer to the instruction's CPU.
120 * NOTE: Must set Binary Instrution through Member Function
122 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
123 InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
125 /** BaseDynInst constructor given a StaticInst pointer.
126 * @param _staticInst The StaticInst for this BaseDynInst.
128 InOrderDynInst(StaticInstPtr &_staticInst);
130 /** Skeleton Constructor. */
133 /** InOrderDynInst destructor. */
137 /** The sequence number of the instruction. */
140 /** The sequence number of the instruction. */
141 InstSeqNum bdelaySeqNum;
144 RegDepMapEntry, /// Instruction is entered onto the RegDepMap
145 IqEntry, /// Instruction is in the IQ
146 RobEntry, /// Instruction is in the ROB
147 LsqEntry, /// Instruction is in the LSQ
148 Completed, /// Instruction has completed
149 ResultReady, /// Instruction has its result
150 CanIssue, /// Instruction can issue and execute
151 Issued, /// Instruction has issued
152 Executed, /// Instruction has executed
153 CanCommit, /// Instruction can commit
154 AtCommit, /// Instruction has reached commit
155 Committed, /// Instruction has committed
156 Squashed, /// Instruction is squashed
157 SquashedInIQ, /// Instruction is squashed in the IQ
158 SquashedInLSQ, /// Instruction is squashed in the LSQ
159 SquashedInROB, /// Instruction is squashed in the ROB
160 RecoverInst, /// Is a recover instruction
161 BlockingInst, /// Is a blocking instruction
162 ThreadsyncWait, /// Is a thread synchronization instruction
163 SerializeBefore, /// Needs to serialize on
164 /// instructions ahead of it
165 SerializeAfter, /// Needs to serialize instructions behind it
166 SerializeHandled, /// Serialization has been handled
167 RemoveList, /// Is Instruction on Remove List?
171 /** The status of this BaseDynInst. Several bits can be set. */
172 std::bitset<NumStatus> status;
174 /** The thread this instruction is from. */
177 /** data address space ID, for loads & stores. */
180 /** The virtual processor number */
181 short virtProcNumber;
183 /** The StaticInst used by this BaseDynInst. */
184 StaticInstPtr staticInst;
186 /** InstRecord that tracks this instructions. */
187 Trace::InOrderTraceRecord *traceData;
189 /** Pointer to the Impl's CPU object. */
192 /** Pointer to the thread state. */
193 InOrderThreadState *thread;
195 /** The kind of fault this instruction has generated. */
198 /** The memory request. */
201 /** Pointer to the data for the memory access. */
204 /** Data used for a store for operation. */
207 /** Data used for a store for operation. */
210 /** The resource schedule for this inst */
211 ThePipeline::ResSchedule resSched;
213 /** List of active resource requests for this instruction */
214 std::list<ResourceRequest*> reqList;
216 /** The effective virtual address (lds & stores only). */
219 /** The effective physical address. */
222 /** Effective virtual address for a copy source. */
225 /** Effective physical address for a copy source. */
226 Addr copySrcPhysEffAddr;
228 /** The memory request flags (from translation). */
229 unsigned memReqFlags;
231 /** How many source registers are ready. */
234 /** An instruction src/dest has to be one of these types */
240 //@TODO: Naming Convention for Enums?
249 /** Result of an instruction execution */
256 : type(None), tick(0)
260 /** The source of the instruction; assumes for now that there's only one
261 * destination register.
263 InstValue instSrc[MaxInstSrcRegs];
265 /** The result of the instruction; assumes for now that there's only one
266 * destination register.
268 InstResult instResult[MaxInstDestRegs];
270 /** PC of this instruction. */
273 /** Next non-speculative PC. It is not filled in at fetch, but rather
274 * once the target of the branch is truly known (either decode or
279 /** Next next non-speculative PC. It is not filled in at fetch, but rather
280 * once the target of the branch is truly known (either decode or
285 /** Predicted next PC. */
288 /** Predicted next NPC. */
291 /** Predicted next microPC */
294 /** Address to fetch from */
297 /** Address to get/write data from/to */
300 /** Whether or not the source register is ready.
301 * @todo: Not sure this should be here vs the derived class.
303 bool _readySrcRegIdx[MaxInstSrcRegs];
305 /** Physical register index of the destination registers of this
308 PhysRegIndex _destRegIdx[MaxInstDestRegs];
310 /** Physical register index of the source registers of this
313 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
315 /** Physical register index of the previous producers of the
316 * architected destinations.
318 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
322 /* vars to keep track of InstStage's - used for resource sched defn */
323 int nextInstStageNum;
324 ThePipeline::InstStage *currentInstStage;
325 std::list<ThePipeline::InstStage*> instStageList;
328 /** Function to initialize variables in the constructors. */
334 PacketDataPtr splitMemData;
335 RequestPtr splitMemReq;
340 uint8_t split2ndData;
341 PacketDataPtr split2ndDataPtr;
342 unsigned split2ndFlags;
345 uint64_t *split2ndStoreDataPtr;
348 ////////////////////////////////////////////////////////////
350 // BASE INSTRUCTION INFORMATION.
352 ////////////////////////////////////////////////////////////
353 std::string instName() { return staticInst->getName(); }
356 void setMachInst(ExtMachInst inst);
358 /** Sets the StaticInst. */
359 void setStaticInst(StaticInstPtr &static_inst);
361 /** Sets the sequence number. */
362 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
364 /** Sets the ASID. */
365 void setASID(short addr_space_id) { asid = addr_space_id; }
367 /** Reads the thread id. */
368 short readTid() { return threadNumber; }
370 /** Sets the thread id. */
371 void setTid(ThreadID tid) { threadNumber = tid; }
373 void setVpn(int id) { virtProcNumber = id; }
375 int readVpn() { return virtProcNumber; }
377 /** Sets the pointer to the thread state. */
378 void setThreadState(InOrderThreadState *state) { thread = state; }
380 /** Returns the thread context. */
381 ThreadContext *tcBase() { return thread->getTC(); }
383 /** Returns the fault type. */
384 Fault getFault() { return fault; }
386 ////////////////////////////////////////////////////////////
388 // INSTRUCTION TYPES - Forward checks to StaticInst object.
390 ////////////////////////////////////////////////////////////
391 bool isNop() const { return staticInst->isNop(); }
392 bool isMemRef() const { return staticInst->isMemRef(); }
393 bool isLoad() const { return staticInst->isLoad(); }
394 bool isStore() const { return staticInst->isStore(); }
395 bool isStoreConditional() const
396 { return staticInst->isStoreConditional(); }
397 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
398 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
399 bool isCopy() const { return staticInst->isCopy(); }
400 bool isInteger() const { return staticInst->isInteger(); }
401 bool isFloating() const { return staticInst->isFloating(); }
402 bool isControl() const { return staticInst->isControl(); }
403 bool isCall() const { return staticInst->isCall(); }
404 bool isReturn() const { return staticInst->isReturn(); }
405 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
406 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
407 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
408 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
409 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
411 bool isThreadSync() const { return staticInst->isThreadSync(); }
412 bool isSerializing() const { return staticInst->isSerializing(); }
413 bool isSerializeBefore() const
414 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
415 bool isSerializeAfter() const
416 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
417 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
418 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
419 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
420 bool isQuiesce() const { return staticInst->isQuiesce(); }
421 bool isIprAccess() const { return staticInst->isIprAccess(); }
422 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
424 /////////////////////////////////////////////
426 // RESOURCE SCHEDULING
428 /////////////////////////////////////////////
430 void setNextStage(int stage_num) { nextStage = stage_num; }
431 int getNextStage() { return nextStage; }
433 ThePipeline::InstStage *addStage();
434 ThePipeline::InstStage *addStage(int stage);
435 ThePipeline::InstStage *currentStage() { return currentInstStage; }
438 /** Add A Entry To Reource Schedule */
439 void addToSched(ThePipeline::ScheduleEntry* sched_entry)
440 { resSched.push(sched_entry); }
443 /** Print Resource Schedule */
444 /** @NOTE: DEBUG ONLY */
447 ThePipeline::ResSchedule tempSched;
448 std::cerr << "\tInst. Res. Schedule: ";
449 while (!resSched.empty()) {
450 std::cerr << '\t' << resSched.top()->stageNum << "-"
451 << resSched.top()->resNum << ", ";
453 tempSched.push(resSched.top());
457 std::cerr << std::endl;
458 resSched = tempSched;
461 /** Return Next Resource Stage To Be Used */
464 if (resSched.empty())
467 return resSched.top()->stageNum;
471 /** Return Next Resource To Be Used */
474 if (resSched.empty())
477 return resSched.top()->resNum;
480 /** Remove & Deallocate a schedule entry */
483 if (!resSched.empty()) {
484 ThePipeline::ScheduleEntry* sked = resSched.top();
493 /** Release a Resource Request (Currently Unused) */
494 void releaseReq(ResourceRequest* req);
496 ////////////////////////////////////////////
498 // INSTRUCTION EXECUTION
500 ////////////////////////////////////////////
501 /** Returns the opclass of this instruction. */
502 OpClass opClass() const { return staticInst->opClass(); }
504 /** Executes the instruction.*/
509 unsigned getCurResSlot() { return curResSlot; }
511 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
513 /** Calls a syscall. */
515 /** Calls hardware return from error interrupt. */
517 /** Traps to handle specified fault. */
518 void trap(Fault fault);
519 bool simPalCheck(int palFunc);
521 /** Calls a syscall. */
522 void syscall(int64_t callnum);
524 void prefetch(Addr addr, unsigned flags);
525 void writeHint(Addr addr, int size, unsigned flags);
526 Fault copySrcTranslate(Addr src);
527 Fault copy(Addr dest);
529 ////////////////////////////////////////////////////////////
531 // MULTITHREADING INTERFACE TO CPU MODELS
533 ////////////////////////////////////////////////////////////
534 virtual void deallocateContext(int thread_num);
536 ////////////////////////////////////////////////////////////
538 // PROGRAM COUNTERS - PC/NPC/NPC
540 ////////////////////////////////////////////////////////////
541 /** Read the PC of this instruction. */
542 const Addr readPC() const { return PC; }
544 /** Sets the PC of this instruction. */
545 void setPC(Addr pc) { PC = pc; }
547 /** Returns the next PC. This could be the speculative next PC if it is
548 * called prior to the actual branch target being calculated.
550 Addr readNextPC() { return nextPC; }
552 /** Set the next PC of this instruction (its actual target). */
553 void setNextPC(uint64_t val) { nextPC = val; }
555 /** Returns the next NPC. This could be the speculative next NPC if it is
556 * called prior to the actual branch target being calculated.
560 #if ISA_HAS_DELAY_SLOT
563 return nextPC + sizeof(TheISA::MachInst);
567 /** Set the next PC of this instruction (its actual target). */
568 void setNextNPC(uint64_t val) { nextNPC = val; }
570 ////////////////////////////////////////////////////////////
574 ////////////////////////////////////////////////////////////
575 /** Set the predicted target of this current instruction. */
576 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
578 /** Returns the predicted target of the branch. */
579 Addr readPredTarg() { return predPC; }
581 /** Returns the predicted PC immediately after the branch. */
582 Addr readPredPC() { return predPC; }
584 /** Returns the predicted PC two instructions after the branch */
585 Addr readPredNPC() { return predNPC; }
587 /** Returns the predicted micro PC after the branch */
588 Addr readPredMicroPC() { return predMicroPC; }
590 /** Returns whether the instruction was predicted taken or not. */
591 bool predTaken() { return predictTaken; }
593 /** Returns whether the instruction mispredicted. */
596 #if ISA_HAS_DELAY_SLOT
597 return predPC != nextNPC;
599 return predPC != nextPC;
603 /** Returns whether the instruction mispredicted. */
604 bool mistargeted() { return predPC != nextNPC; }
606 /** Returns the branch target address. */
607 Addr branchTarget() const { return staticInst->branchTarget(PC); }
609 /** Checks whether or not this instruction has had its branch target
610 * calculated yet. For now it is not utilized and is hacked to be
612 * @todo: Actually use this instruction.
614 bool doneTargCalc() { return false; }
616 void setBranchPred(bool prediction) { predictTaken = prediction; }
622 bool procDelaySlotOnMispred;
624 ////////////////////////////////////////////
628 ////////////////////////////////////////////
630 * Does a read to a given address.
631 * @param addr The address to read.
632 * @param data The read's data is written into this parameter.
633 * @param flags The request's flags.
634 * @return Returns any fault due to the read.
637 Fault read(Addr addr, T &data, unsigned flags);
640 * Does a write to a given address.
641 * @param data The data to be written.
642 * @param addr The address to write to.
643 * @param flags The request's flags.
644 * @param res The result of the write (for load locked/store conditionals).
645 * @return Returns any fault due to the write.
648 Fault write(T data, Addr addr, unsigned flags,
651 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
652 * Access Only valid for memory operations.
656 /** Completes a memory access - Only valid for memory operations. */
657 Fault completeAcc(Packet *pkt);
659 /** Calculates Eff. Addr. part of a memory instruction. */
662 /** Read Effective Address from instruction & do memory access */
665 RequestPtr fetchMemReq;
666 RequestPtr dataMemReq;
671 { return memAddrReady; }
673 void setMemAddr(Addr addr)
674 { memAddr = addr; memAddrReady = true;}
677 { memAddrReady = false;}
682 /** Sets the effective address. */
683 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
685 /** Returns the effective address. */
686 const Addr &getEA() const { return instEffAddr; }
688 /** Returns whether or not the eff. addr. calculation has been completed.*/
689 bool doneEACalc() { return eaCalcDone; }
691 /** Returns whether or not the eff. addr. source registers are ready.
692 * Assume that src registers 1..n-1 are the ones that the
693 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
698 for (int i = 1; i < numSrcRegs(); ++i) {
699 if (!_readySrcRegIdx[i])
706 //////////////////////////////////////////////////
708 // SOURCE-DESTINATION REGISTER INDEXING
710 //////////////////////////////////////////////////
711 /** Returns the number of source registers. */
712 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
714 /** Returns the number of destination registers. */
715 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
717 // the following are used to track physical register usage
718 // for machines with separate int & FP reg files
719 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
720 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
722 /** Returns the logical register index of the i'th destination register. */
723 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
725 /** Returns the logical register index of the i'th source register. */
726 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
728 //////////////////////////////////////////////////
730 // RENAME/PHYSICAL REGISTER FILE SUPPORT
732 //////////////////////////////////////////////////
733 /** Returns the physical register index of the i'th destination
736 PhysRegIndex renamedDestRegIdx(int idx) const
738 return _destRegIdx[idx];
741 /** Returns the physical register index of the i'th source register. */
742 PhysRegIndex renamedSrcRegIdx(int idx) const
744 return _srcRegIdx[idx];
747 /** Returns the physical register index of the previous physical register
748 * that remapped to the same logical register index.
750 PhysRegIndex prevDestRegIdx(int idx) const
752 return _prevDestRegIdx[idx];
755 /** Returns if a source register is ready. */
756 bool isReadySrcRegIdx(int idx) const
758 return this->_readySrcRegIdx[idx];
761 /** Records that one of the source registers is ready. */
762 void markSrcRegReady()
764 if (++readyRegs == numSrcRegs()) {
765 status.set(CanIssue);
769 /** Marks a specific register as ready. */
770 void markSrcRegReady(RegIndex src_idx)
772 _readySrcRegIdx[src_idx] = true;
777 /** Renames a destination register to a physical register. Also records
778 * the previous physical register that the logical register mapped to.
780 void renameDestReg(int idx,
781 PhysRegIndex renamed_dest,
782 PhysRegIndex previous_rename)
784 _destRegIdx[idx] = renamed_dest;
785 _prevDestRegIdx[idx] = previous_rename;
788 /** Renames a source logical register to the physical register which
789 * has/will produce that logical register's result.
790 * @todo: add in whether or not the source register is ready.
792 void renameSrcReg(int idx, PhysRegIndex renamed_src)
794 _srcRegIdx[idx] = renamed_src;
798 PhysRegIndex readDestRegIdx(int idx)
800 return _destRegIdx[idx];
803 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
805 _destRegIdx[idx] = dest_idx;
808 int getDestIdxNum(PhysRegIndex dest_idx)
810 for (int i=0; i < staticInst->numDestRegs(); i++) {
811 if (_destRegIdx[i] == dest_idx)
818 PhysRegIndex readSrcRegIdx(int idx)
820 return _srcRegIdx[idx];
823 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
825 _srcRegIdx[idx] = src_idx;
828 int getSrcIdxNum(PhysRegIndex src_idx)
830 for (int i=0; i < staticInst->numSrcRegs(); i++) {
831 if (_srcRegIdx[i] == src_idx)
838 ////////////////////////////////////////////////////
840 // SOURCE-DESTINATION REGISTER VALUES
842 ////////////////////////////////////////////////////
844 /** Functions that sets an integer or floating point
845 * source register to a value. */
846 void setIntSrc(int idx, uint64_t val);
847 void setFloatSrc(int idx, FloatReg val);
848 void setFloatRegBitsSrc(int idx, uint64_t val);
850 uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
851 uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
853 /** These Instructions read a integer/float/misc. source register
854 * value in the instruction. The instruction's execute function will
855 * call these and it is the interface that is used by the ISA descr.
856 * language (which is why the name isnt readIntSrc(...)) Note: That
857 * the source reg. value is set using the setSrcReg() function.
859 IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
860 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
861 TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
862 MiscReg readMiscReg(int misc_reg);
863 MiscReg readMiscRegNoEffect(int misc_reg);
864 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
865 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
867 /** Returns the result value instruction. */
868 ResultType resultType(int idx)
870 return instResult[idx].type;
873 uint64_t readIntResult(int idx)
875 return instResult[idx].val.integer;
878 /** Depending on type, return Float or Double */
879 double readFloatResult(int idx)
881 return instResult[idx].val.dbl;
884 Tick readResultTime(int idx) { return instResult[idx].tick; }
886 uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
888 /** This is the interface that an instruction will use to write
889 * it's destination register.
891 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
892 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
893 void setFloatRegOperandBits(const StaticInst *si, int idx,
894 TheISA::FloatRegBits val);
895 void setMiscReg(int misc_reg, const MiscReg &val);
896 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
897 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
898 void setMiscRegOperandNoEffect(const StaticInst *si, int idx,
901 virtual uint64_t readRegOtherThread(unsigned idx,
902 ThreadID tid = InvalidThreadID);
903 virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
904 ThreadID tid = InvalidThreadID);
906 /** Sets the number of consecutive store conditional failures. */
907 void setStCondFailures(unsigned sc_failures)
908 { thread->storeCondFailures = sc_failures; }
910 //////////////////////////////////////////////////////////////
912 // INSTRUCTION STATUS FLAGS (READ/SET)
914 //////////////////////////////////////////////////////////////
915 /** Sets this instruction as entered on the CPU Reg Dep Map */
916 void setRegDepEntry() { status.set(RegDepMapEntry); }
918 /** Returns whether or not the entry is on the CPU Reg Dep Map */
919 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
921 /** Sets this instruction as entered on the CPU Reg Dep Map */
922 void setRemoveList() { status.set(RemoveList); }
924 /** Returns whether or not the entry is on the CPU Reg Dep Map */
925 bool isRemoveList() const { return status[RemoveList]; }
927 /** Sets this instruction as completed. */
928 void setCompleted() { status.set(Completed); }
930 /** Returns whether or not this instruction is completed. */
931 bool isCompleted() const { return status[Completed]; }
933 /** Marks the result as ready. */
934 void setResultReady() { status.set(ResultReady); }
936 /** Returns whether or not the result is ready. */
937 bool isResultReady() const { return status[ResultReady]; }
939 /** Sets this instruction as ready to issue. */
940 void setCanIssue() { status.set(CanIssue); }
942 /** Returns whether or not this instruction is ready to issue. */
943 bool readyToIssue() const { return status[CanIssue]; }
945 /** Sets this instruction as issued from the IQ. */
946 void setIssued() { status.set(Issued); }
948 /** Returns whether or not this instruction has issued. */
949 bool isIssued() const { return status[Issued]; }
951 /** Sets this instruction as executed. */
952 void setExecuted() { status.set(Executed); }
954 /** Returns whether or not this instruction has executed. */
955 bool isExecuted() const { return status[Executed]; }
957 /** Sets this instruction as ready to commit. */
958 void setCanCommit() { status.set(CanCommit); }
960 /** Clears this instruction as being ready to commit. */
961 void clearCanCommit() { status.reset(CanCommit); }
963 /** Returns whether or not this instruction is ready to commit. */
964 bool readyToCommit() const { return status[CanCommit]; }
966 void setAtCommit() { status.set(AtCommit); }
968 bool isAtCommit() { return status[AtCommit]; }
970 /** Sets this instruction as committed. */
971 void setCommitted() { status.set(Committed); }
973 /** Returns whether or not this instruction is committed. */
974 bool isCommitted() const { return status[Committed]; }
976 /** Sets this instruction as squashed. */
977 void setSquashed() { status.set(Squashed); }
979 /** Returns whether or not this instruction is squashed. */
980 bool isSquashed() const { return status[Squashed]; }
982 /** Temporarily sets this instruction as a serialize before instruction. */
983 void setSerializeBefore() { status.set(SerializeBefore); }
985 /** Clears the serializeBefore part of this instruction. */
986 void clearSerializeBefore() { status.reset(SerializeBefore); }
988 /** Checks if this serializeBefore is only temporarily set. */
989 bool isTempSerializeBefore() { return status[SerializeBefore]; }
991 /** Temporarily sets this instruction as a serialize after instruction. */
992 void setSerializeAfter() { status.set(SerializeAfter); }
994 /** Clears the serializeAfter part of this instruction.*/
995 void clearSerializeAfter() { status.reset(SerializeAfter); }
997 /** Checks if this serializeAfter is only temporarily set. */
998 bool isTempSerializeAfter() { return status[SerializeAfter]; }
1000 /** Sets the serialization part of this instruction as handled. */
1001 void setSerializeHandled() { status.set(SerializeHandled); }
1003 /** Checks if the serialization part of this instruction has been
1004 * handled. This does not apply to the temporary serializing
1005 * state; it only applies to this instruction's own permanent
1006 * serializing state.
1008 bool isSerializeHandled() { return status[SerializeHandled]; }
1011 /** Instruction effective address.
1012 * @todo: Consider if this is necessary or not.
1016 /** Whether or not the effective address calculation is completed.
1017 * @todo: Consider if this is necessary or not.
1022 /** Whether or not the memory operation is done. */
1026 /** Load queue index. */
1029 /** Store queue index. */
1032 /** Iterator pointing to this BaseDynInst in the list of all insts. */
1035 /** Returns iterator to this instruction in the list of all insts. */
1036 ListIt &getInstListIt() { return instListIt; }
1038 /** Sets iterator for this instruction in the list of all insts. */
1039 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
1041 /** Count of total number of dynamic instructions. */
1042 static int instcount;
1044 void resetInstCount();
1046 /** Dumps out contents of this BaseDynInst. */
1049 /** Dumps out contents of this BaseDynInst into given string. */
1050 void dump(std::string &outstring);
1052 //inline int curCount() { return curCount(); }
1056 #endif // __CPU_BASE_DYN_INST_HH__