2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/faults.hh"
41 #include "arch/isa_traits.hh"
43 #include "arch/types.hh"
44 #include "arch/utility.hh"
45 #include "base/fast_alloc.hh"
46 #include "base/trace.hh"
47 #include "base/types.hh"
48 #include "config/full_system.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/exetrace.hh"
51 #include "cpu/inorder/inorder_trace.hh"
52 #include "cpu/inorder/pipeline_traits.hh"
53 #include "cpu/inorder/resource.hh"
54 #include "cpu/inorder/resource_sked.hh"
55 #include "cpu/inorder/thread_state.hh"
56 #include "cpu/inst_seq.hh"
57 #include "cpu/op_class.hh"
58 #include "cpu/static_inst.hh"
59 #include "cpu/thread_context.hh"
60 #include "mem/packet.hh"
61 #include "sim/system.hh"
63 #if THE_ISA == ALPHA_ISA
64 #include "arch/alpha/ev5.hh"
69 * Defines a dynamic instruction context for a inorder CPU model.
72 // Forward declaration.
74 class ResourceRequest;
77 class InOrderDynInst : public FastAlloc, public RefCounted
80 // Binary machine instruction type.
81 typedef TheISA::MachInst MachInst;
82 // Extended machine instruction type
83 typedef TheISA::ExtMachInst ExtMachInst;
84 // Logical register index type.
85 typedef TheISA::RegIndex RegIndex;
86 // Integer register type.
87 typedef TheISA::IntReg IntReg;
88 // Floating point register type.
89 typedef TheISA::FloatReg FloatReg;
90 // Floating point register type.
91 typedef TheISA::MiscReg MiscReg;
93 typedef short int PhysRegIndex;
95 /** The refcounted DynInst pointer to be used. In most cases this is
96 * what should be used, and not DynInst*.
98 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
100 // The list of instructions iterator type.
101 typedef std::list<DynInstPtr>::iterator ListIt;
104 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
105 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
109 /** BaseDynInst constructor given a binary instruction.
110 * @param inst The binary instruction.
111 * @param PC The PC of the instruction.
112 * @param predPC The predicted next PC.
113 * @param seq_num The sequence number of the instruction.
114 * @param cpu Pointer to the instruction's CPU.
116 InOrderDynInst(ExtMachInst inst, const TheISA::PCState &PC,
117 const TheISA::PCState &predPC, InstSeqNum seq_num,
120 /** BaseDynInst constructor given a binary instruction.
121 * @param seq_num The sequence number of the instruction.
122 * @param cpu Pointer to the instruction's CPU.
123 * NOTE: Must set Binary Instrution through Member Function
125 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
126 InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
128 /** BaseDynInst constructor given a StaticInst pointer.
129 * @param _staticInst The StaticInst for this BaseDynInst.
131 InOrderDynInst(StaticInstPtr &_staticInst);
133 /** Skeleton Constructor. */
136 /** InOrderDynInst destructor. */
140 /** The sequence number of the instruction. */
143 /** The sequence number of the instruction. */
144 InstSeqNum bdelaySeqNum;
147 RegDepMapEntry, /// Instruction is entered onto the RegDepMap
148 IqEntry, /// Instruction is in the IQ
149 RobEntry, /// Instruction is in the ROB
150 LsqEntry, /// Instruction is in the LSQ
151 Completed, /// Instruction has completed
152 ResultReady, /// Instruction has its result
153 CanIssue, /// Instruction can issue and execute
154 Issued, /// Instruction has issued
155 Executed, /// Instruction has executed
156 CanCommit, /// Instruction can commit
157 AtCommit, /// Instruction has reached commit
158 Committed, /// Instruction has committed
159 Squashed, /// Instruction is squashed
160 SquashedInIQ, /// Instruction is squashed in the IQ
161 SquashedInLSQ, /// Instruction is squashed in the LSQ
162 SquashedInROB, /// Instruction is squashed in the ROB
163 RecoverInst, /// Is a recover instruction
164 BlockingInst, /// Is a blocking instruction
165 ThreadsyncWait, /// Is a thread synchronization instruction
166 SerializeBefore, /// Needs to serialize on
167 /// instructions ahead of it
168 SerializeAfter, /// Needs to serialize instructions behind it
169 SerializeHandled, /// Serialization has been handled
170 RemoveList, /// Is Instruction on Remove List?
174 /** The status of this BaseDynInst. Several bits can be set. */
175 std::bitset<NumStatus> status;
177 /** The thread this instruction is from. */
180 /** data address space ID, for loads & stores. */
183 /** The virtual processor number */
184 short virtProcNumber;
186 /** The StaticInst used by this BaseDynInst. */
187 StaticInstPtr staticInst;
189 /** InstRecord that tracks this instructions. */
190 Trace::InOrderTraceRecord *traceData;
192 /** Pointer to the Impl's CPU object. */
195 /** Pointer to the thread state. */
196 InOrderThreadState *thread;
198 /** The kind of fault this instruction has generated. */
201 /** The memory request. */
204 /** Pointer to the data for the memory access. */
207 /** Data used for a store for operation. */
210 /** Data used for a store for operation. */
213 /** The resource schedule for this inst */
214 ThePipeline::ResSchedule resSched;
216 /** List of active resource requests for this instruction */
217 std::list<ResourceRequest*> reqList;
219 /** The effective virtual address (lds & stores only). */
222 /** The effective physical address. */
225 /** Effective virtual address for a copy source. */
228 /** Effective physical address for a copy source. */
229 Addr copySrcPhysEffAddr;
231 /** The memory request flags (from translation). */
232 unsigned memReqFlags;
234 /** How many source registers are ready. */
237 /** An instruction src/dest has to be one of these types */
243 //@TODO: Naming Convention for Enums?
252 /** Result of an instruction execution */
259 : type(None), tick(0)
263 /** The source of the instruction; assumes for now that there's only one
264 * destination register.
266 InstValue instSrc[MaxInstSrcRegs];
268 /** The result of the instruction; assumes for now that there's only one
269 * destination register.
271 InstResult instResult[MaxInstDestRegs];
273 /** PC of this instruction. */
276 /** Predicted next PC. */
277 TheISA::PCState predPC;
279 /** Address to fetch from */
282 /** Address to get/write data from/to */
285 /** Whether or not the source register is ready.
286 * @todo: Not sure this should be here vs the derived class.
288 bool _readySrcRegIdx[MaxInstSrcRegs];
290 /** Physical register index of the destination registers of this
293 PhysRegIndex _destRegIdx[MaxInstDestRegs];
295 /** Physical register index of the source registers of this
298 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
300 /** Physical register index of the previous producers of the
301 * architected destinations.
303 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
307 /* vars to keep track of InstStage's - used for resource sched defn */
308 int nextInstStageNum;
309 ThePipeline::InstStage *currentInstStage;
310 std::list<ThePipeline::InstStage*> instStageList;
313 /** Function to initialize variables in the constructors. */
319 PacketDataPtr splitMemData;
320 RequestPtr splitMemReq;
325 uint8_t split2ndData;
326 PacketDataPtr split2ndDataPtr;
327 unsigned split2ndFlags;
330 uint64_t *split2ndStoreDataPtr;
333 ////////////////////////////////////////////////////////////
335 // BASE INSTRUCTION INFORMATION.
337 ////////////////////////////////////////////////////////////
338 std::string instName() { return staticInst->getName(); }
341 void setMachInst(ExtMachInst inst);
343 /** Sets the StaticInst. */
344 void setStaticInst(StaticInstPtr &static_inst);
346 /** Sets the sequence number. */
347 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
349 /** Sets the ASID. */
350 void setASID(short addr_space_id) { asid = addr_space_id; }
352 /** Reads the thread id. */
353 short readTid() { return threadNumber; }
355 /** Sets the thread id. */
356 void setTid(ThreadID tid) { threadNumber = tid; }
358 void setVpn(int id) { virtProcNumber = id; }
360 int readVpn() { return virtProcNumber; }
362 /** Sets the pointer to the thread state. */
363 void setThreadState(InOrderThreadState *state) { thread = state; }
365 /** Returns the thread context. */
366 ThreadContext *tcBase() { return thread->getTC(); }
368 /** Returns the fault type. */
369 Fault getFault() { return fault; }
371 ////////////////////////////////////////////////////////////
373 // INSTRUCTION TYPES - Forward checks to StaticInst object.
375 ////////////////////////////////////////////////////////////
376 bool isNop() const { return staticInst->isNop(); }
377 bool isMemRef() const { return staticInst->isMemRef(); }
378 bool isLoad() const { return staticInst->isLoad(); }
379 bool isStore() const { return staticInst->isStore(); }
380 bool isStoreConditional() const
381 { return staticInst->isStoreConditional(); }
382 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
383 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
384 bool isCopy() const { return staticInst->isCopy(); }
385 bool isInteger() const { return staticInst->isInteger(); }
386 bool isFloating() const { return staticInst->isFloating(); }
387 bool isControl() const { return staticInst->isControl(); }
388 bool isCall() const { return staticInst->isCall(); }
389 bool isReturn() const { return staticInst->isReturn(); }
390 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
391 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
392 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
393 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
394 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
396 bool isThreadSync() const { return staticInst->isThreadSync(); }
397 bool isSerializing() const { return staticInst->isSerializing(); }
398 bool isSerializeBefore() const
399 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
400 bool isSerializeAfter() const
401 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
402 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
403 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
404 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
405 bool isQuiesce() const { return staticInst->isQuiesce(); }
406 bool isIprAccess() const { return staticInst->isIprAccess(); }
407 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
409 /////////////////////////////////////////////
411 // RESOURCE SCHEDULING
413 /////////////////////////////////////////////
415 void setNextStage(int stage_num) { nextStage = stage_num; }
416 int getNextStage() { return nextStage; }
418 ThePipeline::InstStage *addStage();
419 ThePipeline::InstStage *addStage(int stage);
420 ThePipeline::InstStage *currentStage() { return currentInstStage; }
423 /** Add A Entry To Reource Schedule */
424 void addToSched(ScheduleEntry* sched_entry)
425 { resSched.push(sched_entry); }
428 /** Print Resource Schedule */
429 /** @NOTE: DEBUG ONLY */
432 ThePipeline::ResSchedule tempSched;
433 std::cerr << "\tInst. Res. Schedule: ";
434 while (!resSched.empty()) {
435 std::cerr << '\t' << resSched.top()->stageNum << "-"
436 << resSched.top()->resNum << ", ";
438 tempSched.push(resSched.top());
442 std::cerr << std::endl;
443 resSched = tempSched;
446 /** Return Next Resource Stage To Be Used */
449 if (resSched.empty())
452 return resSched.top()->stageNum;
456 /** Return Next Resource To Be Used */
459 if (resSched.empty())
462 return resSched.top()->resNum;
465 /** Remove & Deallocate a schedule entry */
468 if (!resSched.empty()) {
469 ScheduleEntry* sked = resSched.top();
478 /** Release a Resource Request (Currently Unused) */
479 void releaseReq(ResourceRequest* req);
481 ////////////////////////////////////////////
483 // INSTRUCTION EXECUTION
485 ////////////////////////////////////////////
486 /** Returns the opclass of this instruction. */
487 OpClass opClass() const { return staticInst->opClass(); }
489 /** Executes the instruction.*/
494 unsigned getCurResSlot() { return curResSlot; }
496 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
498 /** Calls a syscall. */
500 /** Calls hardware return from error interrupt. */
502 /** Traps to handle specified fault. */
503 void trap(Fault fault);
504 bool simPalCheck(int palFunc);
506 /** Calls a syscall. */
507 void syscall(int64_t callnum);
510 ////////////////////////////////////////////////////////////
512 // MULTITHREADING INTERFACE TO CPU MODELS
514 ////////////////////////////////////////////////////////////
515 virtual void deallocateContext(int thread_num);
517 ////////////////////////////////////////////////////////////
519 // PROGRAM COUNTERS - PC/NPC/NPC
521 ////////////////////////////////////////////////////////////
522 /** Read the PC of this instruction. */
523 const TheISA::PCState &pcState() const { return pc; }
525 /** Sets the PC of this instruction. */
526 void pcState(const TheISA::PCState &_pc) { pc = _pc; }
528 const Addr instAddr() { return pc.instAddr(); }
529 const Addr nextInstAddr() { return pc.nextInstAddr(); }
530 const MicroPC microPC() { return pc.microPC(); }
532 ////////////////////////////////////////////////////////////
536 ////////////////////////////////////////////////////////////
537 /** Set the predicted target of this current instruction. */
538 void setPredTarg(const TheISA::PCState &predictedPC)
539 { predPC = predictedPC; }
541 /** Returns the predicted target of the branch. */
542 TheISA::PCState readPredTarg() { return predPC; }
544 /** Returns the predicted PC immediately after the branch. */
545 Addr predInstAddr() { return predPC.instAddr(); }
547 /** Returns the predicted PC two instructions after the branch */
548 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
550 /** Returns the predicted micro PC after the branch */
551 Addr readPredMicroPC() { return predPC.microPC(); }
553 /** Returns whether the instruction was predicted taken or not. */
554 bool predTaken() { return predictTaken; }
556 /** Returns whether the instruction mispredicted. */
560 TheISA::PCState nextPC = pc;
561 TheISA::advancePC(nextPC, staticInst);
562 return !(nextPC == predPC);
565 /** Returns the branch target address. */
566 TheISA::PCState branchTarget() const
567 { return staticInst->branchTarget(pc); }
569 /** Checks whether or not this instruction has had its branch target
570 * calculated yet. For now it is not utilized and is hacked to be
572 * @todo: Actually use this instruction.
574 bool doneTargCalc() { return false; }
576 void setBranchPred(bool prediction) { predictTaken = prediction; }
582 bool procDelaySlotOnMispred;
584 ////////////////////////////////////////////
588 ////////////////////////////////////////////
590 * Does a read to a given address.
591 * @param addr The address to read.
592 * @param data The read's data is written into this parameter.
593 * @param flags The request's flags.
594 * @return Returns any fault due to the read.
597 Fault read(Addr addr, T &data, unsigned flags);
599 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
602 * Does a write to a given address.
603 * @param data The data to be written.
604 * @param addr The address to write to.
605 * @param flags The request's flags.
606 * @param res The result of the write (for load locked/store conditionals).
607 * @return Returns any fault due to the write.
610 Fault write(T data, Addr addr, unsigned flags,
613 Fault writeBytes(uint8_t *data, unsigned size,
614 Addr addr, unsigned flags, uint64_t *res);
616 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
617 * Access Only valid for memory operations.
621 /** Completes a memory access - Only valid for memory operations. */
622 Fault completeAcc(Packet *pkt);
624 /** Calculates Eff. Addr. part of a memory instruction. */
627 /** Read Effective Address from instruction & do memory access */
630 RequestPtr fetchMemReq;
631 RequestPtr dataMemReq;
636 { return memAddrReady; }
638 void setMemAddr(Addr addr)
639 { memAddr = addr; memAddrReady = true;}
642 { memAddrReady = false;}
647 /** Sets the effective address. */
648 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
650 /** Returns the effective address. */
651 const Addr &getEA() const { return instEffAddr; }
653 /** Returns whether or not the eff. addr. calculation has been completed.*/
654 bool doneEACalc() { return eaCalcDone; }
656 /** Returns whether or not the eff. addr. source registers are ready.
657 * Assume that src registers 1..n-1 are the ones that the
658 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
663 for (int i = 1; i < numSrcRegs(); ++i) {
664 if (!_readySrcRegIdx[i])
671 //////////////////////////////////////////////////
673 // SOURCE-DESTINATION REGISTER INDEXING
675 //////////////////////////////////////////////////
676 /** Returns the number of source registers. */
677 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
679 /** Returns the number of destination registers. */
680 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
682 // the following are used to track physical register usage
683 // for machines with separate int & FP reg files
684 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
685 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
687 /** Returns the logical register index of the i'th destination register. */
688 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
690 /** Returns the logical register index of the i'th source register. */
691 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
693 //////////////////////////////////////////////////
695 // RENAME/PHYSICAL REGISTER FILE SUPPORT
697 //////////////////////////////////////////////////
698 /** Returns the physical register index of the i'th destination
701 PhysRegIndex renamedDestRegIdx(int idx) const
703 return _destRegIdx[idx];
706 /** Returns the physical register index of the i'th source register. */
707 PhysRegIndex renamedSrcRegIdx(int idx) const
709 return _srcRegIdx[idx];
712 /** Returns the physical register index of the previous physical register
713 * that remapped to the same logical register index.
715 PhysRegIndex prevDestRegIdx(int idx) const
717 return _prevDestRegIdx[idx];
720 /** Returns if a source register is ready. */
721 bool isReadySrcRegIdx(int idx) const
723 return this->_readySrcRegIdx[idx];
726 /** Records that one of the source registers is ready. */
727 void markSrcRegReady()
729 if (++readyRegs == numSrcRegs()) {
730 status.set(CanIssue);
734 /** Marks a specific register as ready. */
735 void markSrcRegReady(RegIndex src_idx)
737 _readySrcRegIdx[src_idx] = true;
742 /** Renames a destination register to a physical register. Also records
743 * the previous physical register that the logical register mapped to.
745 void renameDestReg(int idx,
746 PhysRegIndex renamed_dest,
747 PhysRegIndex previous_rename)
749 _destRegIdx[idx] = renamed_dest;
750 _prevDestRegIdx[idx] = previous_rename;
753 /** Renames a source logical register to the physical register which
754 * has/will produce that logical register's result.
755 * @todo: add in whether or not the source register is ready.
757 void renameSrcReg(int idx, PhysRegIndex renamed_src)
759 _srcRegIdx[idx] = renamed_src;
763 PhysRegIndex readDestRegIdx(int idx)
765 return _destRegIdx[idx];
768 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
770 _destRegIdx[idx] = dest_idx;
773 int getDestIdxNum(PhysRegIndex dest_idx)
775 for (int i=0; i < staticInst->numDestRegs(); i++) {
776 if (_destRegIdx[i] == dest_idx)
783 PhysRegIndex readSrcRegIdx(int idx)
785 return _srcRegIdx[idx];
788 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
790 _srcRegIdx[idx] = src_idx;
793 int getSrcIdxNum(PhysRegIndex src_idx)
795 for (int i=0; i < staticInst->numSrcRegs(); i++) {
796 if (_srcRegIdx[i] == src_idx)
803 ////////////////////////////////////////////////////
805 // SOURCE-DESTINATION REGISTER VALUES
807 ////////////////////////////////////////////////////
809 /** Functions that sets an integer or floating point
810 * source register to a value. */
811 void setIntSrc(int idx, uint64_t val);
812 void setFloatSrc(int idx, FloatReg val);
813 void setFloatRegBitsSrc(int idx, uint64_t val);
815 uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
816 uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
818 /** These Instructions read a integer/float/misc. source register
819 * value in the instruction. The instruction's execute function will
820 * call these and it is the interface that is used by the ISA descr.
821 * language (which is why the name isnt readIntSrc(...)) Note: That
822 * the source reg. value is set using the setSrcReg() function.
824 IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
825 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
826 TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
827 MiscReg readMiscReg(int misc_reg);
828 MiscReg readMiscRegNoEffect(int misc_reg);
829 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
830 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
832 /** Returns the result value instruction. */
833 ResultType resultType(int idx)
835 return instResult[idx].type;
838 uint64_t readIntResult(int idx)
840 return instResult[idx].val.integer;
843 /** Depending on type, return Float or Double */
844 double readFloatResult(int idx)
846 return instResult[idx].val.dbl;
849 Tick readResultTime(int idx) { return instResult[idx].tick; }
851 uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
853 /** This is the interface that an instruction will use to write
854 * it's destination register.
856 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
857 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
858 void setFloatRegOperandBits(const StaticInst *si, int idx,
859 TheISA::FloatRegBits val);
860 void setMiscReg(int misc_reg, const MiscReg &val);
861 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
862 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
863 void setMiscRegOperandNoEffect(const StaticInst *si, int idx,
866 virtual uint64_t readRegOtherThread(unsigned idx,
867 ThreadID tid = InvalidThreadID);
868 virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
869 ThreadID tid = InvalidThreadID);
871 /** Sets the number of consecutive store conditional failures. */
872 void setStCondFailures(unsigned sc_failures)
873 { thread->storeCondFailures = sc_failures; }
875 //////////////////////////////////////////////////////////////
877 // INSTRUCTION STATUS FLAGS (READ/SET)
879 //////////////////////////////////////////////////////////////
880 /** Sets this instruction as entered on the CPU Reg Dep Map */
881 void setRegDepEntry() { status.set(RegDepMapEntry); }
883 /** Returns whether or not the entry is on the CPU Reg Dep Map */
884 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
886 /** Sets this instruction as entered on the CPU Reg Dep Map */
887 void setRemoveList() { status.set(RemoveList); }
889 /** Returns whether or not the entry is on the CPU Reg Dep Map */
890 bool isRemoveList() const { return status[RemoveList]; }
892 /** Sets this instruction as completed. */
893 void setCompleted() { status.set(Completed); }
895 /** Returns whether or not this instruction is completed. */
896 bool isCompleted() const { return status[Completed]; }
898 /** Marks the result as ready. */
899 void setResultReady() { status.set(ResultReady); }
901 /** Returns whether or not the result is ready. */
902 bool isResultReady() const { return status[ResultReady]; }
904 /** Sets this instruction as ready to issue. */
905 void setCanIssue() { status.set(CanIssue); }
907 /** Returns whether or not this instruction is ready to issue. */
908 bool readyToIssue() const { return status[CanIssue]; }
910 /** Sets this instruction as issued from the IQ. */
911 void setIssued() { status.set(Issued); }
913 /** Returns whether or not this instruction has issued. */
914 bool isIssued() const { return status[Issued]; }
916 /** Sets this instruction as executed. */
917 void setExecuted() { status.set(Executed); }
919 /** Returns whether or not this instruction has executed. */
920 bool isExecuted() const { return status[Executed]; }
922 /** Sets this instruction as ready to commit. */
923 void setCanCommit() { status.set(CanCommit); }
925 /** Clears this instruction as being ready to commit. */
926 void clearCanCommit() { status.reset(CanCommit); }
928 /** Returns whether or not this instruction is ready to commit. */
929 bool readyToCommit() const { return status[CanCommit]; }
931 void setAtCommit() { status.set(AtCommit); }
933 bool isAtCommit() { return status[AtCommit]; }
935 /** Sets this instruction as committed. */
936 void setCommitted() { status.set(Committed); }
938 /** Returns whether or not this instruction is committed. */
939 bool isCommitted() const { return status[Committed]; }
941 /** Sets this instruction as squashed. */
942 void setSquashed() { status.set(Squashed); }
944 /** Returns whether or not this instruction is squashed. */
945 bool isSquashed() const { return status[Squashed]; }
947 /** Temporarily sets this instruction as a serialize before instruction. */
948 void setSerializeBefore() { status.set(SerializeBefore); }
950 /** Clears the serializeBefore part of this instruction. */
951 void clearSerializeBefore() { status.reset(SerializeBefore); }
953 /** Checks if this serializeBefore is only temporarily set. */
954 bool isTempSerializeBefore() { return status[SerializeBefore]; }
956 /** Temporarily sets this instruction as a serialize after instruction. */
957 void setSerializeAfter() { status.set(SerializeAfter); }
959 /** Clears the serializeAfter part of this instruction.*/
960 void clearSerializeAfter() { status.reset(SerializeAfter); }
962 /** Checks if this serializeAfter is only temporarily set. */
963 bool isTempSerializeAfter() { return status[SerializeAfter]; }
965 /** Sets the serialization part of this instruction as handled. */
966 void setSerializeHandled() { status.set(SerializeHandled); }
968 /** Checks if the serialization part of this instruction has been
969 * handled. This does not apply to the temporary serializing
970 * state; it only applies to this instruction's own permanent
973 bool isSerializeHandled() { return status[SerializeHandled]; }
976 /** Instruction effective address.
977 * @todo: Consider if this is necessary or not.
981 /** Whether or not the effective address calculation is completed.
982 * @todo: Consider if this is necessary or not.
987 /** Whether or not the memory operation is done. */
991 /** Load queue index. */
994 /** Store queue index. */
997 /** Iterator pointing to this BaseDynInst in the list of all insts. */
1000 /** Returns iterator to this instruction in the list of all insts. */
1001 ListIt &getInstListIt() { return instListIt; }
1003 /** Sets iterator for this instruction in the list of all insts. */
1004 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
1006 /** Count of total number of dynamic instructions. */
1007 static int instcount;
1009 void resetInstCount();
1011 /** Dumps out contents of this BaseDynInst. */
1014 /** Dumps out contents of this BaseDynInst into given string. */
1015 void dump(std::string &outstring);
1017 //inline int curCount() { return curCount(); }
1021 #endif // __CPU_BASE_DYN_INST_HH__