2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/isa_traits.hh"
42 #include "arch/types.hh"
43 #include "arch/utility.hh"
44 #include "base/fast_alloc.hh"
45 #include "base/trace.hh"
46 #include "base/types.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/inorder/inorder_trace.hh"
49 #include "cpu/inorder/pipeline_traits.hh"
50 #include "cpu/inorder/resource.hh"
51 #include "cpu/inorder/resource_sked.hh"
52 #include "cpu/inorder/thread_state.hh"
53 #include "cpu/exetrace.hh"
54 #include "cpu/inst_seq.hh"
55 #include "cpu/op_class.hh"
56 #include "cpu/static_inst.hh"
57 #include "cpu/thread_context.hh"
58 #include "debug/InOrderDynInst.hh"
59 #include "mem/packet.hh"
60 #include "sim/fault_fwd.hh"
61 #include "sim/system.hh"
63 #if THE_ISA == ALPHA_ISA
64 #include "arch/alpha/ev5.hh"
69 * Defines a dynamic instruction context for a inorder CPU model.
72 // Forward declaration.
73 class ResourceRequest;
76 class InOrderDynInst : public FastAlloc, public RefCounted
79 // Binary machine instruction type.
80 typedef TheISA::MachInst MachInst;
81 // Extended machine instruction type
82 typedef TheISA::ExtMachInst ExtMachInst;
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
89 // Floating point register type.
90 typedef TheISA::FloatRegBits FloatRegBits;
91 // Floating point register type.
92 typedef TheISA::MiscReg MiscReg;
94 typedef short int PhysRegIndex;
96 /** The refcounted DynInst pointer to be used. In most cases this is
97 * what should be used, and not DynInst*.
99 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
101 // The list of instructions iterator type.
102 typedef std::list<DynInstPtr>::iterator ListIt;
105 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
106 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
110 /** BaseDynInst constructor given a binary instruction.
111 * @param seq_num The sequence number of the instruction.
112 * @param cpu Pointer to the instruction's CPU.
113 * NOTE: Must set Binary Instrution through Member Function
115 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
116 InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
118 /** InOrderDynInst destructor. */
122 /** The sequence number of the instruction. */
125 /** If this instruction is squashing, the number should we squash behind. */
126 InstSeqNum squashSeqNum;
129 RegDepMapEntry, /// Instruction is entered onto the RegDepMap
130 IqEntry, /// Instruction is in the IQ
131 RobEntry, /// Instruction is in the ROB
132 LsqEntry, /// Instruction is in the LSQ
133 Completed, /// Instruction has completed
134 ResultReady, /// Instruction has its result
135 CanIssue, /// Instruction can issue and execute
136 Issued, /// Instruction has issued
137 Executed, /// Instruction has executed
138 CanCommit, /// Instruction can commit
139 AtCommit, /// Instruction has reached commit
140 Committed, /// Instruction has committed
141 Squashed, /// Instruction is squashed
142 SquashedInIQ, /// Instruction is squashed in the IQ
143 SquashedInLSQ, /// Instruction is squashed in the LSQ
144 SquashedInROB, /// Instruction is squashed in the ROB
145 RecoverInst, /// Is a recover instruction
146 BlockingInst, /// Is a blocking instruction
147 ThreadsyncWait, /// Is a thread synchronization instruction
148 SerializeBefore, /// Needs to serialize on
149 /// instructions ahead of it
150 SerializeAfter, /// Needs to serialize instructions behind it
151 SerializeHandled, /// Serialization has been handled
152 RemoveList, /// Is Instruction on Remove List?
156 /** The status of this BaseDynInst. Several bits can be set. */
157 std::bitset<NumStatus> status;
159 /** The thread this instruction is from. */
162 /** data address space ID, for loads & stores. */
165 /** The virtual processor number */
166 short virtProcNumber;
168 /** The StaticInst used by this BaseDynInst. */
169 StaticInstPtr staticInst;
171 /** InstRecord that tracks this instructions. */
172 Trace::InOrderTraceRecord *traceData;
174 /** Pointer to the Impl's CPU object. */
177 /** Pointer to the thread state. */
178 InOrderThreadState *thread;
180 /** The kind of fault this instruction has generated. */
183 /** The memory request. */
186 /** Pointer to the data for the memory access. */
189 /** Data used for a store for operation. */
192 /** Data used for a store for operation. */
195 /** List of active resource requests for this instruction */
196 std::list<ResourceRequest*> reqList;
198 /** The effective virtual address (lds & stores only). */
201 /** The effective physical address. */
204 /** The memory request flags (from translation). */
205 unsigned memReqFlags;
207 /** How many source registers are ready. */
218 /** An instruction src/dest has to be one of these types */
233 /** Result of an instruction execution */
240 : type(None), tick(0)
244 /** The source of the instruction; assumes for now that there's only one
245 * destination register.
247 InstValue instSrc[MaxInstSrcRegs];
249 /** The result of the instruction; assumes for now that there's only one
250 * destination register.
252 InstResult instResult[MaxInstDestRegs];
254 /** PC of this instruction. */
257 /** Predicted next PC. */
258 TheISA::PCState predPC;
260 /** Address to get/write data from/to */
261 /* Fetching address when inst. starts, Data address for load/store after fetch*/
264 /** Whether or not the source register is ready.
265 * @todo: Not sure this should be here vs the derived class.
267 bool _readySrcRegIdx[MaxInstSrcRegs];
269 /** Flattened register index of the destination registers of this
272 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
274 /** Flattened register index of the source registers of this
277 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
279 /** Physical register index of the destination registers of this
282 PhysRegIndex _destRegIdx[MaxInstDestRegs];
284 /** Physical register index of the source registers of this
287 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
289 /** Physical register index of the previous producers of the
290 * architected destinations.
292 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
297 /** Function to initialize variables in the constructors. */
303 PacketDataPtr splitMemData;
304 RequestPtr splitMemReq;
309 uint8_t split2ndData;
310 PacketDataPtr split2ndDataPtr;
311 unsigned split2ndFlags;
314 uint64_t *split2ndStoreDataPtr;
317 ////////////////////////////////////////////////////////////
319 // BASE INSTRUCTION INFORMATION.
321 ////////////////////////////////////////////////////////////
322 std::string instName()
323 { return (staticInst) ? staticInst->getName() : "undecoded-inst"; }
325 void setStaticInst(StaticInstPtr si);
327 ExtMachInst getMachInst() { return staticInst->machInst; }
329 /** Sets the StaticInst. */
330 void setStaticInst(StaticInstPtr &static_inst);
332 /** Sets the sequence number. */
333 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
335 /** Sets the ASID. */
336 void setASID(short addr_space_id) { asid = addr_space_id; }
338 /** Reads the thread id. */
339 short readTid() { return threadNumber; }
341 /** Sets the thread id. */
342 void setTid(ThreadID tid) { threadNumber = tid; }
344 void setVpn(int id) { virtProcNumber = id; }
346 int readVpn() { return virtProcNumber; }
348 /** Sets the pointer to the thread state. */
349 void setThreadState(InOrderThreadState *state) { thread = state; }
351 /** Returns the thread context. */
352 ThreadContext *tcBase() { return thread->getTC(); }
354 /** Returns the fault type. */
355 Fault getFault() { return fault; }
357 /** Read this CPU's ID. */
360 /** Read this context's system-wide ID **/
361 int contextId() { return thread->contextId(); }
363 ////////////////////////////////////////////////////////////
365 // INSTRUCTION TYPES - Forward checks to StaticInst object.
367 ////////////////////////////////////////////////////////////
368 bool isNop() const { return staticInst->isNop(); }
369 bool isMemRef() const { return staticInst->isMemRef(); }
370 bool isLoad() const { return staticInst->isLoad(); }
371 bool isStore() const { return staticInst->isStore(); }
372 bool isStoreConditional() const
373 { return staticInst->isStoreConditional(); }
374 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
375 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
376 bool isInteger() const { return staticInst->isInteger(); }
377 bool isFloating() const { return staticInst->isFloating(); }
378 bool isControl() const { return staticInst->isControl(); }
379 bool isCall() const { return staticInst->isCall(); }
380 bool isReturn() const { return staticInst->isReturn(); }
381 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
382 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
383 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
384 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
385 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
387 bool isThreadSync() const { return staticInst->isThreadSync(); }
388 bool isSerializing() const { return staticInst->isSerializing(); }
389 bool isSerializeBefore() const
390 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
391 bool isSerializeAfter() const
392 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
393 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
394 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
395 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
396 bool isQuiesce() const { return staticInst->isQuiesce(); }
397 bool isIprAccess() const { return staticInst->isIprAccess(); }
398 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
399 bool isSyscall() const
400 { return staticInst->isSyscall(); }
401 bool isMicroop() const { return staticInst->isMicroop(); }
402 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
405 /////////////////////////////////////////////
407 // RESOURCE SCHEDULING
409 /////////////////////////////////////////////
410 typedef ThePipeline::RSkedPtr RSkedPtr;
414 RSkedIt frontSked_end;
417 RSkedIt backSked_end;
419 RSkedIt curSkedEntry;
421 void setFrontSked(RSkedPtr front_sked)
423 frontSked = front_sked;
424 frontSked_end.init(frontSked);
425 frontSked_end = frontSked->end();
426 //DPRINTF(InOrderDynInst, "Set FrontSked End to : %x \n" ,
427 // frontSked_end.getIt()/*, frontSked->end()*/);
428 //assert(frontSked_end == frontSked->end());
430 // This initializes instruction to be able
431 // to walk the resource schedule
432 curSkedEntry.init(frontSked);
433 curSkedEntry = frontSked->begin();
436 void setBackSked(RSkedPtr back_sked)
438 backSked = back_sked;
439 backSked_end.init(backSked);
440 backSked_end = backSked->end();
443 void setNextStage(int stage_num) { nextStage = stage_num; }
444 int getNextStage() { return nextStage; }
446 /** Print Resource Schedule */
449 if (frontSked != NULL) {
453 if (backSked != NULL) {
458 /** Return Next Resource Stage To Be Used */
461 assert((inFrontEnd && curSkedEntry != frontSked_end) ||
462 (!inFrontEnd && curSkedEntry != backSked_end));
464 return curSkedEntry->stageNum;
468 /** Return Next Resource To Be Used */
471 assert((inFrontEnd && curSkedEntry != frontSked_end) ||
472 (!inFrontEnd && curSkedEntry != backSked_end));
474 return curSkedEntry->resNum;
477 /** Finish using a schedule entry, increment to next entry */
478 bool finishSkedEntry()
482 if (inFrontEnd && curSkedEntry == frontSked_end) {
483 DPRINTF(InOrderDynInst, "[sn:%i] Switching to "
484 "back end schedule.\n", seqNum);
485 assert(backSked != NULL);
486 curSkedEntry.init(backSked);
487 curSkedEntry = backSked->begin();
489 } else if (!inFrontEnd && curSkedEntry == backSked_end) {
493 DPRINTF(InOrderDynInst, "[sn:%i] Next Stage: %i "
494 "Next Resource: %i.\n", seqNum, curSkedEntry->stageNum,
495 curSkedEntry->resNum);
500 /** Release a Resource Request (Currently Unused) */
501 void releaseReq(ResourceRequest* req);
503 ////////////////////////////////////////////
505 // INSTRUCTION EXECUTION
507 ////////////////////////////////////////////
508 /** Returns the opclass of this instruction. */
509 OpClass opClass() const { return staticInst->opClass(); }
511 /** Executes the instruction.*/
516 unsigned getCurResSlot() { return curResSlot; }
518 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
520 /** Calls a syscall. */
521 /** Calls hardware return from error interrupt. */
523 /** Traps to handle specified fault. */
524 void trap(Fault fault);
525 bool simPalCheck(int palFunc);
528 /** Emulates a syscall. */
529 void syscall(int64_t callnum);
531 ////////////////////////////////////////////////////////////
533 // MULTITHREADING INTERFACE TO CPU MODELS
535 ////////////////////////////////////////////////////////////
536 virtual void deallocateContext(int thread_num);
538 ////////////////////////////////////////////////////////////
540 // PROGRAM COUNTERS - PC/NPC/NPC
542 ////////////////////////////////////////////////////////////
543 /** Read the PC of this instruction. */
544 const TheISA::PCState &pcState() const { return pc; }
546 /** Sets the PC of this instruction. */
547 void pcState(const TheISA::PCState &_pc) { pc = _pc; }
549 const Addr instAddr() { return pc.instAddr(); }
550 const Addr nextInstAddr() { return pc.nextInstAddr(); }
551 const MicroPC microPC() { return pc.microPC(); }
553 ////////////////////////////////////////////////////////////
557 ////////////////////////////////////////////////////////////
558 /** Set the predicted target of this current instruction. */
559 void setPredTarg(const TheISA::PCState &predictedPC)
560 { predPC = predictedPC; }
562 /** Returns the predicted target of the branch. */
563 TheISA::PCState readPredTarg() { return predPC; }
565 /** Returns the predicted PC immediately after the branch. */
566 Addr predInstAddr() { return predPC.instAddr(); }
568 /** Returns the predicted PC two instructions after the branch */
569 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
571 /** Returns the predicted micro PC after the branch */
572 Addr readPredMicroPC() { return predPC.microPC(); }
574 /** Returns whether the instruction was predicted taken or not. */
575 bool predTaken() { return predictTaken; }
577 /** Returns whether the instruction mispredicted. */
581 TheISA::PCState nextPC = pc;
582 TheISA::advancePC(nextPC, staticInst);
583 return !(nextPC == predPC);
586 /** Returns the branch target address. */
587 TheISA::PCState branchTarget() const
588 { return staticInst->branchTarget(pc); }
590 /** Checks whether or not this instruction has had its branch target
591 * calculated yet. For now it is not utilized and is hacked to be
593 * @todo: Actually use this instruction.
595 bool doneTargCalc() { return false; }
597 void setBranchPred(bool prediction) { predictTaken = prediction; }
603 bool procDelaySlotOnMispred;
605 void setSquashInfo(unsigned stage_num);
607 ////////////////////////////////////////////
611 ////////////////////////////////////////////
613 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
615 Fault writeMem(uint8_t *data, unsigned size,
616 Addr addr, unsigned flags, uint64_t *res);
618 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
619 * Access Only valid for memory operations.
623 /** Completes a memory access - Only valid for memory operations. */
624 Fault completeAcc(Packet *pkt);
626 /** Calculates Eff. Addr. part of a memory instruction. */
629 /** Read Effective Address from instruction & do memory access */
632 RequestPtr fetchMemReq;
633 RequestPtr dataMemReq;
638 { return memAddrReady; }
640 void setMemAddr(Addr addr)
641 { memAddr = addr; memAddrReady = true;}
644 { memAddrReady = false;}
649 /** Sets the effective address. */
650 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
652 /** Returns the effective address. */
653 const Addr &getEA() const { return instEffAddr; }
655 /** Returns whether or not the eff. addr. calculation has been completed.*/
656 bool doneEACalc() { return eaCalcDone; }
658 /** Returns whether or not the eff. addr. source registers are ready.
659 * Assume that src registers 1..n-1 are the ones that the
660 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
665 for (int i = 1; i < numSrcRegs(); ++i) {
666 if (!_readySrcRegIdx[i])
673 //////////////////////////////////////////////////
675 // SOURCE-DESTINATION REGISTER INDEXING
677 //////////////////////////////////////////////////
678 /** Returns the number of source registers. */
679 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
681 /** Returns the number of destination registers. */
682 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
684 // the following are used to track physical register usage
685 // for machines with separate int & FP reg files
686 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
687 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
689 /** Returns the logical register index of the i'th destination register. */
690 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
692 /** Returns the logical register index of the i'th source register. */
693 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
695 //////////////////////////////////////////////////
697 // RENAME/PHYSICAL REGISTER FILE SUPPORT
699 //////////////////////////////////////////////////
700 /** Returns the physical register index of the i'th destination
703 PhysRegIndex renamedDestRegIdx(int idx) const
705 return _destRegIdx[idx];
708 /** Returns the physical register index of the i'th source register. */
709 PhysRegIndex renamedSrcRegIdx(int idx) const
711 return _srcRegIdx[idx];
714 /** Flattens a source architectural register index into a logical index.
716 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
718 _flatSrcRegIdx[idx] = flattened_src;
721 /** Flattens a destination architectural register index into a logical
724 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
726 _flatDestRegIdx[idx] = flattened_dest;
729 /** Returns the flattened register index of the i'th destination
732 TheISA::RegIndex flattenedDestRegIdx(int idx) const
734 return _flatDestRegIdx[idx];
737 /** Returns the flattened register index of the i'th source register */
738 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
740 return _flatSrcRegIdx[idx];
743 /** Returns the physical register index of the previous physical register
744 * that remapped to the same logical register index.
746 PhysRegIndex prevDestRegIdx(int idx) const
748 return _prevDestRegIdx[idx];
751 /** Returns if a source register is ready. */
752 bool isReadySrcRegIdx(int idx) const
754 return this->_readySrcRegIdx[idx];
757 /** Records that one of the source registers is ready. */
758 void markSrcRegReady()
760 if (++readyRegs == numSrcRegs()) {
761 status.set(CanIssue);
765 /** Marks a specific register as ready. */
766 void markSrcRegReady(RegIndex src_idx)
768 _readySrcRegIdx[src_idx] = true;
773 /** Renames a destination register to a physical register. Also records
774 * the previous physical register that the logical register mapped to.
776 void renameDestReg(int idx,
777 PhysRegIndex renamed_dest,
778 PhysRegIndex previous_rename)
780 _destRegIdx[idx] = renamed_dest;
781 _prevDestRegIdx[idx] = previous_rename;
784 /** Renames a source logical register to the physical register which
785 * has/will produce that logical register's result.
786 * @todo: add in whether or not the source register is ready.
788 void renameSrcReg(int idx, PhysRegIndex renamed_src)
790 _srcRegIdx[idx] = renamed_src;
794 PhysRegIndex readDestRegIdx(int idx)
796 return _destRegIdx[idx];
799 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
801 _destRegIdx[idx] = dest_idx;
804 int getDestIdxNum(PhysRegIndex dest_idx)
806 for (int i=0; i < staticInst->numDestRegs(); i++) {
807 if (_flatDestRegIdx[i] == dest_idx)
814 PhysRegIndex readSrcRegIdx(int idx)
816 return _srcRegIdx[idx];
819 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
821 _srcRegIdx[idx] = src_idx;
824 int getSrcIdxNum(PhysRegIndex src_idx)
826 for (int i=0; i < staticInst->numSrcRegs(); i++) {
827 if (_srcRegIdx[i] == src_idx)
834 ////////////////////////////////////////////////////
836 // SOURCE-DESTINATION REGISTER VALUES
838 ////////////////////////////////////////////////////
840 /** Functions that sets an integer or floating point
841 * source register to a value. */
842 void setIntSrc(int idx, uint64_t val);
843 void setFloatSrc(int idx, FloatReg val);
844 void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val);
846 TheISA::IntReg* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
847 uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; }
849 /** These Instructions read a integer/float/misc. source register
850 * value in the instruction. The instruction's execute function will
851 * call these and it is the interface that is used by the ISA descr.
852 * language (which is why the name isnt readIntSrc(...)) Note: That
853 * the source reg. value is set using the setSrcReg() function.
855 IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
856 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
857 TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
858 MiscReg readMiscReg(int misc_reg);
859 MiscReg readMiscRegNoEffect(int misc_reg);
860 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
861 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
863 /** Returns the result value instruction. */
864 ResultType resultType(int idx)
866 return instResult[idx].type;
869 IntReg readIntResult(int idx)
871 return instResult[idx].res.intVal;
874 FloatReg readFloatResult(int idx)
876 return instResult[idx].res.fpVal.f;
879 FloatRegBits readFloatBitsResult(int idx)
881 return instResult[idx].res.fpVal.i;
884 Tick readResultTime(int idx) { return instResult[idx].tick; }
886 IntReg* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; }
888 /** This is the interface that an instruction will use to write
889 * it's destination register.
891 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
892 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
893 void setFloatRegOperandBits(const StaticInst *si, int idx,
894 TheISA::FloatRegBits val);
895 void setMiscReg(int misc_reg, const MiscReg &val);
896 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
897 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
898 void setMiscRegOperandNoEffect(const StaticInst *si, int idx,
901 virtual uint64_t readRegOtherThread(unsigned idx,
902 ThreadID tid = InvalidThreadID);
903 virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
904 ThreadID tid = InvalidThreadID);
906 /** Returns the number of consecutive store conditional failures. */
907 unsigned readStCondFailures()
908 { return thread->storeCondFailures; }
910 /** Sets the number of consecutive store conditional failures. */
911 void setStCondFailures(unsigned sc_failures)
912 { thread->storeCondFailures = sc_failures; }
914 //////////////////////////////////////////////////////////////
916 // INSTRUCTION STATUS FLAGS (READ/SET)
918 //////////////////////////////////////////////////////////////
919 /** Sets this instruction as entered on the CPU Reg Dep Map */
920 void setRegDepEntry() { status.set(RegDepMapEntry); }
922 /** Unsets this instruction as entered on the CPU Reg Dep Map */
923 void clearRegDepEntry() { status.reset(RegDepMapEntry); }
925 /** Returns whether or not the entry is on the CPU Reg Dep Map */
926 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
928 /** Sets this instruction as entered on the CPU Reg Dep Map */
929 void setRemoveList() { status.set(RemoveList); }
931 /** Returns whether or not the entry is on the CPU Reg Dep Map */
932 bool isRemoveList() const { return status[RemoveList]; }
934 /** Sets this instruction as completed. */
935 void setCompleted() { status.set(Completed); }
937 /** Returns whether or not this instruction is completed. */
938 bool isCompleted() const { return status[Completed]; }
940 /** Marks the result as ready. */
941 void setResultReady() { status.set(ResultReady); }
943 /** Returns whether or not the result is ready. */
944 bool isResultReady() const { return status[ResultReady]; }
946 /** Sets this instruction as ready to issue. */
947 void setCanIssue() { status.set(CanIssue); }
949 /** Returns whether or not this instruction is ready to issue. */
950 bool readyToIssue() const { return status[CanIssue]; }
952 /** Sets this instruction as issued from the IQ. */
953 void setIssued() { status.set(Issued); }
955 /** Returns whether or not this instruction has issued. */
956 bool isIssued() const { return status[Issued]; }
958 /** Sets this instruction as executed. */
959 void setExecuted() { status.set(Executed); }
961 /** Returns whether or not this instruction has executed. */
962 bool isExecuted() const { return status[Executed]; }
964 /** Sets this instruction as ready to commit. */
965 void setCanCommit() { status.set(CanCommit); }
967 /** Clears this instruction as being ready to commit. */
968 void clearCanCommit() { status.reset(CanCommit); }
970 /** Returns whether or not this instruction is ready to commit. */
971 bool readyToCommit() const { return status[CanCommit]; }
973 void setAtCommit() { status.set(AtCommit); }
975 bool isAtCommit() { return status[AtCommit]; }
977 /** Sets this instruction as committed. */
978 void setCommitted() { status.set(Committed); }
980 /** Returns whether or not this instruction is committed. */
981 bool isCommitted() const { return status[Committed]; }
983 /** Sets this instruction as squashed. */
984 void setSquashed() { status.set(Squashed); }
986 /** Returns whether or not this instruction is squashed. */
987 bool isSquashed() const { return status[Squashed]; }
989 /** Temporarily sets this instruction as a serialize before instruction. */
990 void setSerializeBefore() { status.set(SerializeBefore); }
992 /** Clears the serializeBefore part of this instruction. */
993 void clearSerializeBefore() { status.reset(SerializeBefore); }
995 /** Checks if this serializeBefore is only temporarily set. */
996 bool isTempSerializeBefore() { return status[SerializeBefore]; }
998 /** Temporarily sets this instruction as a serialize after instruction. */
999 void setSerializeAfter() { status.set(SerializeAfter); }
1001 /** Clears the serializeAfter part of this instruction.*/
1002 void clearSerializeAfter() { status.reset(SerializeAfter); }
1004 /** Checks if this serializeAfter is only temporarily set. */
1005 bool isTempSerializeAfter() { return status[SerializeAfter]; }
1007 /** Sets the serialization part of this instruction as handled. */
1008 void setSerializeHandled() { status.set(SerializeHandled); }
1010 /** Checks if the serialization part of this instruction has been
1011 * handled. This does not apply to the temporary serializing
1012 * state; it only applies to this instruction's own permanent
1013 * serializing state.
1015 bool isSerializeHandled() { return status[SerializeHandled]; }
1018 /** Instruction effective address.
1019 * @todo: Consider if this is necessary or not.
1023 /** Whether or not the effective address calculation is completed.
1024 * @todo: Consider if this is necessary or not.
1029 /** Load queue index. */
1032 /** Store queue index. */
1035 /** Iterator pointing to this BaseDynInst in the list of all insts. */
1040 /** Returns iterator to this instruction in the list of all insts. */
1041 ListIt getInstListIt() { return instListIt; }
1043 /** Sets iterator for this instruction in the list of all insts. */
1044 void setInstListIt(ListIt _instListIt) { onInstList = true; instListIt = _instListIt; }
1046 /** Count of total number of dynamic instructions. */
1047 static int instcount;
1049 void resetInstCount();
1051 /** Dumps out contents of this BaseDynInst. */
1054 /** Dumps out contents of this BaseDynInst into given string. */
1055 void dump(std::string &outstring);
1057 //inline int curCount() { return curCount(); }
1061 #endif // __CPU_BASE_DYN_INST_HH__