2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/faults.hh"
41 #include "arch/isa_traits.hh"
43 #include "arch/types.hh"
44 #include "base/fast_alloc.hh"
45 #include "base/trace.hh"
46 #include "base/types.hh"
47 #include "config/full_system.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/exetrace.hh"
50 #include "cpu/inorder/inorder_trace.hh"
51 #include "cpu/inorder/pipeline_traits.hh"
52 #include "cpu/inorder/resource.hh"
53 #include "cpu/inorder/thread_state.hh"
54 #include "cpu/inst_seq.hh"
55 #include "cpu/op_class.hh"
56 #include "cpu/static_inst.hh"
57 #include "cpu/thread_context.hh"
58 #include "mem/packet.hh"
59 #include "sim/system.hh"
61 #if THE_ISA == ALPHA_ISA
62 #include "arch/alpha/ev5.hh"
67 * Defines a dynamic instruction context for a inorder CPU model.
70 // Forward declaration.
72 class ResourceRequest;
75 class InOrderDynInst : public FastAlloc, public RefCounted
78 // Binary machine instruction type.
79 typedef TheISA::MachInst MachInst;
80 // Extended machine instruction type
81 typedef TheISA::ExtMachInst ExtMachInst;
82 // Logical register index type.
83 typedef TheISA::RegIndex RegIndex;
84 // Integer register type.
85 typedef TheISA::IntReg IntReg;
86 // Floating point register type.
87 typedef TheISA::FloatReg FloatReg;
88 // Floating point register type.
89 typedef TheISA::MiscReg MiscReg;
91 typedef short int PhysRegIndex;
93 /** The refcounted DynInst pointer to be used. In most cases this is
94 * what should be used, and not DynInst*.
96 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
98 // The list of instructions iterator type.
99 typedef std::list<DynInstPtr>::iterator ListIt;
102 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
103 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
107 /** BaseDynInst constructor given a binary instruction.
108 * @param inst The binary instruction.
109 * @param PC The PC of the instruction.
110 * @param pred_PC The predicted next PC.
111 * @param seq_num The sequence number of the instruction.
112 * @param cpu Pointer to the instruction's CPU.
114 InOrderDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
117 /** BaseDynInst constructor given a binary instruction.
118 * @param seq_num The sequence number of the instruction.
119 * @param cpu Pointer to the instruction's CPU.
120 * NOTE: Must set Binary Instrution through Member Function
122 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
123 InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
125 /** BaseDynInst constructor given a StaticInst pointer.
126 * @param _staticInst The StaticInst for this BaseDynInst.
128 InOrderDynInst(StaticInstPtr &_staticInst);
130 /** Skeleton Constructor. */
133 /** InOrderDynInst destructor. */
137 /** The sequence number of the instruction. */
140 /** The sequence number of the instruction. */
141 InstSeqNum bdelaySeqNum;
144 RegDepMapEntry, /// Instruction has been entered onto the RegDepMap
145 IqEntry, /// Instruction is in the IQ
146 RobEntry, /// Instruction is in the ROB
147 LsqEntry, /// Instruction is in the LSQ
148 Completed, /// Instruction has completed
149 ResultReady, /// Instruction has its result
150 CanIssue, /// Instruction can issue and execute
151 Issued, /// Instruction has issued
152 Executed, /// Instruction has executed
153 CanCommit, /// Instruction can commit
154 AtCommit, /// Instruction has reached commit
155 Committed, /// Instruction has committed
156 Squashed, /// Instruction is squashed
157 SquashedInIQ, /// Instruction is squashed in the IQ
158 SquashedInLSQ, /// Instruction is squashed in the LSQ
159 SquashedInROB, /// Instruction is squashed in the ROB
160 RecoverInst, /// Is a recover instruction
161 BlockingInst, /// Is a blocking instruction
162 ThreadsyncWait, /// Is a thread synchronization instruction
163 SerializeBefore, /// Needs to serialize on
164 /// instructions ahead of it
165 SerializeAfter, /// Needs to serialize instructions behind it
166 SerializeHandled, /// Serialization has been handled
170 /** The status of this BaseDynInst. Several bits can be set. */
171 std::bitset<NumStatus> status;
173 /** The thread this instruction is from. */
176 /** data address space ID, for loads & stores. */
179 /** The virtual processor number */
180 short virtProcNumber;
182 /** The StaticInst used by this BaseDynInst. */
183 StaticInstPtr staticInst;
185 /** InstRecord that tracks this instructions. */
186 Trace::InOrderTraceRecord *traceData;
188 /** Pointer to the Impl's CPU object. */
191 /** Pointer to the thread state. */
192 InOrderThreadState *thread;
194 /** The kind of fault this instruction has generated. */
197 /** The memory request. */
200 /** Pointer to the data for the memory access. */
203 /** Data used for a store for operation. */
206 /** Data used for a store for operation. */
209 /** The resource schedule for this inst */
210 ThePipeline::ResSchedule resSched;
212 /** List of active resource requests for this instruction */
213 std::list<ResourceRequest*> reqList;
215 /** The effective virtual address (lds & stores only). */
218 /** The effective physical address. */
221 /** Effective virtual address for a copy source. */
224 /** Effective physical address for a copy source. */
225 Addr copySrcPhysEffAddr;
227 /** The memory request flags (from translation). */
228 unsigned memReqFlags;
230 /** How many source registers are ready. */
233 /** An instruction src/dest has to be one of these types */
239 //@TODO: Naming Convention for Enums?
248 /** Result of an instruction execution */
255 : type(None), tick(0)
259 /** The source of the instruction; assumes for now that there's only one
260 * destination register.
262 InstValue instSrc[MaxInstSrcRegs];
264 /** The result of the instruction; assumes for now that there's only one
265 * destination register.
267 InstResult instResult[MaxInstDestRegs];
269 /** PC of this instruction. */
272 /** Next non-speculative PC. It is not filled in at fetch, but rather
273 * once the target of the branch is truly known (either decode or
278 /** Next next non-speculative PC. It is not filled in at fetch, but rather
279 * once the target of the branch is truly known (either decode or
284 /** Predicted next PC. */
287 /** Predicted next NPC. */
290 /** Predicted next microPC */
293 /** Address to fetch from */
296 /** Address to get/write data from/to */
299 /** Whether or not the source register is ready.
300 * @todo: Not sure this should be here vs the derived class.
302 bool _readySrcRegIdx[MaxInstSrcRegs];
304 /** Physical register index of the destination registers of this
307 PhysRegIndex _destRegIdx[MaxInstDestRegs];
309 /** Physical register index of the source registers of this
312 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
314 /** Physical register index of the previous producers of the
315 * architected destinations.
317 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
321 /* vars to keep track of InstStage's - used for resource sched defn */
322 int nextInstStageNum;
323 ThePipeline::InstStage *currentInstStage;
324 std::list<ThePipeline::InstStage*> instStageList;
327 /** Function to initialize variables in the constructors. */
333 ////////////////////////////////////////////////////////////
335 // BASE INSTRUCTION INFORMATION.
337 ////////////////////////////////////////////////////////////
338 std::string instName() { return staticInst->getName(); }
341 void setMachInst(ExtMachInst inst);
343 /** Sets the StaticInst. */
344 void setStaticInst(StaticInstPtr &static_inst);
346 /** Sets the sequence number. */
347 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
349 /** Sets the ASID. */
350 void setASID(short addr_space_id) { asid = addr_space_id; }
352 /** Reads the thread id. */
353 short readTid() { return threadNumber; }
355 /** Sets the thread id. */
356 void setTid(ThreadID tid) { threadNumber = tid; }
358 void setVpn(int id) { virtProcNumber = id; }
360 int readVpn() { return virtProcNumber; }
362 /** Sets the pointer to the thread state. */
363 void setThreadState(InOrderThreadState *state) { thread = state; }
365 /** Returns the thread context. */
366 ThreadContext *tcBase() { return thread->getTC(); }
368 /** Returns the fault type. */
369 Fault getFault() { return fault; }
371 ////////////////////////////////////////////////////////////
373 // INSTRUCTION TYPES - Forward checks to StaticInst object.
375 ////////////////////////////////////////////////////////////
376 bool isNop() const { return staticInst->isNop(); }
377 bool isMemRef() const { return staticInst->isMemRef(); }
378 bool isLoad() const { return staticInst->isLoad(); }
379 bool isStore() const { return staticInst->isStore(); }
380 bool isStoreConditional() const
381 { return staticInst->isStoreConditional(); }
382 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
383 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
384 bool isCopy() const { return staticInst->isCopy(); }
385 bool isInteger() const { return staticInst->isInteger(); }
386 bool isFloating() const { return staticInst->isFloating(); }
387 bool isControl() const { return staticInst->isControl(); }
388 bool isCall() const { return staticInst->isCall(); }
389 bool isReturn() const { return staticInst->isReturn(); }
390 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
391 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
392 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
393 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
394 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
396 bool isThreadSync() const { return staticInst->isThreadSync(); }
397 bool isSerializing() const { return staticInst->isSerializing(); }
398 bool isSerializeBefore() const
399 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
400 bool isSerializeAfter() const
401 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
402 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
403 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
404 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
405 bool isQuiesce() const { return staticInst->isQuiesce(); }
406 bool isIprAccess() const { return staticInst->isIprAccess(); }
407 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
409 /////////////////////////////////////////////
411 // RESOURCE SCHEDULING
413 /////////////////////////////////////////////
415 void setNextStage(int stage_num) { nextStage = stage_num; }
416 int getNextStage() { return nextStage; }
418 ThePipeline::InstStage *addStage();
419 ThePipeline::InstStage *addStage(int stage);
420 ThePipeline::InstStage *currentStage() { return currentInstStage; }
423 /** Add A Entry To Reource Schedule */
424 void addToSched(ThePipeline::ScheduleEntry* sched_entry)
425 { resSched.push(sched_entry); }
428 /** Print Resource Schedule */
429 /** @NOTE: DEBUG ONLY */
432 ThePipeline::ResSchedule tempSched;
433 std::cerr << "\tInst. Res. Schedule: ";
434 while (!resSched.empty()) {
435 std::cerr << '\t' << resSched.top()->stageNum << "-"
436 << resSched.top()->resNum << ", ";
438 tempSched.push(resSched.top());
442 std::cerr << std::endl;
443 resSched = tempSched;
446 /** Return Next Resource Stage To Be Used */
449 if (resSched.empty())
452 return resSched.top()->stageNum;
456 /** Return Next Resource To Be Used */
459 if (resSched.empty())
462 return resSched.top()->resNum;
465 /** Remove & Deallocate a schedule entry */
468 if (!resSched.empty()) {
469 ThePipeline::ScheduleEntry* sked = resSched.top();
475 /** Release a Resource Request (Currently Unused) */
476 void releaseReq(ResourceRequest* req);
478 ////////////////////////////////////////////
480 // INSTRUCTION EXECUTION
482 ////////////////////////////////////////////
483 /** Returns the opclass of this instruction. */
484 OpClass opClass() const { return staticInst->opClass(); }
486 /** Executes the instruction.*/
491 unsigned getCurResSlot() { return curResSlot; }
493 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
495 /** Calls a syscall. */
497 /** Calls hardware return from error interrupt. */
499 /** Traps to handle specified fault. */
500 void trap(Fault fault);
501 bool simPalCheck(int palFunc);
503 /** Calls a syscall. */
504 void syscall(int64_t callnum);
506 void prefetch(Addr addr, unsigned flags);
507 void writeHint(Addr addr, int size, unsigned flags);
508 Fault copySrcTranslate(Addr src);
509 Fault copy(Addr dest);
511 ////////////////////////////////////////////////////////////
513 // MULTITHREADING INTERFACE TO CPU MODELS
515 ////////////////////////////////////////////////////////////
516 virtual void deallocateContext(int thread_num);
518 virtual void enableVirtProcElement(unsigned vpe);
519 virtual void disableVirtProcElement(unsigned vpe);
521 virtual void enableMultiThreading(unsigned vpe);
522 virtual void disableMultiThreading(unsigned vpe);
524 ////////////////////////////////////////////////////////////
526 // PROGRAM COUNTERS - PC/NPC/NPC
528 ////////////////////////////////////////////////////////////
529 /** Read the PC of this instruction. */
530 const Addr readPC() const { return PC; }
532 /** Sets the PC of this instruction. */
533 void setPC(Addr pc) { PC = pc; }
535 /** Returns the next PC. This could be the speculative next PC if it is
536 * called prior to the actual branch target being calculated.
538 Addr readNextPC() { return nextPC; }
540 /** Set the next PC of this instruction (its actual target). */
541 void setNextPC(uint64_t val) { nextPC = val; }
543 /** Returns the next NPC. This could be the speculative next NPC if it is
544 * called prior to the actual branch target being calculated.
548 #if ISA_HAS_DELAY_SLOT
551 return nextPC + sizeof(TheISA::MachInst);
555 /** Set the next PC of this instruction (its actual target). */
556 void setNextNPC(uint64_t val) { nextNPC = val; }
558 ////////////////////////////////////////////////////////////
562 ////////////////////////////////////////////////////////////
563 /** Set the predicted target of this current instruction. */
564 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
566 /** Returns the predicted target of the branch. */
567 Addr readPredTarg() { return predPC; }
569 /** Returns the predicted PC immediately after the branch. */
570 Addr readPredPC() { return predPC; }
572 /** Returns the predicted PC two instructions after the branch */
573 Addr readPredNPC() { return predNPC; }
575 /** Returns the predicted micro PC after the branch */
576 Addr readPredMicroPC() { return predMicroPC; }
578 /** Returns whether the instruction was predicted taken or not. */
579 bool predTaken() { return predictTaken; }
581 /** Returns whether the instruction mispredicted. */
584 #if ISA_HAS_DELAY_SLOT
585 return predPC != nextNPC;
587 return predPC != nextPC;
591 /** Returns whether the instruction mispredicted. */
592 bool mistargeted() { return predPC != nextNPC; }
594 /** Returns the branch target address. */
595 Addr branchTarget() const { return staticInst->branchTarget(PC); }
597 /** Checks whether or not this instruction has had its branch target
598 * calculated yet. For now it is not utilized and is hacked to be
600 * @todo: Actually use this instruction.
602 bool doneTargCalc() { return false; }
604 void setBranchPred(bool prediction) { predictTaken = prediction; }
610 bool procDelaySlotOnMispred;
612 ////////////////////////////////////////////
616 ////////////////////////////////////////////
618 * Does a read to a given address.
619 * @param addr The address to read.
620 * @param data The read's data is written into this parameter.
621 * @param flags The request's flags.
622 * @return Returns any fault due to the read.
625 Fault read(Addr addr, T &data, unsigned flags);
628 * Does a write to a given address.
629 * @param data The data to be written.
630 * @param addr The address to write to.
631 * @param flags The request's flags.
632 * @param res The result of the write (for load locked/store conditionals).
633 * @return Returns any fault due to the write.
636 Fault write(T data, Addr addr, unsigned flags,
639 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory Access
640 * Only valid for memory operations.
644 /** Completes a memory access - Only valid for memory operations. */
645 Fault completeAcc(Packet *pkt);
647 /** Calculates Eff. Addr. part of a memory instruction. */
650 /** Read Effective Address from instruction & do memory access */
653 RequestPtr fetchMemReq;
654 RequestPtr dataMemReq;
659 { return memAddrReady; }
661 void setMemAddr(Addr addr)
662 { memAddr = addr; memAddrReady = true;}
665 { memAddrReady = false;}
670 /** Sets the effective address. */
671 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
673 /** Returns the effective address. */
674 const Addr &getEA() const { return instEffAddr; }
676 /** Returns whether or not the eff. addr. calculation has been completed. */
677 bool doneEACalc() { return eaCalcDone; }
679 /** Returns whether or not the eff. addr. source registers are ready.
680 * Assume that src registers 1..n-1 are the ones that the
681 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
686 for (int i = 1; i < numSrcRegs(); ++i) {
687 if (!_readySrcRegIdx[i])
694 //////////////////////////////////////////////////
696 // SOURCE-DESTINATION REGISTER INDEXING
698 //////////////////////////////////////////////////
699 /** Returns the number of source registers. */
700 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
702 /** Returns the number of destination registers. */
703 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
705 // the following are used to track physical register usage
706 // for machines with separate int & FP reg files
707 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
708 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
710 /** Returns the logical register index of the i'th destination register. */
711 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
713 /** Returns the logical register index of the i'th source register. */
714 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
716 //////////////////////////////////////////////////
718 // RENAME/PHYSICAL REGISTER FILE SUPPORT
720 //////////////////////////////////////////////////
721 /** Returns the physical register index of the i'th destination
724 PhysRegIndex renamedDestRegIdx(int idx) const
726 return _destRegIdx[idx];
729 /** Returns the physical register index of the i'th source register. */
730 PhysRegIndex renamedSrcRegIdx(int idx) const
732 return _srcRegIdx[idx];
735 /** Returns the physical register index of the previous physical register
736 * that remapped to the same logical register index.
738 PhysRegIndex prevDestRegIdx(int idx) const
740 return _prevDestRegIdx[idx];
743 /** Returns if a source register is ready. */
744 bool isReadySrcRegIdx(int idx) const
746 return this->_readySrcRegIdx[idx];
749 /** Records that one of the source registers is ready. */
750 void markSrcRegReady()
752 if (++readyRegs == numSrcRegs()) {
753 status.set(CanIssue);
757 /** Marks a specific register as ready. */
758 void markSrcRegReady(RegIndex src_idx)
760 _readySrcRegIdx[src_idx] = true;
765 /** Renames a destination register to a physical register. Also records
766 * the previous physical register that the logical register mapped to.
768 void renameDestReg(int idx,
769 PhysRegIndex renamed_dest,
770 PhysRegIndex previous_rename)
772 _destRegIdx[idx] = renamed_dest;
773 _prevDestRegIdx[idx] = previous_rename;
776 /** Renames a source logical register to the physical register which
777 * has/will produce that logical register's result.
778 * @todo: add in whether or not the source register is ready.
780 void renameSrcReg(int idx, PhysRegIndex renamed_src)
782 _srcRegIdx[idx] = renamed_src;
786 PhysRegIndex readDestRegIdx(int idx)
788 return _destRegIdx[idx];
791 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
793 _destRegIdx[idx] = dest_idx;
796 int getDestIdxNum(PhysRegIndex dest_idx)
798 for (int i=0; i < staticInst->numDestRegs(); i++) {
799 if (_destRegIdx[i] == dest_idx)
806 PhysRegIndex readSrcRegIdx(int idx)
808 return _srcRegIdx[idx];
811 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
813 _srcRegIdx[idx] = src_idx;
816 int getSrcIdxNum(PhysRegIndex src_idx)
818 for (int i=0; i < staticInst->numSrcRegs(); i++) {
819 if (_srcRegIdx[i] == src_idx)
826 ////////////////////////////////////////////////////
828 // SOURCE-DESTINATION REGISTER VALUES
830 ////////////////////////////////////////////////////
832 /** Functions that sets an integer or floating point
833 * source register to a value. */
834 void setIntSrc(int idx, uint64_t val);
835 void setFloatSrc(int idx, FloatReg val);
836 void setFloatRegBitsSrc(int idx, uint64_t val);
838 uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
839 uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
841 /** These Instructions read a integer/float/misc. source register
842 * value in the instruction. The instruction's execute function will
843 * call these and it is the interface that is used by the ISA descr.
844 * language (which is why the name isnt readIntSrc(...)) Note: That
845 * the source reg. value is set using the setSrcReg() function.
847 IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
848 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
849 TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
850 MiscReg readMiscReg(int misc_reg);
851 MiscReg readMiscRegNoEffect(int misc_reg);
852 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
853 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
855 /** Returns the result value instruction. */
856 ResultType resultType(int idx)
858 return instResult[idx].type;
861 uint64_t readIntResult(int idx)
863 return instResult[idx].val.integer;
866 /** Depending on type, return Float or Double */
867 double readFloatResult(int idx)
869 return instResult[idx].val.dbl;
872 Tick readResultTime(int idx) { return instResult[idx].tick; }
874 uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
876 /** This is the interface that an instruction will use to write
877 * it's destination register.
879 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
880 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
881 void setFloatRegOperandBits(const StaticInst *si, int idx,
882 TheISA::FloatRegBits val);
883 void setMiscReg(int misc_reg, const MiscReg &val);
884 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
885 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
886 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val);
888 virtual uint64_t readRegOtherThread(unsigned idx,
889 ThreadID tid = InvalidThreadID);
890 virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
891 ThreadID tid = InvalidThreadID);
893 /** Sets the number of consecutive store conditional failures. */
894 void setStCondFailures(unsigned sc_failures)
895 { thread->storeCondFailures = sc_failures; }
897 //////////////////////////////////////////////////////////////
899 // INSTRUCTION STATUS FLAGS (READ/SET)
901 //////////////////////////////////////////////////////////////
902 /** Sets this instruction as entered on the CPU Reg Dep Map */
903 void setRegDepEntry() { status.set(RegDepMapEntry); }
905 /** Returns whether or not the entry is on the CPU Reg Dep Map */
906 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
908 /** Sets this instruction as completed. */
909 void setCompleted() { status.set(Completed); }
911 /** Returns whether or not this instruction is completed. */
912 bool isCompleted() const { return status[Completed]; }
914 /** Marks the result as ready. */
915 void setResultReady() { status.set(ResultReady); }
917 /** Returns whether or not the result is ready. */
918 bool isResultReady() const { return status[ResultReady]; }
920 /** Sets this instruction as ready to issue. */
921 void setCanIssue() { status.set(CanIssue); }
923 /** Returns whether or not this instruction is ready to issue. */
924 bool readyToIssue() const { return status[CanIssue]; }
926 /** Sets this instruction as issued from the IQ. */
927 void setIssued() { status.set(Issued); }
929 /** Returns whether or not this instruction has issued. */
930 bool isIssued() const { return status[Issued]; }
932 /** Sets this instruction as executed. */
933 void setExecuted() { status.set(Executed); }
935 /** Returns whether or not this instruction has executed. */
936 bool isExecuted() const { return status[Executed]; }
938 /** Sets this instruction as ready to commit. */
939 void setCanCommit() { status.set(CanCommit); }
941 /** Clears this instruction as being ready to commit. */
942 void clearCanCommit() { status.reset(CanCommit); }
944 /** Returns whether or not this instruction is ready to commit. */
945 bool readyToCommit() const { return status[CanCommit]; }
947 void setAtCommit() { status.set(AtCommit); }
949 bool isAtCommit() { return status[AtCommit]; }
951 /** Sets this instruction as committed. */
952 void setCommitted() { status.set(Committed); }
954 /** Returns whether or not this instruction is committed. */
955 bool isCommitted() const { return status[Committed]; }
957 /** Sets this instruction as squashed. */
958 void setSquashed() { status.set(Squashed); }
960 /** Returns whether or not this instruction is squashed. */
961 bool isSquashed() const { return status[Squashed]; }
963 /** Temporarily sets this instruction as a serialize before instruction. */
964 void setSerializeBefore() { status.set(SerializeBefore); }
966 /** Clears the serializeBefore part of this instruction. */
967 void clearSerializeBefore() { status.reset(SerializeBefore); }
969 /** Checks if this serializeBefore is only temporarily set. */
970 bool isTempSerializeBefore() { return status[SerializeBefore]; }
972 /** Temporarily sets this instruction as a serialize after instruction. */
973 void setSerializeAfter() { status.set(SerializeAfter); }
975 /** Clears the serializeAfter part of this instruction.*/
976 void clearSerializeAfter() { status.reset(SerializeAfter); }
978 /** Checks if this serializeAfter is only temporarily set. */
979 bool isTempSerializeAfter() { return status[SerializeAfter]; }
981 /** Sets the serialization part of this instruction as handled. */
982 void setSerializeHandled() { status.set(SerializeHandled); }
984 /** Checks if the serialization part of this instruction has been
985 * handled. This does not apply to the temporary serializing
986 * state; it only applies to this instruction's own permanent
989 bool isSerializeHandled() { return status[SerializeHandled]; }
992 /** Instruction effective address.
993 * @todo: Consider if this is necessary or not.
997 /** Whether or not the effective address calculation is completed.
998 * @todo: Consider if this is necessary or not.
1003 /** Whether or not the memory operation is done. */
1007 /** Load queue index. */
1010 /** Store queue index. */
1013 /** Iterator pointing to this BaseDynInst in the list of all insts. */
1016 /** Returns iterator to this instruction in the list of all insts. */
1017 ListIt &getInstListIt() { return instListIt; }
1019 /** Sets iterator for this instruction in the list of all insts. */
1020 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
1022 /** Count of total number of dynamic instructions. */
1023 static int instcount;
1025 /** Dumps out contents of this BaseDynInst. */
1028 /** Dumps out contents of this BaseDynInst into given string. */
1029 void dump(std::string &outstring);
1032 //inline int curCount() { return curCount(); }
1036 #endif // __CPU_BASE_DYN_INST_HH__