2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/faults.hh"
41 #include "arch/isa_traits.hh"
43 #include "arch/types.hh"
44 #include "base/fast_alloc.hh"
45 #include "base/trace.hh"
46 #include "base/types.hh"
47 #include "config/full_system.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/exetrace.hh"
50 #include "cpu/inorder/inorder_trace.hh"
51 #include "cpu/inorder/pipeline_traits.hh"
52 #include "cpu/inorder/resource.hh"
53 #include "cpu/inorder/thread_state.hh"
54 #include "cpu/inst_seq.hh"
55 #include "cpu/op_class.hh"
56 #include "cpu/static_inst.hh"
57 #include "cpu/thread_context.hh"
58 #include "mem/packet.hh"
59 #include "sim/system.hh"
61 #if THE_ISA == ALPHA_ISA
62 #include "arch/alpha/ev5.hh"
67 * Defines a dynamic instruction context for a inorder CPU model.
70 // Forward declaration.
72 class ResourceRequest;
75 class InOrderDynInst : public FastAlloc, public RefCounted
78 // Binary machine instruction type.
79 typedef TheISA::MachInst MachInst;
80 // Extended machine instruction type
81 typedef TheISA::ExtMachInst ExtMachInst;
82 // Logical register index type.
83 typedef TheISA::RegIndex RegIndex;
84 // Integer register type.
85 typedef TheISA::IntReg IntReg;
86 // Floating point register type.
87 typedef TheISA::FloatReg FloatReg;
88 // Floating point register type.
89 typedef TheISA::MiscReg MiscReg;
91 typedef short int PhysRegIndex;
93 /** The refcounted DynInst pointer to be used. In most cases this is
94 * what should be used, and not DynInst*.
96 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
98 // The list of instructions iterator type.
99 typedef std::list<DynInstPtr>::iterator ListIt;
102 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
103 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
107 /** BaseDynInst constructor given a binary instruction.
108 * @param inst The binary instruction.
109 * @param PC The PC of the instruction.
110 * @param pred_PC The predicted next PC.
111 * @param seq_num The sequence number of the instruction.
112 * @param cpu Pointer to the instruction's CPU.
114 InOrderDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
117 /** BaseDynInst constructor given a binary instruction.
118 * @param seq_num The sequence number of the instruction.
119 * @param cpu Pointer to the instruction's CPU.
120 * NOTE: Must set Binary Instrution through Member Function
122 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
123 InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
125 /** BaseDynInst constructor given a StaticInst pointer.
126 * @param _staticInst The StaticInst for this BaseDynInst.
128 InOrderDynInst(StaticInstPtr &_staticInst);
130 /** Skeleton Constructor. */
133 /** InOrderDynInst destructor. */
137 /** The sequence number of the instruction. */
140 /** The sequence number of the instruction. */
141 InstSeqNum bdelaySeqNum;
144 RegDepMapEntry, /// Instruction has been entered onto the RegDepMap
145 IqEntry, /// Instruction is in the IQ
146 RobEntry, /// Instruction is in the ROB
147 LsqEntry, /// Instruction is in the LSQ
148 Completed, /// Instruction has completed
149 ResultReady, /// Instruction has its result
150 CanIssue, /// Instruction can issue and execute
151 Issued, /// Instruction has issued
152 Executed, /// Instruction has executed
153 CanCommit, /// Instruction can commit
154 AtCommit, /// Instruction has reached commit
155 Committed, /// Instruction has committed
156 Squashed, /// Instruction is squashed
157 SquashedInIQ, /// Instruction is squashed in the IQ
158 SquashedInLSQ, /// Instruction is squashed in the LSQ
159 SquashedInROB, /// Instruction is squashed in the ROB
160 RecoverInst, /// Is a recover instruction
161 BlockingInst, /// Is a blocking instruction
162 ThreadsyncWait, /// Is a thread synchronization instruction
163 SerializeBefore, /// Needs to serialize on
164 /// instructions ahead of it
165 SerializeAfter, /// Needs to serialize instructions behind it
166 SerializeHandled, /// Serialization has been handled
170 /** The status of this BaseDynInst. Several bits can be set. */
171 std::bitset<NumStatus> status;
173 /** The thread this instruction is from. */
176 /** data address space ID, for loads & stores. */
179 /** The virtual processor number */
180 short virtProcNumber;
182 /** The StaticInst used by this BaseDynInst. */
183 StaticInstPtr staticInst;
185 /** InstRecord that tracks this instructions. */
186 Trace::InOrderTraceRecord *traceData;
188 /** Pointer to the Impl's CPU object. */
191 /** Pointer to the thread state. */
192 InOrderThreadState *thread;
194 /** The kind of fault this instruction has generated. */
197 /** The memory request. */
200 /** Pointer to the data for the memory access. */
203 /** Data used for a store for operation. */
206 /** Data used for a store for operation. */
209 /** The resource schedule for this inst */
210 ThePipeline::ResSchedule resSched;
212 /** List of active resource requests for this instruction */
213 std::list<ResourceRequest*> reqList;
215 /** The effective virtual address (lds & stores only). */
218 /** The effective physical address. */
221 /** Effective virtual address for a copy source. */
224 /** Effective physical address for a copy source. */
225 Addr copySrcPhysEffAddr;
227 /** The memory request flags (from translation). */
228 unsigned memReqFlags;
230 /** How many source registers are ready. */
233 /** An instruction src/dest has to be one of these types */
239 //@TODO: Naming Convention for Enums?
248 /** Result of an instruction execution */
255 : type(None), tick(0)
259 /** The source of the instruction; assumes for now that there's only one
260 * destination register.
262 InstValue instSrc[MaxInstSrcRegs];
264 /** The result of the instruction; assumes for now that there's only one
265 * destination register.
267 InstResult instResult[MaxInstDestRegs];
269 /** PC of this instruction. */
272 /** Next non-speculative PC. It is not filled in at fetch, but rather
273 * once the target of the branch is truly known (either decode or
278 /** Next next non-speculative PC. It is not filled in at fetch, but rather
279 * once the target of the branch is truly known (either decode or
284 /** Predicted next PC. */
287 /** Predicted next NPC. */
290 /** Predicted next microPC */
293 /** Address to fetch from */
296 /** Address to get/write data from/to */
299 /** Whether or not the source register is ready.
300 * @todo: Not sure this should be here vs the derived class.
302 bool _readySrcRegIdx[MaxInstSrcRegs];
304 /** Physical register index of the destination registers of this
307 PhysRegIndex _destRegIdx[MaxInstDestRegs];
309 /** Physical register index of the source registers of this
312 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
314 /** Physical register index of the previous producers of the
315 * architected destinations.
317 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
321 /* vars to keep track of InstStage's - used for resource sched defn */
322 int nextInstStageNum;
323 ThePipeline::InstStage *currentInstStage;
324 std::list<ThePipeline::InstStage*> instStageList;
327 /** Function to initialize variables in the constructors. */
333 PacketDataPtr splitMemData;
334 RequestPtr splitMemReq;
339 uint8_t split2ndData;
340 PacketDataPtr split2ndDataPtr;
341 unsigned split2ndFlags;
346 ////////////////////////////////////////////////////////////
348 // BASE INSTRUCTION INFORMATION.
350 ////////////////////////////////////////////////////////////
351 std::string instName() { return staticInst->getName(); }
354 void setMachInst(ExtMachInst inst);
356 /** Sets the StaticInst. */
357 void setStaticInst(StaticInstPtr &static_inst);
359 /** Sets the sequence number. */
360 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
362 /** Sets the ASID. */
363 void setASID(short addr_space_id) { asid = addr_space_id; }
365 /** Reads the thread id. */
366 short readTid() { return threadNumber; }
368 /** Sets the thread id. */
369 void setTid(ThreadID tid) { threadNumber = tid; }
371 void setVpn(int id) { virtProcNumber = id; }
373 int readVpn() { return virtProcNumber; }
375 /** Sets the pointer to the thread state. */
376 void setThreadState(InOrderThreadState *state) { thread = state; }
378 /** Returns the thread context. */
379 ThreadContext *tcBase() { return thread->getTC(); }
381 /** Returns the fault type. */
382 Fault getFault() { return fault; }
384 ////////////////////////////////////////////////////////////
386 // INSTRUCTION TYPES - Forward checks to StaticInst object.
388 ////////////////////////////////////////////////////////////
389 bool isNop() const { return staticInst->isNop(); }
390 bool isMemRef() const { return staticInst->isMemRef(); }
391 bool isLoad() const { return staticInst->isLoad(); }
392 bool isStore() const { return staticInst->isStore(); }
393 bool isStoreConditional() const
394 { return staticInst->isStoreConditional(); }
395 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
396 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
397 bool isCopy() const { return staticInst->isCopy(); }
398 bool isInteger() const { return staticInst->isInteger(); }
399 bool isFloating() const { return staticInst->isFloating(); }
400 bool isControl() const { return staticInst->isControl(); }
401 bool isCall() const { return staticInst->isCall(); }
402 bool isReturn() const { return staticInst->isReturn(); }
403 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
404 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
405 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
406 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
407 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
409 bool isThreadSync() const { return staticInst->isThreadSync(); }
410 bool isSerializing() const { return staticInst->isSerializing(); }
411 bool isSerializeBefore() const
412 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
413 bool isSerializeAfter() const
414 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
415 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
416 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
417 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
418 bool isQuiesce() const { return staticInst->isQuiesce(); }
419 bool isIprAccess() const { return staticInst->isIprAccess(); }
420 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
422 /////////////////////////////////////////////
424 // RESOURCE SCHEDULING
426 /////////////////////////////////////////////
428 void setNextStage(int stage_num) { nextStage = stage_num; }
429 int getNextStage() { return nextStage; }
431 ThePipeline::InstStage *addStage();
432 ThePipeline::InstStage *addStage(int stage);
433 ThePipeline::InstStage *currentStage() { return currentInstStage; }
436 /** Add A Entry To Reource Schedule */
437 void addToSched(ThePipeline::ScheduleEntry* sched_entry)
438 { resSched.push(sched_entry); }
441 /** Print Resource Schedule */
442 /** @NOTE: DEBUG ONLY */
445 ThePipeline::ResSchedule tempSched;
446 std::cerr << "\tInst. Res. Schedule: ";
447 while (!resSched.empty()) {
448 std::cerr << '\t' << resSched.top()->stageNum << "-"
449 << resSched.top()->resNum << ", ";
451 tempSched.push(resSched.top());
455 std::cerr << std::endl;
456 resSched = tempSched;
459 /** Return Next Resource Stage To Be Used */
462 if (resSched.empty())
465 return resSched.top()->stageNum;
469 /** Return Next Resource To Be Used */
472 if (resSched.empty())
475 return resSched.top()->resNum;
478 /** Remove & Deallocate a schedule entry */
481 if (!resSched.empty()) {
482 ThePipeline::ScheduleEntry* sked = resSched.top();
491 /** Release a Resource Request (Currently Unused) */
492 void releaseReq(ResourceRequest* req);
494 ////////////////////////////////////////////
496 // INSTRUCTION EXECUTION
498 ////////////////////////////////////////////
499 /** Returns the opclass of this instruction. */
500 OpClass opClass() const { return staticInst->opClass(); }
502 /** Executes the instruction.*/
507 unsigned getCurResSlot() { return curResSlot; }
509 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
511 /** Calls a syscall. */
513 /** Calls hardware return from error interrupt. */
515 /** Traps to handle specified fault. */
516 void trap(Fault fault);
517 bool simPalCheck(int palFunc);
519 /** Calls a syscall. */
520 void syscall(int64_t callnum);
522 void prefetch(Addr addr, unsigned flags);
523 void writeHint(Addr addr, int size, unsigned flags);
524 Fault copySrcTranslate(Addr src);
525 Fault copy(Addr dest);
527 ////////////////////////////////////////////////////////////
529 // MULTITHREADING INTERFACE TO CPU MODELS
531 ////////////////////////////////////////////////////////////
532 virtual void deallocateContext(int thread_num);
534 ////////////////////////////////////////////////////////////
536 // PROGRAM COUNTERS - PC/NPC/NPC
538 ////////////////////////////////////////////////////////////
539 /** Read the PC of this instruction. */
540 const Addr readPC() const { return PC; }
542 /** Sets the PC of this instruction. */
543 void setPC(Addr pc) { PC = pc; }
545 /** Returns the next PC. This could be the speculative next PC if it is
546 * called prior to the actual branch target being calculated.
548 Addr readNextPC() { return nextPC; }
550 /** Set the next PC of this instruction (its actual target). */
551 void setNextPC(uint64_t val) { nextPC = val; }
553 /** Returns the next NPC. This could be the speculative next NPC if it is
554 * called prior to the actual branch target being calculated.
558 #if ISA_HAS_DELAY_SLOT
561 return nextPC + sizeof(TheISA::MachInst);
565 /** Set the next PC of this instruction (its actual target). */
566 void setNextNPC(uint64_t val) { nextNPC = val; }
568 ////////////////////////////////////////////////////////////
572 ////////////////////////////////////////////////////////////
573 /** Set the predicted target of this current instruction. */
574 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
576 /** Returns the predicted target of the branch. */
577 Addr readPredTarg() { return predPC; }
579 /** Returns the predicted PC immediately after the branch. */
580 Addr readPredPC() { return predPC; }
582 /** Returns the predicted PC two instructions after the branch */
583 Addr readPredNPC() { return predNPC; }
585 /** Returns the predicted micro PC after the branch */
586 Addr readPredMicroPC() { return predMicroPC; }
588 /** Returns whether the instruction was predicted taken or not. */
589 bool predTaken() { return predictTaken; }
591 /** Returns whether the instruction mispredicted. */
594 #if ISA_HAS_DELAY_SLOT
595 return predPC != nextNPC;
597 return predPC != nextPC;
601 /** Returns whether the instruction mispredicted. */
602 bool mistargeted() { return predPC != nextNPC; }
604 /** Returns the branch target address. */
605 Addr branchTarget() const { return staticInst->branchTarget(PC); }
607 /** Checks whether or not this instruction has had its branch target
608 * calculated yet. For now it is not utilized and is hacked to be
610 * @todo: Actually use this instruction.
612 bool doneTargCalc() { return false; }
614 void setBranchPred(bool prediction) { predictTaken = prediction; }
620 bool procDelaySlotOnMispred;
622 ////////////////////////////////////////////
626 ////////////////////////////////////////////
628 * Does a read to a given address.
629 * @param addr The address to read.
630 * @param data The read's data is written into this parameter.
631 * @param flags The request's flags.
632 * @return Returns any fault due to the read.
635 Fault read(Addr addr, T &data, unsigned flags);
638 * Does a write to a given address.
639 * @param data The data to be written.
640 * @param addr The address to write to.
641 * @param flags The request's flags.
642 * @param res The result of the write (for load locked/store conditionals).
643 * @return Returns any fault due to the write.
646 Fault write(T data, Addr addr, unsigned flags,
649 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory Access
650 * Only valid for memory operations.
654 /** Completes a memory access - Only valid for memory operations. */
655 Fault completeAcc(Packet *pkt);
657 /** Calculates Eff. Addr. part of a memory instruction. */
660 /** Read Effective Address from instruction & do memory access */
663 RequestPtr fetchMemReq;
664 RequestPtr dataMemReq;
669 { return memAddrReady; }
671 void setMemAddr(Addr addr)
672 { memAddr = addr; memAddrReady = true;}
675 { memAddrReady = false;}
680 /** Sets the effective address. */
681 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
683 /** Returns the effective address. */
684 const Addr &getEA() const { return instEffAddr; }
686 /** Returns whether or not the eff. addr. calculation has been completed. */
687 bool doneEACalc() { return eaCalcDone; }
689 /** Returns whether or not the eff. addr. source registers are ready.
690 * Assume that src registers 1..n-1 are the ones that the
691 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
696 for (int i = 1; i < numSrcRegs(); ++i) {
697 if (!_readySrcRegIdx[i])
704 //////////////////////////////////////////////////
706 // SOURCE-DESTINATION REGISTER INDEXING
708 //////////////////////////////////////////////////
709 /** Returns the number of source registers. */
710 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
712 /** Returns the number of destination registers. */
713 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
715 // the following are used to track physical register usage
716 // for machines with separate int & FP reg files
717 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
718 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
720 /** Returns the logical register index of the i'th destination register. */
721 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
723 /** Returns the logical register index of the i'th source register. */
724 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
726 //////////////////////////////////////////////////
728 // RENAME/PHYSICAL REGISTER FILE SUPPORT
730 //////////////////////////////////////////////////
731 /** Returns the physical register index of the i'th destination
734 PhysRegIndex renamedDestRegIdx(int idx) const
736 return _destRegIdx[idx];
739 /** Returns the physical register index of the i'th source register. */
740 PhysRegIndex renamedSrcRegIdx(int idx) const
742 return _srcRegIdx[idx];
745 /** Returns the physical register index of the previous physical register
746 * that remapped to the same logical register index.
748 PhysRegIndex prevDestRegIdx(int idx) const
750 return _prevDestRegIdx[idx];
753 /** Returns if a source register is ready. */
754 bool isReadySrcRegIdx(int idx) const
756 return this->_readySrcRegIdx[idx];
759 /** Records that one of the source registers is ready. */
760 void markSrcRegReady()
762 if (++readyRegs == numSrcRegs()) {
763 status.set(CanIssue);
767 /** Marks a specific register as ready. */
768 void markSrcRegReady(RegIndex src_idx)
770 _readySrcRegIdx[src_idx] = true;
775 /** Renames a destination register to a physical register. Also records
776 * the previous physical register that the logical register mapped to.
778 void renameDestReg(int idx,
779 PhysRegIndex renamed_dest,
780 PhysRegIndex previous_rename)
782 _destRegIdx[idx] = renamed_dest;
783 _prevDestRegIdx[idx] = previous_rename;
786 /** Renames a source logical register to the physical register which
787 * has/will produce that logical register's result.
788 * @todo: add in whether or not the source register is ready.
790 void renameSrcReg(int idx, PhysRegIndex renamed_src)
792 _srcRegIdx[idx] = renamed_src;
796 PhysRegIndex readDestRegIdx(int idx)
798 return _destRegIdx[idx];
801 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
803 _destRegIdx[idx] = dest_idx;
806 int getDestIdxNum(PhysRegIndex dest_idx)
808 for (int i=0; i < staticInst->numDestRegs(); i++) {
809 if (_destRegIdx[i] == dest_idx)
816 PhysRegIndex readSrcRegIdx(int idx)
818 return _srcRegIdx[idx];
821 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
823 _srcRegIdx[idx] = src_idx;
826 int getSrcIdxNum(PhysRegIndex src_idx)
828 for (int i=0; i < staticInst->numSrcRegs(); i++) {
829 if (_srcRegIdx[i] == src_idx)
836 ////////////////////////////////////////////////////
838 // SOURCE-DESTINATION REGISTER VALUES
840 ////////////////////////////////////////////////////
842 /** Functions that sets an integer or floating point
843 * source register to a value. */
844 void setIntSrc(int idx, uint64_t val);
845 void setFloatSrc(int idx, FloatReg val);
846 void setFloatRegBitsSrc(int idx, uint64_t val);
848 uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
849 uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
851 /** These Instructions read a integer/float/misc. source register
852 * value in the instruction. The instruction's execute function will
853 * call these and it is the interface that is used by the ISA descr.
854 * language (which is why the name isnt readIntSrc(...)) Note: That
855 * the source reg. value is set using the setSrcReg() function.
857 IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
858 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
859 TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
860 MiscReg readMiscReg(int misc_reg);
861 MiscReg readMiscRegNoEffect(int misc_reg);
862 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
863 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
865 /** Returns the result value instruction. */
866 ResultType resultType(int idx)
868 return instResult[idx].type;
871 uint64_t readIntResult(int idx)
873 return instResult[idx].val.integer;
876 /** Depending on type, return Float or Double */
877 double readFloatResult(int idx)
879 return instResult[idx].val.dbl;
882 Tick readResultTime(int idx) { return instResult[idx].tick; }
884 uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
886 /** This is the interface that an instruction will use to write
887 * it's destination register.
889 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
890 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
891 void setFloatRegOperandBits(const StaticInst *si, int idx,
892 TheISA::FloatRegBits val);
893 void setMiscReg(int misc_reg, const MiscReg &val);
894 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
895 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
896 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val);
898 virtual uint64_t readRegOtherThread(unsigned idx,
899 ThreadID tid = InvalidThreadID);
900 virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
901 ThreadID tid = InvalidThreadID);
903 /** Sets the number of consecutive store conditional failures. */
904 void setStCondFailures(unsigned sc_failures)
905 { thread->storeCondFailures = sc_failures; }
907 //////////////////////////////////////////////////////////////
909 // INSTRUCTION STATUS FLAGS (READ/SET)
911 //////////////////////////////////////////////////////////////
912 /** Sets this instruction as entered on the CPU Reg Dep Map */
913 void setRegDepEntry() { status.set(RegDepMapEntry); }
915 /** Returns whether or not the entry is on the CPU Reg Dep Map */
916 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
918 /** Sets this instruction as completed. */
919 void setCompleted() { status.set(Completed); }
921 /** Returns whether or not this instruction is completed. */
922 bool isCompleted() const { return status[Completed]; }
924 /** Marks the result as ready. */
925 void setResultReady() { status.set(ResultReady); }
927 /** Returns whether or not the result is ready. */
928 bool isResultReady() const { return status[ResultReady]; }
930 /** Sets this instruction as ready to issue. */
931 void setCanIssue() { status.set(CanIssue); }
933 /** Returns whether or not this instruction is ready to issue. */
934 bool readyToIssue() const { return status[CanIssue]; }
936 /** Sets this instruction as issued from the IQ. */
937 void setIssued() { status.set(Issued); }
939 /** Returns whether or not this instruction has issued. */
940 bool isIssued() const { return status[Issued]; }
942 /** Sets this instruction as executed. */
943 void setExecuted() { status.set(Executed); }
945 /** Returns whether or not this instruction has executed. */
946 bool isExecuted() const { return status[Executed]; }
948 /** Sets this instruction as ready to commit. */
949 void setCanCommit() { status.set(CanCommit); }
951 /** Clears this instruction as being ready to commit. */
952 void clearCanCommit() { status.reset(CanCommit); }
954 /** Returns whether or not this instruction is ready to commit. */
955 bool readyToCommit() const { return status[CanCommit]; }
957 void setAtCommit() { status.set(AtCommit); }
959 bool isAtCommit() { return status[AtCommit]; }
961 /** Sets this instruction as committed. */
962 void setCommitted() { status.set(Committed); }
964 /** Returns whether or not this instruction is committed. */
965 bool isCommitted() const { return status[Committed]; }
967 /** Sets this instruction as squashed. */
968 void setSquashed() { status.set(Squashed); }
970 /** Returns whether or not this instruction is squashed. */
971 bool isSquashed() const { return status[Squashed]; }
973 /** Temporarily sets this instruction as a serialize before instruction. */
974 void setSerializeBefore() { status.set(SerializeBefore); }
976 /** Clears the serializeBefore part of this instruction. */
977 void clearSerializeBefore() { status.reset(SerializeBefore); }
979 /** Checks if this serializeBefore is only temporarily set. */
980 bool isTempSerializeBefore() { return status[SerializeBefore]; }
982 /** Temporarily sets this instruction as a serialize after instruction. */
983 void setSerializeAfter() { status.set(SerializeAfter); }
985 /** Clears the serializeAfter part of this instruction.*/
986 void clearSerializeAfter() { status.reset(SerializeAfter); }
988 /** Checks if this serializeAfter is only temporarily set. */
989 bool isTempSerializeAfter() { return status[SerializeAfter]; }
991 /** Sets the serialization part of this instruction as handled. */
992 void setSerializeHandled() { status.set(SerializeHandled); }
994 /** Checks if the serialization part of this instruction has been
995 * handled. This does not apply to the temporary serializing
996 * state; it only applies to this instruction's own permanent
999 bool isSerializeHandled() { return status[SerializeHandled]; }
1002 /** Instruction effective address.
1003 * @todo: Consider if this is necessary or not.
1007 /** Whether or not the effective address calculation is completed.
1008 * @todo: Consider if this is necessary or not.
1013 /** Whether or not the memory operation is done. */
1017 /** Load queue index. */
1020 /** Store queue index. */
1023 /** Iterator pointing to this BaseDynInst in the list of all insts. */
1026 /** Returns iterator to this instruction in the list of all insts. */
1027 ListIt &getInstListIt() { return instListIt; }
1029 /** Sets iterator for this instruction in the list of all insts. */
1030 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
1032 /** Count of total number of dynamic instructions. */
1033 static int instcount;
1035 /** Dumps out contents of this BaseDynInst. */
1038 /** Dumps out contents of this BaseDynInst into given string. */
1039 void dump(std::string &outstring);
1042 //inline int curCount() { return curCount(); }
1046 #endif // __CPU_BASE_DYN_INST_HH__