2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/isa_traits.hh"
41 #include "arch/faults.hh"
42 #include "arch/types.hh"
44 #include "base/fast_alloc.hh"
45 #include "base/trace.hh"
46 #include "cpu/inorder/inorder_trace.hh"
47 #include "config/full_system.hh"
48 #include "cpu/thread_context.hh"
49 #include "cpu/exetrace.hh"
50 #include "cpu/inst_seq.hh"
51 #include "cpu/op_class.hh"
52 #include "cpu/static_inst.hh"
53 #include "cpu/inorder/thread_state.hh"
54 #include "cpu/inorder/resource.hh"
55 #include "cpu/inorder/pipeline_traits.hh"
56 #include "mem/packet.hh"
57 #include "sim/system.hh"
61 * Defines a dynamic instruction context for a inorder CPU model.
64 // Forward declaration.
66 class ResourceRequest;
68 class InOrderDynInst : public FastAlloc, public RefCounted
71 // Binary machine instruction type.
72 typedef TheISA::MachInst MachInst;
73 // Extended machine instruction type
74 typedef TheISA::ExtMachInst ExtMachInst;
75 // Logical register index type.
76 typedef TheISA::RegIndex RegIndex;
77 // Integer register type.
78 typedef TheISA::IntReg IntReg;
79 // Floating point register type.
80 typedef TheISA::FloatReg FloatReg;
81 // Floating point register type.
82 typedef TheISA::MiscReg MiscReg;
84 typedef short int PhysRegIndex;
86 /** The refcounted DynInst pointer to be used. In most cases this is
87 * what should be used, and not DynInst*.
89 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
91 // The list of instructions iterator type.
92 typedef std::list<DynInstPtr>::iterator ListIt;
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
100 /** BaseDynInst constructor given a binary instruction.
101 * @param inst The binary instruction.
102 * @param PC The PC of the instruction.
103 * @param pred_PC The predicted next PC.
104 * @param seq_num The sequence number of the instruction.
105 * @param cpu Pointer to the instruction's CPU.
107 InOrderDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
110 /** BaseDynInst constructor given a binary instruction.
111 * @param seq_num The sequence number of the instruction.
112 * @param cpu Pointer to the instruction's CPU.
113 * NOTE: Must set Binary Instrution through Member Function
115 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state, InstSeqNum seq_num,
118 /** BaseDynInst constructor given a StaticInst pointer.
119 * @param _staticInst The StaticInst for this BaseDynInst.
121 InOrderDynInst(StaticInstPtr &_staticInst);
123 /** Skeleton Constructor. */
126 /** InOrderDynInst destructor. */
130 /** The sequence number of the instruction. */
133 /** The sequence number of the instruction. */
134 InstSeqNum bdelaySeqNum;
137 RegDepMapEntry, /// Instruction has been entered onto the RegDepMap
138 IqEntry, /// Instruction is in the IQ
139 RobEntry, /// Instruction is in the ROB
140 LsqEntry, /// Instruction is in the LSQ
141 Completed, /// Instruction has completed
142 ResultReady, /// Instruction has its result
143 CanIssue, /// Instruction can issue and execute
144 Issued, /// Instruction has issued
145 Executed, /// Instruction has executed
146 CanCommit, /// Instruction can commit
147 AtCommit, /// Instruction has reached commit
148 Committed, /// Instruction has committed
149 Squashed, /// Instruction is squashed
150 SquashedInIQ, /// Instruction is squashed in the IQ
151 SquashedInLSQ, /// Instruction is squashed in the LSQ
152 SquashedInROB, /// Instruction is squashed in the ROB
153 RecoverInst, /// Is a recover instruction
154 BlockingInst, /// Is a blocking instruction
155 ThreadsyncWait, /// Is a thread synchronization instruction
156 SerializeBefore, /// Needs to serialize on
157 /// instructions ahead of it
158 SerializeAfter, /// Needs to serialize instructions behind it
159 SerializeHandled, /// Serialization has been handled
163 /** The status of this BaseDynInst. Several bits can be set. */
164 std::bitset<NumStatus> status;
166 /** The thread this instruction is from. */
169 /** data address space ID, for loads & stores. */
172 /** The virtual processor number */
173 short virtProcNumber;
175 /** The StaticInst used by this BaseDynInst. */
176 StaticInstPtr staticInst;
178 /** InstRecord that tracks this instructions. */
179 Trace::InOrderTraceRecord *traceData;
181 /** Pointer to the Impl's CPU object. */
184 /** Pointer to the thread state. */
185 InOrderThreadState *thread;
187 /** The kind of fault this instruction has generated. */
190 /** The memory request. */
193 /** Pointer to the data for the memory access. */
196 /** Data used for a store for operation. */
199 /** Data used for a store for operation. */
202 /** The resource schedule for this inst */
203 ThePipeline::ResSchedule resSched;
205 /** List of active resource requests for this instruction */
206 std::list<ResourceRequest*> reqList;
208 /** The effective virtual address (lds & stores only). */
211 /** The effective physical address. */
214 /** Effective virtual address for a copy source. */
217 /** Effective physical address for a copy source. */
218 Addr copySrcPhysEffAddr;
220 /** The memory request flags (from translation). */
221 unsigned memReqFlags;
223 /** How many source registers are ready. */
226 /** An instruction src/dest has to be one of these types */
233 /** Result of an instruction execution */
239 /** The source of the instruction; assumes for now that there's only one
240 * destination register.
242 InstValue instSrc[MaxInstSrcRegs];
244 /** The result of the instruction; assumes for now that there's only one
245 * destination register.
247 InstResult instResult[MaxInstDestRegs];
249 /** PC of this instruction. */
252 /** Next non-speculative PC. It is not filled in at fetch, but rather
253 * once the target of the branch is truly known (either decode or
258 /** Next next non-speculative PC. It is not filled in at fetch, but rather
259 * once the target of the branch is truly known (either decode or
264 /** Predicted next PC. */
267 /** Predicted next NPC. */
270 /** Predicted next microPC */
273 /** Address to fetch from */
276 /** Address to get/write data from/to */
279 /** Whether or not the source register is ready.
280 * @todo: Not sure this should be here vs the derived class.
282 bool _readySrcRegIdx[MaxInstSrcRegs];
284 /** Physical register index of the destination registers of this
287 PhysRegIndex _destRegIdx[MaxInstDestRegs];
289 /** Physical register index of the source registers of this
292 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
294 /** Physical register index of the previous producers of the
295 * architected destinations.
297 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
301 /* vars to keep track of InstStage's - used for resource sched defn */
302 int nextInstStageNum;
303 ThePipeline::InstStage *currentInstStage;
304 std::list<ThePipeline::InstStage*> instStageList;
307 /** Function to initialize variables in the constructors. */
313 ////////////////////////////////////////////////////////////
315 // BASE INSTRUCTION INFORMATION.
317 ////////////////////////////////////////////////////////////
318 void setMachInst(ExtMachInst inst);
320 /** Sets the StaticInst. */
321 void setStaticInst(StaticInstPtr &static_inst);
323 /** Sets the sequence number. */
324 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
326 /** Sets the ASID. */
327 void setASID(short addr_space_id) { asid = addr_space_id; }
329 /** Reads the thread id. */
330 short readTid() { return threadNumber; }
332 /** Sets the thread id. */
333 void setTid(unsigned tid) { threadNumber = tid; }
335 void setVpn(int id) { virtProcNumber = id; }
337 int readVpn() { return virtProcNumber; }
339 /** Sets the pointer to the thread state. */
340 void setThreadState(InOrderThreadState *state) { thread = state; }
342 /** Returns the thread context. */
343 ThreadContext *tcBase() { return thread->getTC(); }
345 /** Returns the fault type. */
346 Fault getFault() { return fault; }
348 ////////////////////////////////////////////////////////////
350 // INSTRUCTION TYPES - Forward checks to StaticInst object.
352 ////////////////////////////////////////////////////////////
353 bool isNop() const { return staticInst->isNop(); }
354 bool isMemRef() const { return staticInst->isMemRef(); }
355 bool isLoad() const { return staticInst->isLoad(); }
356 bool isStore() const { return staticInst->isStore(); }
357 bool isStoreConditional() const
358 { return staticInst->isStoreConditional(); }
359 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
360 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
361 bool isCopy() const { return staticInst->isCopy(); }
362 bool isInteger() const { return staticInst->isInteger(); }
363 bool isFloating() const { return staticInst->isFloating(); }
364 bool isControl() const { return staticInst->isControl(); }
365 bool isCall() const { return staticInst->isCall(); }
366 bool isReturn() const { return staticInst->isReturn(); }
367 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
368 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
369 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
370 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
371 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
373 bool isThreadSync() const { return staticInst->isThreadSync(); }
374 bool isSerializing() const { return staticInst->isSerializing(); }
375 bool isSerializeBefore() const
376 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
377 bool isSerializeAfter() const
378 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
379 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
380 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
381 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
382 bool isQuiesce() const { return staticInst->isQuiesce(); }
383 bool isIprAccess() const { return staticInst->isIprAccess(); }
384 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
386 /////////////////////////////////////////////
388 // RESOURCE SCHEDULING
390 /////////////////////////////////////////////
392 void setNextStage(int stage_num) { nextStage = stage_num; }
393 int getNextStage() { return nextStage; }
395 ThePipeline::InstStage *addStage();
396 ThePipeline::InstStage *addStage(int stage);
397 ThePipeline::InstStage *currentStage() { return currentInstStage; }
400 /** Add A Entry To Reource Schedule */
401 void addToSched(ThePipeline::ScheduleEntry* sched_entry)
402 { resSched.push(sched_entry); }
405 /** Print Resource Schedule */
408 using namespace ThePipeline;
410 ResSchedule tempSched;
411 std::cerr << "\tInst. Res. Schedule: ";
412 while (!resSched.empty()) {
413 std::cerr << '\t' << resSched.top()->stageNum << "-"
414 << resSched.top()->resNum << ", ";
416 tempSched.push(resSched.top());
420 std::cerr << std::endl;
421 resSched = tempSched;
424 /** Return Next Resource Stage To Be Used */
427 if (resSched.empty())
430 return resSched.top()->stageNum;
434 /** Return Next Resource To Be Used */
437 if (resSched.empty())
440 return resSched.top()->resNum;
443 /** Remove & Deallocate a schedule entry */
446 if (!resSched.empty()) {
447 ThePipeline::ScheduleEntry* sked = resSched.top();
453 /** Release a Resource Request (Currently Unused) */
454 void releaseReq(ResourceRequest* req);
456 ////////////////////////////////////////////
458 // INSTRUCTION EXECUTION
460 ////////////////////////////////////////////
461 /** Returns the opclass of this instruction. */
462 OpClass opClass() const { return staticInst->opClass(); }
464 /** Executes the instruction.*/
469 unsigned getCurResSlot() { return curResSlot; }
471 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
473 /** Calls a syscall. */
474 void syscall(int64_t callnum);
475 void prefetch(Addr addr, unsigned flags);
476 void writeHint(Addr addr, int size, unsigned flags);
477 Fault copySrcTranslate(Addr src);
478 Fault copy(Addr dest);
480 ////////////////////////////////////////////////////////////
482 // MULTITHREADING INTERFACE TO CPU MODELS
484 ////////////////////////////////////////////////////////////
485 virtual void deallocateContext(int thread_num);
487 virtual void enableVirtProcElement(unsigned vpe);
488 virtual void disableVirtProcElement(unsigned vpe);
490 virtual void enableMultiThreading(unsigned vpe);
491 virtual void disableMultiThreading(unsigned vpe);
493 ////////////////////////////////////////////////////////////
495 // PROGRAM COUNTERS - PC/NPC/NPC
497 ////////////////////////////////////////////////////////////
498 /** Read the PC of this instruction. */
499 const Addr readPC() const { return PC; }
501 /** Sets the PC of this instruction. */
502 void setPC(Addr pc) { PC = pc; }
504 /** Returns the next PC. This could be the speculative next PC if it is
505 * called prior to the actual branch target being calculated.
507 Addr readNextPC() { return nextPC; }
509 /** Set the next PC of this instruction (its actual target). */
510 void setNextPC(uint64_t val) { nextPC = val; }
512 /** Returns the next NPC. This could be the speculative next NPC if it is
513 * called prior to the actual branch target being calculated.
517 #if ISA_HAS_DELAY_SLOT
520 return nextPC + sizeof(TheISA::MachInst);
524 /** Set the next PC of this instruction (its actual target). */
525 void setNextNPC(uint64_t val) { nextNPC = val; }
527 ////////////////////////////////////////////////////////////
531 ////////////////////////////////////////////////////////////
532 /** Set the predicted target of this current instruction. */
533 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
535 /** Returns the predicted target of the branch. */
536 Addr readPredTarg() { return predPC; }
538 /** Returns the predicted PC immediately after the branch. */
539 Addr readPredPC() { return predPC; }
541 /** Returns the predicted PC two instructions after the branch */
542 Addr readPredNPC() { return predNPC; }
544 /** Returns the predicted micro PC after the branch */
545 Addr readPredMicroPC() { return predMicroPC; }
547 /** Returns whether the instruction was predicted taken or not. */
548 bool predTaken() { return predictTaken; }
550 /** Returns whether the instruction mispredicted. */
553 #if ISA_HAS_DELAY_SLOT
554 return predPC != nextNPC;
556 return predPC != nextPC;
560 /** Returns whether the instruction mispredicted. */
561 bool mistargeted() { return predPC != nextNPC; }
563 /** Returns the branch target address. */
564 Addr branchTarget() const { return staticInst->branchTarget(PC); }
566 /** Checks whether or not this instruction has had its branch target
567 * calculated yet. For now it is not utilized and is hacked to be
569 * @todo: Actually use this instruction.
571 bool doneTargCalc() { return false; }
573 void setBranchPred(bool prediction) { predictTaken = prediction; }
579 bool procDelaySlotOnMispred;
581 ////////////////////////////////////////////
585 ////////////////////////////////////////////
587 * Does a read to a given address.
588 * @param addr The address to read.
589 * @param data The read's data is written into this parameter.
590 * @param flags The request's flags.
591 * @return Returns any fault due to the read.
594 Fault read(Addr addr, T &data, unsigned flags);
597 * Does a write to a given address.
598 * @param data The data to be written.
599 * @param addr The address to write to.
600 * @param flags The request's flags.
601 * @param res The result of the write (for load locked/store conditionals).
602 * @return Returns any fault due to the write.
605 Fault write(T data, Addr addr, unsigned flags,
608 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory Access
609 * Only valid for memory operations.
613 /** Completes a memory access - Only valid for memory operations. */
614 Fault completeAcc(Packet *pkt);
616 /** Calculates Eff. Addr. part of a memory instruction. */
619 /** Read Effective Address from instruction & do memory access */
627 { return memAddrReady; }
629 void setMemAddr(Addr addr)
630 { memAddr = addr; memAddrReady = true;}
633 { memAddrReady = false;}
638 int getMemAccSize() { return staticInst->memAccSize(this); }
640 int getMemFlags() { return staticInst->memAccFlags(); }
642 /** Sets the effective address. */
643 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
645 /** Returns the effective address. */
646 const Addr &getEA() const { return instEffAddr; }
648 /** Returns whether or not the eff. addr. calculation has been completed. */
649 bool doneEACalc() { return eaCalcDone; }
651 /** Returns whether or not the eff. addr. source registers are ready.
652 * Assume that src registers 1..n-1 are the ones that the
653 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
658 for (int i = 1; i < numSrcRegs(); ++i) {
659 if (!_readySrcRegIdx[i])
666 //////////////////////////////////////////////////
668 // SOURCE-DESTINATION REGISTER INDEXING
670 //////////////////////////////////////////////////
671 /** Returns the number of source registers. */
672 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
674 /** Returns the number of destination registers. */
675 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
677 // the following are used to track physical register usage
678 // for machines with separate int & FP reg files
679 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
680 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
682 /** Returns the logical register index of the i'th destination register. */
683 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
685 /** Returns the logical register index of the i'th source register. */
686 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
688 //////////////////////////////////////////////////
690 // RENAME/PHYSICAL REGISTER FILE SUPPORT
692 //////////////////////////////////////////////////
693 /** Returns the physical register index of the i'th destination
696 PhysRegIndex renamedDestRegIdx(int idx) const
698 return _destRegIdx[idx];
701 /** Returns the physical register index of the i'th source register. */
702 PhysRegIndex renamedSrcRegIdx(int idx) const
704 return _srcRegIdx[idx];
707 /** Returns the physical register index of the previous physical register
708 * that remapped to the same logical register index.
710 PhysRegIndex prevDestRegIdx(int idx) const
712 return _prevDestRegIdx[idx];
715 /** Returns if a source register is ready. */
716 bool isReadySrcRegIdx(int idx) const
718 return this->_readySrcRegIdx[idx];
721 /** Records that one of the source registers is ready. */
722 void markSrcRegReady()
724 if (++readyRegs == numSrcRegs()) {
725 status.set(CanIssue);
729 /** Marks a specific register as ready. */
730 void markSrcRegReady(RegIndex src_idx)
732 _readySrcRegIdx[src_idx] = true;
737 /** Renames a destination register to a physical register. Also records
738 * the previous physical register that the logical register mapped to.
740 void renameDestReg(int idx,
741 PhysRegIndex renamed_dest,
742 PhysRegIndex previous_rename)
744 _destRegIdx[idx] = renamed_dest;
745 _prevDestRegIdx[idx] = previous_rename;
748 /** Renames a source logical register to the physical register which
749 * has/will produce that logical register's result.
750 * @todo: add in whether or not the source register is ready.
752 void renameSrcReg(int idx, PhysRegIndex renamed_src)
754 _srcRegIdx[idx] = renamed_src;
758 PhysRegIndex readDestRegIdx(int idx)
760 return _destRegIdx[idx];
763 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
765 _destRegIdx[idx] = dest_idx;
768 int getDestIdxNum(PhysRegIndex dest_idx)
770 for (int i=0; i < staticInst->numDestRegs(); i++) {
771 if (_destRegIdx[i] == dest_idx)
778 PhysRegIndex readSrcRegIdx(int idx)
780 return _srcRegIdx[idx];
783 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
785 _srcRegIdx[idx] = src_idx;
788 int getSrcIdxNum(PhysRegIndex src_idx)
790 for (int i=0; i < staticInst->numSrcRegs(); i++) {
791 if (_srcRegIdx[i] == src_idx)
798 ////////////////////////////////////////////////////
800 // SOURCE-DESTINATION REGISTER VALUES
802 ////////////////////////////////////////////////////
804 /** Functions that sets an integer or floating point
805 * source register to a value. */
806 void setIntSrc(int idx, uint64_t val);
807 void setFloatSrc(int idx, FloatReg val, int width = 32);
808 void setFloatRegBitsSrc(int idx, uint64_t val);
810 uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
811 uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
813 /** These Instructions read a integer/float/misc. source register
814 * value in the instruction. The instruction's execute function will
815 * call these and it is the interface that is used by the ISA descr.
816 * language (which is why the name isnt readIntSrc(...)) Note: That
817 * the source reg. value is set using the setSrcReg() function.
819 IntReg readIntRegOperand(const StaticInst *si, int idx, unsigned tid=0);
820 FloatReg readFloatRegOperand(const StaticInst *si, int idx,
821 int width = TheISA::SingleWidth);
822 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
823 int width = TheISA::SingleWidth);
824 MiscReg readMiscReg(int misc_reg);
825 MiscReg readMiscRegNoEffect(int misc_reg);
826 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
827 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
829 /** Returns the result value instruction. */
830 uint64_t readIntResult(int idx) { return instResult[idx].val.integer; }
831 float readFloatResult(int idx) { return instResult[idx].val.fp; }
832 double readDoubleResult(int idx) { return instResult[idx].val.dbl; }
833 Tick readResultTime(int idx) { return instResult[idx].tick; }
835 uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
837 /** This is the interface that an instruction will use to write
838 * it's destination register.
840 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
841 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
842 int width = TheISA::SingleWidth);
843 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val,
844 int width = TheISA::SingleWidth);
845 void setMiscReg(int misc_reg, const MiscReg &val);
846 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
847 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
848 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val);
850 virtual uint64_t readRegOtherThread(unsigned idx, int tid = -1);
851 virtual void setRegOtherThread(unsigned idx, const uint64_t &val, int tid = -1);
853 /** Sets the number of consecutive store conditional failures. */
854 void setStCondFailures(unsigned sc_failures)
855 { thread->storeCondFailures = sc_failures; }
857 //////////////////////////////////////////////////////////////
859 // INSTRUCTION STATUS FLAGS (READ/SET)
861 //////////////////////////////////////////////////////////////
862 /** Sets this instruction as entered on the CPU Reg Dep Map */
863 void setRegDepEntry() { status.set(RegDepMapEntry); }
865 /** Returns whether or not the entry is on the CPU Reg Dep Map */
866 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
868 /** Sets this instruction as completed. */
869 void setCompleted() { status.set(Completed); }
871 /** Returns whether or not this instruction is completed. */
872 bool isCompleted() const { return status[Completed]; }
874 /** Marks the result as ready. */
875 void setResultReady() { status.set(ResultReady); }
877 /** Returns whether or not the result is ready. */
878 bool isResultReady() const { return status[ResultReady]; }
880 /** Sets this instruction as ready to issue. */
881 void setCanIssue() { status.set(CanIssue); }
883 /** Returns whether or not this instruction is ready to issue. */
884 bool readyToIssue() const { return status[CanIssue]; }
886 /** Sets this instruction as issued from the IQ. */
887 void setIssued() { status.set(Issued); }
889 /** Returns whether or not this instruction has issued. */
890 bool isIssued() const { return status[Issued]; }
892 /** Sets this instruction as executed. */
893 void setExecuted() { status.set(Executed); }
895 /** Returns whether or not this instruction has executed. */
896 bool isExecuted() const { return status[Executed]; }
898 /** Sets this instruction as ready to commit. */
899 void setCanCommit() { status.set(CanCommit); }
901 /** Clears this instruction as being ready to commit. */
902 void clearCanCommit() { status.reset(CanCommit); }
904 /** Returns whether or not this instruction is ready to commit. */
905 bool readyToCommit() const { return status[CanCommit]; }
907 void setAtCommit() { status.set(AtCommit); }
909 bool isAtCommit() { return status[AtCommit]; }
911 /** Sets this instruction as committed. */
912 void setCommitted() { status.set(Committed); }
914 /** Returns whether or not this instruction is committed. */
915 bool isCommitted() const { return status[Committed]; }
917 /** Sets this instruction as squashed. */
918 void setSquashed() { status.set(Squashed); }
920 /** Returns whether or not this instruction is squashed. */
921 bool isSquashed() const { return status[Squashed]; }
923 /** Temporarily sets this instruction as a serialize before instruction. */
924 void setSerializeBefore() { status.set(SerializeBefore); }
926 /** Clears the serializeBefore part of this instruction. */
927 void clearSerializeBefore() { status.reset(SerializeBefore); }
929 /** Checks if this serializeBefore is only temporarily set. */
930 bool isTempSerializeBefore() { return status[SerializeBefore]; }
932 /** Temporarily sets this instruction as a serialize after instruction. */
933 void setSerializeAfter() { status.set(SerializeAfter); }
935 /** Clears the serializeAfter part of this instruction.*/
936 void clearSerializeAfter() { status.reset(SerializeAfter); }
938 /** Checks if this serializeAfter is only temporarily set. */
939 bool isTempSerializeAfter() { return status[SerializeAfter]; }
941 /** Sets the serialization part of this instruction as handled. */
942 void setSerializeHandled() { status.set(SerializeHandled); }
944 /** Checks if the serialization part of this instruction has been
945 * handled. This does not apply to the temporary serializing
946 * state; it only applies to this instruction's own permanent
949 bool isSerializeHandled() { return status[SerializeHandled]; }
952 /** Instruction effective address.
953 * @todo: Consider if this is necessary or not.
957 /** Whether or not the effective address calculation is completed.
958 * @todo: Consider if this is necessary or not.
963 /** Whether or not the memory operation is done. */
967 /** Load queue index. */
970 /** Store queue index. */
973 /** Iterator pointing to this BaseDynInst in the list of all insts. */
976 /** Returns iterator to this instruction in the list of all insts. */
977 ListIt &getInstListIt() { return instListIt; }
979 /** Sets iterator for this instruction in the list of all insts. */
980 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
982 /** Count of total number of dynamic instructions. */
983 static int instcount;
985 /** Dumps out contents of this BaseDynInst. */
988 /** Dumps out contents of this BaseDynInst into given string. */
989 void dump(std::string &outstring);
992 //inline int curCount() { return curCount(); }
996 #endif // __CPU_BASE_DYN_INST_HH__