2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/faults.hh"
41 #include "arch/isa_traits.hh"
43 #include "arch/types.hh"
44 #include "arch/utility.hh"
45 #include "base/fast_alloc.hh"
46 #include "base/trace.hh"
47 #include "base/types.hh"
48 #include "config/full_system.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/inorder/inorder_trace.hh"
51 #include "cpu/inorder/pipeline_traits.hh"
52 #include "cpu/inorder/resource.hh"
53 #include "cpu/inorder/resource_sked.hh"
54 #include "cpu/inorder/thread_state.hh"
55 #include "cpu/exetrace.hh"
56 #include "cpu/inst_seq.hh"
57 #include "cpu/op_class.hh"
58 #include "cpu/static_inst.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/InOrderDynInst.hh"
61 #include "mem/packet.hh"
62 #include "sim/system.hh"
64 #if THE_ISA == ALPHA_ISA
65 #include "arch/alpha/ev5.hh"
70 * Defines a dynamic instruction context for a inorder CPU model.
73 // Forward declaration.
75 class ResourceRequest;
78 class InOrderDynInst : public FastAlloc, public RefCounted
81 // Binary machine instruction type.
82 typedef TheISA::MachInst MachInst;
83 // Extended machine instruction type
84 typedef TheISA::ExtMachInst ExtMachInst;
85 // Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
87 // Integer register type.
88 typedef TheISA::IntReg IntReg;
89 // Floating point register type.
90 typedef TheISA::FloatReg FloatReg;
91 // Floating point register type.
92 typedef TheISA::FloatRegBits FloatRegBits;
93 // Floating point register type.
94 typedef TheISA::MiscReg MiscReg;
96 typedef short int PhysRegIndex;
98 /** The refcounted DynInst pointer to be used. In most cases this is
99 * what should be used, and not DynInst*.
101 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
103 // The list of instructions iterator type.
104 typedef std::list<DynInstPtr>::iterator ListIt;
107 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
108 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
112 /** BaseDynInst constructor given a binary instruction.
113 * @param seq_num The sequence number of the instruction.
114 * @param cpu Pointer to the instruction's CPU.
115 * NOTE: Must set Binary Instrution through Member Function
117 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
118 InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
120 /** InOrderDynInst destructor. */
124 /** The sequence number of the instruction. */
127 /** If this instruction is squashing, the number should we squash behind. */
128 InstSeqNum squashSeqNum;
131 RegDepMapEntry, /// Instruction is entered onto the RegDepMap
132 IqEntry, /// Instruction is in the IQ
133 RobEntry, /// Instruction is in the ROB
134 LsqEntry, /// Instruction is in the LSQ
135 Completed, /// Instruction has completed
136 ResultReady, /// Instruction has its result
137 CanIssue, /// Instruction can issue and execute
138 Issued, /// Instruction has issued
139 Executed, /// Instruction has executed
140 CanCommit, /// Instruction can commit
141 AtCommit, /// Instruction has reached commit
142 Committed, /// Instruction has committed
143 Squashed, /// Instruction is squashed
144 SquashedInIQ, /// Instruction is squashed in the IQ
145 SquashedInLSQ, /// Instruction is squashed in the LSQ
146 SquashedInROB, /// Instruction is squashed in the ROB
147 RecoverInst, /// Is a recover instruction
148 BlockingInst, /// Is a blocking instruction
149 ThreadsyncWait, /// Is a thread synchronization instruction
150 SerializeBefore, /// Needs to serialize on
151 /// instructions ahead of it
152 SerializeAfter, /// Needs to serialize instructions behind it
153 SerializeHandled, /// Serialization has been handled
154 RemoveList, /// Is Instruction on Remove List?
158 /** The status of this BaseDynInst. Several bits can be set. */
159 std::bitset<NumStatus> status;
161 /** The thread this instruction is from. */
164 /** data address space ID, for loads & stores. */
167 /** The virtual processor number */
168 short virtProcNumber;
170 /** The StaticInst used by this BaseDynInst. */
171 StaticInstPtr staticInst;
173 /** InstRecord that tracks this instructions. */
174 Trace::InOrderTraceRecord *traceData;
176 /** Pointer to the Impl's CPU object. */
179 /** Pointer to the thread state. */
180 InOrderThreadState *thread;
182 /** The kind of fault this instruction has generated. */
185 /** The memory request. */
188 /** Pointer to the data for the memory access. */
191 /** Data used for a store for operation. */
194 /** Data used for a store for operation. */
197 /** List of active resource requests for this instruction */
198 std::list<ResourceRequest*> reqList;
200 /** The effective virtual address (lds & stores only). */
203 /** The effective physical address. */
206 /** The memory request flags (from translation). */
207 unsigned memReqFlags;
209 /** How many source registers are ready. */
220 /** An instruction src/dest has to be one of these types */
235 /** Result of an instruction execution */
242 : type(None), tick(0)
246 /** The source of the instruction; assumes for now that there's only one
247 * destination register.
249 InstValue instSrc[MaxInstSrcRegs];
251 /** The result of the instruction; assumes for now that there's only one
252 * destination register.
254 InstResult instResult[MaxInstDestRegs];
256 /** PC of this instruction. */
259 /** Predicted next PC. */
260 TheISA::PCState predPC;
262 /** Address to get/write data from/to */
263 /* Fetching address when inst. starts, Data address for load/store after fetch*/
266 /** Whether or not the source register is ready.
267 * @todo: Not sure this should be here vs the derived class.
269 bool _readySrcRegIdx[MaxInstSrcRegs];
271 /** Flattened register index of the destination registers of this
274 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
276 /** Flattened register index of the source registers of this
279 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
281 /** Physical register index of the destination registers of this
284 PhysRegIndex _destRegIdx[MaxInstDestRegs];
286 /** Physical register index of the source registers of this
289 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
291 /** Physical register index of the previous producers of the
292 * architected destinations.
294 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
299 /** Function to initialize variables in the constructors. */
305 PacketDataPtr splitMemData;
306 RequestPtr splitMemReq;
311 uint8_t split2ndData;
312 PacketDataPtr split2ndDataPtr;
313 unsigned split2ndFlags;
316 uint64_t *split2ndStoreDataPtr;
319 ////////////////////////////////////////////////////////////
321 // BASE INSTRUCTION INFORMATION.
323 ////////////////////////////////////////////////////////////
324 std::string instName()
325 { return (staticInst) ? staticInst->getName() : "undecoded-inst"; }
327 void setMachInst(ExtMachInst inst);
329 ExtMachInst getMachInst() { return staticInst->machInst; }
331 /** Sets the StaticInst. */
332 void setStaticInst(StaticInstPtr &static_inst);
334 /** Sets the sequence number. */
335 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
337 /** Sets the ASID. */
338 void setASID(short addr_space_id) { asid = addr_space_id; }
340 /** Reads the thread id. */
341 short readTid() { return threadNumber; }
343 /** Sets the thread id. */
344 void setTid(ThreadID tid) { threadNumber = tid; }
346 void setVpn(int id) { virtProcNumber = id; }
348 int readVpn() { return virtProcNumber; }
350 /** Sets the pointer to the thread state. */
351 void setThreadState(InOrderThreadState *state) { thread = state; }
353 /** Returns the thread context. */
354 ThreadContext *tcBase() { return thread->getTC(); }
356 /** Returns the fault type. */
357 Fault getFault() { return fault; }
359 /** Read this CPU's ID. */
362 /** Read this context's system-wide ID **/
363 int contextId() { return thread->contextId(); }
365 ////////////////////////////////////////////////////////////
367 // INSTRUCTION TYPES - Forward checks to StaticInst object.
369 ////////////////////////////////////////////////////////////
370 bool isNop() const { return staticInst->isNop(); }
371 bool isMemRef() const { return staticInst->isMemRef(); }
372 bool isLoad() const { return staticInst->isLoad(); }
373 bool isStore() const { return staticInst->isStore(); }
374 bool isStoreConditional() const
375 { return staticInst->isStoreConditional(); }
376 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
377 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
378 bool isInteger() const { return staticInst->isInteger(); }
379 bool isFloating() const { return staticInst->isFloating(); }
380 bool isControl() const { return staticInst->isControl(); }
381 bool isCall() const { return staticInst->isCall(); }
382 bool isReturn() const { return staticInst->isReturn(); }
383 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
384 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
385 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
386 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
387 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
389 bool isThreadSync() const { return staticInst->isThreadSync(); }
390 bool isSerializing() const { return staticInst->isSerializing(); }
391 bool isSerializeBefore() const
392 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
393 bool isSerializeAfter() const
394 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
395 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
396 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
397 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
398 bool isQuiesce() const { return staticInst->isQuiesce(); }
399 bool isIprAccess() const { return staticInst->isIprAccess(); }
400 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
401 bool isSyscall() const
402 { return staticInst->isSyscall(); }
405 /////////////////////////////////////////////
407 // RESOURCE SCHEDULING
409 /////////////////////////////////////////////
410 typedef ThePipeline::RSkedPtr RSkedPtr;
414 RSkedIt frontSked_end;
417 RSkedIt backSked_end;
419 RSkedIt curSkedEntry;
421 void setFrontSked(RSkedPtr front_sked)
423 frontSked = front_sked;
424 frontSked_end.init(frontSked);
425 frontSked_end = frontSked->end();
426 //DPRINTF(InOrderDynInst, "Set FrontSked End to : %x \n" ,
427 // frontSked_end.getIt()/*, frontSked->end()*/);
428 //assert(frontSked_end == frontSked->end());
430 // This initializes instruction to be able
431 // to walk the resource schedule
432 curSkedEntry.init(frontSked);
433 curSkedEntry = frontSked->begin();
436 void setBackSked(RSkedPtr back_sked)
438 backSked = back_sked;
439 backSked_end.init(backSked);
440 backSked_end = backSked->end();
443 void setNextStage(int stage_num) { nextStage = stage_num; }
444 int getNextStage() { return nextStage; }
446 /** Print Resource Schedule */
449 if (frontSked != NULL) {
453 if (backSked != NULL) {
458 /** Return Next Resource Stage To Be Used */
461 assert((inFrontEnd && curSkedEntry != frontSked_end) ||
462 (!inFrontEnd && curSkedEntry != backSked_end));
464 return curSkedEntry->stageNum;
468 /** Return Next Resource To Be Used */
471 assert((inFrontEnd && curSkedEntry != frontSked_end) ||
472 (!inFrontEnd && curSkedEntry != backSked_end));
474 return curSkedEntry->resNum;
477 /** Finish using a schedule entry, increment to next entry */
478 bool finishSkedEntry()
482 if (inFrontEnd && curSkedEntry == frontSked_end) {
483 DPRINTF(InOrderDynInst, "[sn:%i] Switching to "
484 "back end schedule.\n", seqNum);
485 assert(backSked != NULL);
486 curSkedEntry.init(backSked);
487 curSkedEntry = backSked->begin();
489 } else if (!inFrontEnd && curSkedEntry == backSked_end) {
493 DPRINTF(InOrderDynInst, "[sn:%i] Next Stage: %i "
494 "Next Resource: %i.\n", seqNum, curSkedEntry->stageNum,
495 curSkedEntry->resNum);
500 /** Release a Resource Request (Currently Unused) */
501 void releaseReq(ResourceRequest* req);
503 ////////////////////////////////////////////
505 // INSTRUCTION EXECUTION
507 ////////////////////////////////////////////
508 /** Returns the opclass of this instruction. */
509 OpClass opClass() const { return staticInst->opClass(); }
511 /** Executes the instruction.*/
516 unsigned getCurResSlot() { return curResSlot; }
518 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
520 /** Calls a syscall. */
522 /** Calls hardware return from error interrupt. */
524 /** Traps to handle specified fault. */
525 void trap(Fault fault);
526 bool simPalCheck(int palFunc);
530 /** Calls a syscall. */
531 void syscall(int64_t callnum);
534 ////////////////////////////////////////////////////////////
536 // MULTITHREADING INTERFACE TO CPU MODELS
538 ////////////////////////////////////////////////////////////
539 virtual void deallocateContext(int thread_num);
541 ////////////////////////////////////////////////////////////
543 // PROGRAM COUNTERS - PC/NPC/NPC
545 ////////////////////////////////////////////////////////////
546 /** Read the PC of this instruction. */
547 const TheISA::PCState &pcState() const { return pc; }
549 /** Sets the PC of this instruction. */
550 void pcState(const TheISA::PCState &_pc) { pc = _pc; }
552 const Addr instAddr() { return pc.instAddr(); }
553 const Addr nextInstAddr() { return pc.nextInstAddr(); }
554 const MicroPC microPC() { return pc.microPC(); }
556 ////////////////////////////////////////////////////////////
560 ////////////////////////////////////////////////////////////
561 /** Set the predicted target of this current instruction. */
562 void setPredTarg(const TheISA::PCState &predictedPC)
563 { predPC = predictedPC; }
565 /** Returns the predicted target of the branch. */
566 TheISA::PCState readPredTarg() { return predPC; }
568 /** Returns the predicted PC immediately after the branch. */
569 Addr predInstAddr() { return predPC.instAddr(); }
571 /** Returns the predicted PC two instructions after the branch */
572 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
574 /** Returns the predicted micro PC after the branch */
575 Addr readPredMicroPC() { return predPC.microPC(); }
577 /** Returns whether the instruction was predicted taken or not. */
578 bool predTaken() { return predictTaken; }
580 /** Returns whether the instruction mispredicted. */
584 TheISA::PCState nextPC = pc;
585 TheISA::advancePC(nextPC, staticInst);
586 return !(nextPC == predPC);
589 /** Returns the branch target address. */
590 TheISA::PCState branchTarget() const
591 { return staticInst->branchTarget(pc); }
593 /** Checks whether or not this instruction has had its branch target
594 * calculated yet. For now it is not utilized and is hacked to be
596 * @todo: Actually use this instruction.
598 bool doneTargCalc() { return false; }
600 void setBranchPred(bool prediction) { predictTaken = prediction; }
606 bool procDelaySlotOnMispred;
608 void setSquashInfo(unsigned stage_num);
610 ////////////////////////////////////////////
614 ////////////////////////////////////////////
616 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
618 Fault writeBytes(uint8_t *data, unsigned size,
619 Addr addr, unsigned flags, uint64_t *res);
621 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
622 * Access Only valid for memory operations.
626 /** Completes a memory access - Only valid for memory operations. */
627 Fault completeAcc(Packet *pkt);
629 /** Calculates Eff. Addr. part of a memory instruction. */
632 /** Read Effective Address from instruction & do memory access */
635 RequestPtr fetchMemReq;
636 RequestPtr dataMemReq;
641 { return memAddrReady; }
643 void setMemAddr(Addr addr)
644 { memAddr = addr; memAddrReady = true;}
647 { memAddrReady = false;}
652 /** Sets the effective address. */
653 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
655 /** Returns the effective address. */
656 const Addr &getEA() const { return instEffAddr; }
658 /** Returns whether or not the eff. addr. calculation has been completed.*/
659 bool doneEACalc() { return eaCalcDone; }
661 /** Returns whether or not the eff. addr. source registers are ready.
662 * Assume that src registers 1..n-1 are the ones that the
663 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
668 for (int i = 1; i < numSrcRegs(); ++i) {
669 if (!_readySrcRegIdx[i])
676 //////////////////////////////////////////////////
678 // SOURCE-DESTINATION REGISTER INDEXING
680 //////////////////////////////////////////////////
681 /** Returns the number of source registers. */
682 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
684 /** Returns the number of destination registers. */
685 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
687 // the following are used to track physical register usage
688 // for machines with separate int & FP reg files
689 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
690 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
692 /** Returns the logical register index of the i'th destination register. */
693 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
695 /** Returns the logical register index of the i'th source register. */
696 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
698 //////////////////////////////////////////////////
700 // RENAME/PHYSICAL REGISTER FILE SUPPORT
702 //////////////////////////////////////////////////
703 /** Returns the physical register index of the i'th destination
706 PhysRegIndex renamedDestRegIdx(int idx) const
708 return _destRegIdx[idx];
711 /** Returns the physical register index of the i'th source register. */
712 PhysRegIndex renamedSrcRegIdx(int idx) const
714 return _srcRegIdx[idx];
717 /** Flattens a source architectural register index into a logical index.
719 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
721 _flatSrcRegIdx[idx] = flattened_src;
724 /** Flattens a destination architectural register index into a logical
727 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
729 _flatDestRegIdx[idx] = flattened_dest;
732 /** Returns the flattened register index of the i'th destination
735 TheISA::RegIndex flattenedDestRegIdx(int idx) const
737 return _flatDestRegIdx[idx];
740 /** Returns the flattened register index of the i'th source register */
741 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
743 return _flatSrcRegIdx[idx];
746 /** Returns the physical register index of the previous physical register
747 * that remapped to the same logical register index.
749 PhysRegIndex prevDestRegIdx(int idx) const
751 return _prevDestRegIdx[idx];
754 /** Returns if a source register is ready. */
755 bool isReadySrcRegIdx(int idx) const
757 return this->_readySrcRegIdx[idx];
760 /** Records that one of the source registers is ready. */
761 void markSrcRegReady()
763 if (++readyRegs == numSrcRegs()) {
764 status.set(CanIssue);
768 /** Marks a specific register as ready. */
769 void markSrcRegReady(RegIndex src_idx)
771 _readySrcRegIdx[src_idx] = true;
776 /** Renames a destination register to a physical register. Also records
777 * the previous physical register that the logical register mapped to.
779 void renameDestReg(int idx,
780 PhysRegIndex renamed_dest,
781 PhysRegIndex previous_rename)
783 _destRegIdx[idx] = renamed_dest;
784 _prevDestRegIdx[idx] = previous_rename;
787 /** Renames a source logical register to the physical register which
788 * has/will produce that logical register's result.
789 * @todo: add in whether or not the source register is ready.
791 void renameSrcReg(int idx, PhysRegIndex renamed_src)
793 _srcRegIdx[idx] = renamed_src;
797 PhysRegIndex readDestRegIdx(int idx)
799 return _destRegIdx[idx];
802 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
804 _destRegIdx[idx] = dest_idx;
807 int getDestIdxNum(PhysRegIndex dest_idx)
809 for (int i=0; i < staticInst->numDestRegs(); i++) {
810 if (_flatDestRegIdx[i] == dest_idx)
817 PhysRegIndex readSrcRegIdx(int idx)
819 return _srcRegIdx[idx];
822 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
824 _srcRegIdx[idx] = src_idx;
827 int getSrcIdxNum(PhysRegIndex src_idx)
829 for (int i=0; i < staticInst->numSrcRegs(); i++) {
830 if (_srcRegIdx[i] == src_idx)
837 ////////////////////////////////////////////////////
839 // SOURCE-DESTINATION REGISTER VALUES
841 ////////////////////////////////////////////////////
843 /** Functions that sets an integer or floating point
844 * source register to a value. */
845 void setIntSrc(int idx, uint64_t val);
846 void setFloatSrc(int idx, FloatReg val);
847 void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val);
849 TheISA::IntReg* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
850 uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; }
852 /** These Instructions read a integer/float/misc. source register
853 * value in the instruction. The instruction's execute function will
854 * call these and it is the interface that is used by the ISA descr.
855 * language (which is why the name isnt readIntSrc(...)) Note: That
856 * the source reg. value is set using the setSrcReg() function.
858 IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
859 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
860 TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
861 MiscReg readMiscReg(int misc_reg);
862 MiscReg readMiscRegNoEffect(int misc_reg);
863 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
864 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
866 /** Returns the result value instruction. */
867 ResultType resultType(int idx)
869 return instResult[idx].type;
872 IntReg readIntResult(int idx)
874 return instResult[idx].res.intVal;
877 FloatReg readFloatResult(int idx)
879 return instResult[idx].res.fpVal.f;
882 FloatRegBits readFloatBitsResult(int idx)
884 return instResult[idx].res.fpVal.i;
887 Tick readResultTime(int idx) { return instResult[idx].tick; }
889 IntReg* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; }
891 /** This is the interface that an instruction will use to write
892 * it's destination register.
894 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
895 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
896 void setFloatRegOperandBits(const StaticInst *si, int idx,
897 TheISA::FloatRegBits val);
898 void setMiscReg(int misc_reg, const MiscReg &val);
899 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
900 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
901 void setMiscRegOperandNoEffect(const StaticInst *si, int idx,
904 virtual uint64_t readRegOtherThread(unsigned idx,
905 ThreadID tid = InvalidThreadID);
906 virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
907 ThreadID tid = InvalidThreadID);
909 /** Returns the number of consecutive store conditional failures. */
910 unsigned readStCondFailures()
911 { return thread->storeCondFailures; }
913 /** Sets the number of consecutive store conditional failures. */
914 void setStCondFailures(unsigned sc_failures)
915 { thread->storeCondFailures = sc_failures; }
917 //////////////////////////////////////////////////////////////
919 // INSTRUCTION STATUS FLAGS (READ/SET)
921 //////////////////////////////////////////////////////////////
922 /** Sets this instruction as entered on the CPU Reg Dep Map */
923 void setRegDepEntry() { status.set(RegDepMapEntry); }
925 /** Unsets this instruction as entered on the CPU Reg Dep Map */
926 void clearRegDepEntry() { status.reset(RegDepMapEntry); }
928 /** Returns whether or not the entry is on the CPU Reg Dep Map */
929 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
931 /** Sets this instruction as entered on the CPU Reg Dep Map */
932 void setRemoveList() { status.set(RemoveList); }
934 /** Returns whether or not the entry is on the CPU Reg Dep Map */
935 bool isRemoveList() const { return status[RemoveList]; }
937 /** Sets this instruction as completed. */
938 void setCompleted() { status.set(Completed); }
940 /** Returns whether or not this instruction is completed. */
941 bool isCompleted() const { return status[Completed]; }
943 /** Marks the result as ready. */
944 void setResultReady() { status.set(ResultReady); }
946 /** Returns whether or not the result is ready. */
947 bool isResultReady() const { return status[ResultReady]; }
949 /** Sets this instruction as ready to issue. */
950 void setCanIssue() { status.set(CanIssue); }
952 /** Returns whether or not this instruction is ready to issue. */
953 bool readyToIssue() const { return status[CanIssue]; }
955 /** Sets this instruction as issued from the IQ. */
956 void setIssued() { status.set(Issued); }
958 /** Returns whether or not this instruction has issued. */
959 bool isIssued() const { return status[Issued]; }
961 /** Sets this instruction as executed. */
962 void setExecuted() { status.set(Executed); }
964 /** Returns whether or not this instruction has executed. */
965 bool isExecuted() const { return status[Executed]; }
967 /** Sets this instruction as ready to commit. */
968 void setCanCommit() { status.set(CanCommit); }
970 /** Clears this instruction as being ready to commit. */
971 void clearCanCommit() { status.reset(CanCommit); }
973 /** Returns whether or not this instruction is ready to commit. */
974 bool readyToCommit() const { return status[CanCommit]; }
976 void setAtCommit() { status.set(AtCommit); }
978 bool isAtCommit() { return status[AtCommit]; }
980 /** Sets this instruction as committed. */
981 void setCommitted() { status.set(Committed); }
983 /** Returns whether or not this instruction is committed. */
984 bool isCommitted() const { return status[Committed]; }
986 /** Sets this instruction as squashed. */
987 void setSquashed() { status.set(Squashed); }
989 /** Returns whether or not this instruction is squashed. */
990 bool isSquashed() const { return status[Squashed]; }
992 /** Temporarily sets this instruction as a serialize before instruction. */
993 void setSerializeBefore() { status.set(SerializeBefore); }
995 /** Clears the serializeBefore part of this instruction. */
996 void clearSerializeBefore() { status.reset(SerializeBefore); }
998 /** Checks if this serializeBefore is only temporarily set. */
999 bool isTempSerializeBefore() { return status[SerializeBefore]; }
1001 /** Temporarily sets this instruction as a serialize after instruction. */
1002 void setSerializeAfter() { status.set(SerializeAfter); }
1004 /** Clears the serializeAfter part of this instruction.*/
1005 void clearSerializeAfter() { status.reset(SerializeAfter); }
1007 /** Checks if this serializeAfter is only temporarily set. */
1008 bool isTempSerializeAfter() { return status[SerializeAfter]; }
1010 /** Sets the serialization part of this instruction as handled. */
1011 void setSerializeHandled() { status.set(SerializeHandled); }
1013 /** Checks if the serialization part of this instruction has been
1014 * handled. This does not apply to the temporary serializing
1015 * state; it only applies to this instruction's own permanent
1016 * serializing state.
1018 bool isSerializeHandled() { return status[SerializeHandled]; }
1021 /** Instruction effective address.
1022 * @todo: Consider if this is necessary or not.
1026 /** Whether or not the effective address calculation is completed.
1027 * @todo: Consider if this is necessary or not.
1032 /** Load queue index. */
1035 /** Store queue index. */
1038 /** Iterator pointing to this BaseDynInst in the list of all insts. */
1043 /** Returns iterator to this instruction in the list of all insts. */
1044 ListIt getInstListIt() { return instListIt; }
1046 /** Sets iterator for this instruction in the list of all insts. */
1047 void setInstListIt(ListIt _instListIt) { onInstList = true; instListIt = _instListIt; }
1049 /** Count of total number of dynamic instructions. */
1050 static int instcount;
1052 void resetInstCount();
1054 /** Dumps out contents of this BaseDynInst. */
1057 /** Dumps out contents of this BaseDynInst into given string. */
1058 void dump(std::string &outstring);
1060 //inline int curCount() { return curCount(); }
1064 #endif // __CPU_BASE_DYN_INST_HH__