2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/faults.hh"
41 #include "arch/isa_traits.hh"
43 #include "arch/types.hh"
44 #include "arch/utility.hh"
45 #include "base/fast_alloc.hh"
46 #include "base/trace.hh"
47 #include "base/types.hh"
48 #include "config/full_system.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/inorder/inorder_trace.hh"
51 #include "cpu/inorder/pipeline_traits.hh"
52 #include "cpu/inorder/resource.hh"
53 #include "cpu/inorder/resource_sked.hh"
54 #include "cpu/inorder/thread_state.hh"
55 #include "cpu/exetrace.hh"
56 #include "cpu/inst_seq.hh"
57 #include "cpu/op_class.hh"
58 #include "cpu/static_inst.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/InOrderDynInst.hh"
61 #include "mem/packet.hh"
62 #include "sim/system.hh"
64 #if THE_ISA == ALPHA_ISA
65 #include "arch/alpha/ev5.hh"
70 * Defines a dynamic instruction context for a inorder CPU model.
73 // Forward declaration.
74 class ResourceRequest;
77 class InOrderDynInst : public FastAlloc, public RefCounted
80 // Binary machine instruction type.
81 typedef TheISA::MachInst MachInst;
82 // Extended machine instruction type
83 typedef TheISA::ExtMachInst ExtMachInst;
84 // Logical register index type.
85 typedef TheISA::RegIndex RegIndex;
86 // Integer register type.
87 typedef TheISA::IntReg IntReg;
88 // Floating point register type.
89 typedef TheISA::FloatReg FloatReg;
90 // Floating point register type.
91 typedef TheISA::FloatRegBits FloatRegBits;
92 // Floating point register type.
93 typedef TheISA::MiscReg MiscReg;
95 typedef short int PhysRegIndex;
97 /** The refcounted DynInst pointer to be used. In most cases this is
98 * what should be used, and not DynInst*.
100 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
102 // The list of instructions iterator type.
103 typedef std::list<DynInstPtr>::iterator ListIt;
106 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
107 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
111 /** BaseDynInst constructor given a binary instruction.
112 * @param seq_num The sequence number of the instruction.
113 * @param cpu Pointer to the instruction's CPU.
114 * NOTE: Must set Binary Instrution through Member Function
116 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
117 InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
119 /** InOrderDynInst destructor. */
123 /** The sequence number of the instruction. */
126 /** If this instruction is squashing, the number should we squash behind. */
127 InstSeqNum squashSeqNum;
130 RegDepMapEntry, /// Instruction is entered onto the RegDepMap
131 IqEntry, /// Instruction is in the IQ
132 RobEntry, /// Instruction is in the ROB
133 LsqEntry, /// Instruction is in the LSQ
134 Completed, /// Instruction has completed
135 ResultReady, /// Instruction has its result
136 CanIssue, /// Instruction can issue and execute
137 Issued, /// Instruction has issued
138 Executed, /// Instruction has executed
139 CanCommit, /// Instruction can commit
140 AtCommit, /// Instruction has reached commit
141 Committed, /// Instruction has committed
142 Squashed, /// Instruction is squashed
143 SquashedInIQ, /// Instruction is squashed in the IQ
144 SquashedInLSQ, /// Instruction is squashed in the LSQ
145 SquashedInROB, /// Instruction is squashed in the ROB
146 RecoverInst, /// Is a recover instruction
147 BlockingInst, /// Is a blocking instruction
148 ThreadsyncWait, /// Is a thread synchronization instruction
149 SerializeBefore, /// Needs to serialize on
150 /// instructions ahead of it
151 SerializeAfter, /// Needs to serialize instructions behind it
152 SerializeHandled, /// Serialization has been handled
153 RemoveList, /// Is Instruction on Remove List?
157 /** The status of this BaseDynInst. Several bits can be set. */
158 std::bitset<NumStatus> status;
160 /** The thread this instruction is from. */
163 /** data address space ID, for loads & stores. */
166 /** The virtual processor number */
167 short virtProcNumber;
169 /** The StaticInst used by this BaseDynInst. */
170 StaticInstPtr staticInst;
172 /** InstRecord that tracks this instructions. */
173 Trace::InOrderTraceRecord *traceData;
175 /** Pointer to the Impl's CPU object. */
178 /** Pointer to the thread state. */
179 InOrderThreadState *thread;
181 /** The kind of fault this instruction has generated. */
184 /** The memory request. */
187 /** Pointer to the data for the memory access. */
190 /** Data used for a store for operation. */
193 /** Data used for a store for operation. */
196 /** List of active resource requests for this instruction */
197 std::list<ResourceRequest*> reqList;
199 /** The effective virtual address (lds & stores only). */
202 /** The effective physical address. */
205 /** The memory request flags (from translation). */
206 unsigned memReqFlags;
208 /** How many source registers are ready. */
219 /** An instruction src/dest has to be one of these types */
234 /** Result of an instruction execution */
241 : type(None), tick(0)
245 /** The source of the instruction; assumes for now that there's only one
246 * destination register.
248 InstValue instSrc[MaxInstSrcRegs];
250 /** The result of the instruction; assumes for now that there's only one
251 * destination register.
253 InstResult instResult[MaxInstDestRegs];
255 /** PC of this instruction. */
258 /** Predicted next PC. */
259 TheISA::PCState predPC;
261 /** Address to get/write data from/to */
262 /* Fetching address when inst. starts, Data address for load/store after fetch*/
265 /** Whether or not the source register is ready.
266 * @todo: Not sure this should be here vs the derived class.
268 bool _readySrcRegIdx[MaxInstSrcRegs];
270 /** Flattened register index of the destination registers of this
273 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
275 /** Flattened register index of the source registers of this
278 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
280 /** Physical register index of the destination registers of this
283 PhysRegIndex _destRegIdx[MaxInstDestRegs];
285 /** Physical register index of the source registers of this
288 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
290 /** Physical register index of the previous producers of the
291 * architected destinations.
293 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
298 /** Function to initialize variables in the constructors. */
304 PacketDataPtr splitMemData;
305 RequestPtr splitMemReq;
310 uint8_t split2ndData;
311 PacketDataPtr split2ndDataPtr;
312 unsigned split2ndFlags;
315 uint64_t *split2ndStoreDataPtr;
318 ////////////////////////////////////////////////////////////
320 // BASE INSTRUCTION INFORMATION.
322 ////////////////////////////////////////////////////////////
323 std::string instName()
324 { return (staticInst) ? staticInst->getName() : "undecoded-inst"; }
326 void setStaticInst(StaticInstPtr si);
328 ExtMachInst getMachInst() { return staticInst->machInst; }
330 /** Sets the StaticInst. */
331 void setStaticInst(StaticInstPtr &static_inst);
333 /** Sets the sequence number. */
334 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
336 /** Sets the ASID. */
337 void setASID(short addr_space_id) { asid = addr_space_id; }
339 /** Reads the thread id. */
340 short readTid() { return threadNumber; }
342 /** Sets the thread id. */
343 void setTid(ThreadID tid) { threadNumber = tid; }
345 void setVpn(int id) { virtProcNumber = id; }
347 int readVpn() { return virtProcNumber; }
349 /** Sets the pointer to the thread state. */
350 void setThreadState(InOrderThreadState *state) { thread = state; }
352 /** Returns the thread context. */
353 ThreadContext *tcBase() { return thread->getTC(); }
355 /** Returns the fault type. */
356 Fault getFault() { return fault; }
358 /** Read this CPU's ID. */
361 /** Read this context's system-wide ID **/
362 int contextId() { return thread->contextId(); }
364 ////////////////////////////////////////////////////////////
366 // INSTRUCTION TYPES - Forward checks to StaticInst object.
368 ////////////////////////////////////////////////////////////
369 bool isNop() const { return staticInst->isNop(); }
370 bool isMemRef() const { return staticInst->isMemRef(); }
371 bool isLoad() const { return staticInst->isLoad(); }
372 bool isStore() const { return staticInst->isStore(); }
373 bool isStoreConditional() const
374 { return staticInst->isStoreConditional(); }
375 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
376 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
377 bool isInteger() const { return staticInst->isInteger(); }
378 bool isFloating() const { return staticInst->isFloating(); }
379 bool isControl() const { return staticInst->isControl(); }
380 bool isCall() const { return staticInst->isCall(); }
381 bool isReturn() const { return staticInst->isReturn(); }
382 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
383 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
384 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
385 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
386 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
388 bool isThreadSync() const { return staticInst->isThreadSync(); }
389 bool isSerializing() const { return staticInst->isSerializing(); }
390 bool isSerializeBefore() const
391 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
392 bool isSerializeAfter() const
393 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
394 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
395 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
396 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
397 bool isQuiesce() const { return staticInst->isQuiesce(); }
398 bool isIprAccess() const { return staticInst->isIprAccess(); }
399 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
400 bool isSyscall() const
401 { return staticInst->isSyscall(); }
404 /////////////////////////////////////////////
406 // RESOURCE SCHEDULING
408 /////////////////////////////////////////////
409 typedef ThePipeline::RSkedPtr RSkedPtr;
413 RSkedIt frontSked_end;
416 RSkedIt backSked_end;
418 RSkedIt curSkedEntry;
420 void setFrontSked(RSkedPtr front_sked)
422 frontSked = front_sked;
423 frontSked_end.init(frontSked);
424 frontSked_end = frontSked->end();
425 //DPRINTF(InOrderDynInst, "Set FrontSked End to : %x \n" ,
426 // frontSked_end.getIt()/*, frontSked->end()*/);
427 //assert(frontSked_end == frontSked->end());
429 // This initializes instruction to be able
430 // to walk the resource schedule
431 curSkedEntry.init(frontSked);
432 curSkedEntry = frontSked->begin();
435 void setBackSked(RSkedPtr back_sked)
437 backSked = back_sked;
438 backSked_end.init(backSked);
439 backSked_end = backSked->end();
442 void setNextStage(int stage_num) { nextStage = stage_num; }
443 int getNextStage() { return nextStage; }
445 /** Print Resource Schedule */
448 if (frontSked != NULL) {
452 if (backSked != NULL) {
457 /** Return Next Resource Stage To Be Used */
460 assert((inFrontEnd && curSkedEntry != frontSked_end) ||
461 (!inFrontEnd && curSkedEntry != backSked_end));
463 return curSkedEntry->stageNum;
467 /** Return Next Resource To Be Used */
470 assert((inFrontEnd && curSkedEntry != frontSked_end) ||
471 (!inFrontEnd && curSkedEntry != backSked_end));
473 return curSkedEntry->resNum;
476 /** Finish using a schedule entry, increment to next entry */
477 bool finishSkedEntry()
481 if (inFrontEnd && curSkedEntry == frontSked_end) {
482 DPRINTF(InOrderDynInst, "[sn:%i] Switching to "
483 "back end schedule.\n", seqNum);
484 assert(backSked != NULL);
485 curSkedEntry.init(backSked);
486 curSkedEntry = backSked->begin();
488 } else if (!inFrontEnd && curSkedEntry == backSked_end) {
492 DPRINTF(InOrderDynInst, "[sn:%i] Next Stage: %i "
493 "Next Resource: %i.\n", seqNum, curSkedEntry->stageNum,
494 curSkedEntry->resNum);
499 /** Release a Resource Request (Currently Unused) */
500 void releaseReq(ResourceRequest* req);
502 ////////////////////////////////////////////
504 // INSTRUCTION EXECUTION
506 ////////////////////////////////////////////
507 /** Returns the opclass of this instruction. */
508 OpClass opClass() const { return staticInst->opClass(); }
510 /** Executes the instruction.*/
515 unsigned getCurResSlot() { return curResSlot; }
517 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
519 /** Calls a syscall. */
521 /** Calls hardware return from error interrupt. */
523 /** Traps to handle specified fault. */
524 void trap(Fault fault);
525 bool simPalCheck(int palFunc);
530 /** Emulates a syscall. */
531 void syscall(int64_t callnum);
533 ////////////////////////////////////////////////////////////
535 // MULTITHREADING INTERFACE TO CPU MODELS
537 ////////////////////////////////////////////////////////////
538 virtual void deallocateContext(int thread_num);
540 ////////////////////////////////////////////////////////////
542 // PROGRAM COUNTERS - PC/NPC/NPC
544 ////////////////////////////////////////////////////////////
545 /** Read the PC of this instruction. */
546 const TheISA::PCState &pcState() const { return pc; }
548 /** Sets the PC of this instruction. */
549 void pcState(const TheISA::PCState &_pc) { pc = _pc; }
551 const Addr instAddr() { return pc.instAddr(); }
552 const Addr nextInstAddr() { return pc.nextInstAddr(); }
553 const MicroPC microPC() { return pc.microPC(); }
555 ////////////////////////////////////////////////////////////
559 ////////////////////////////////////////////////////////////
560 /** Set the predicted target of this current instruction. */
561 void setPredTarg(const TheISA::PCState &predictedPC)
562 { predPC = predictedPC; }
564 /** Returns the predicted target of the branch. */
565 TheISA::PCState readPredTarg() { return predPC; }
567 /** Returns the predicted PC immediately after the branch. */
568 Addr predInstAddr() { return predPC.instAddr(); }
570 /** Returns the predicted PC two instructions after the branch */
571 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
573 /** Returns the predicted micro PC after the branch */
574 Addr readPredMicroPC() { return predPC.microPC(); }
576 /** Returns whether the instruction was predicted taken or not. */
577 bool predTaken() { return predictTaken; }
579 /** Returns whether the instruction mispredicted. */
583 TheISA::PCState nextPC = pc;
584 TheISA::advancePC(nextPC, staticInst);
585 return !(nextPC == predPC);
588 /** Returns the branch target address. */
589 TheISA::PCState branchTarget() const
590 { return staticInst->branchTarget(pc); }
592 /** Checks whether or not this instruction has had its branch target
593 * calculated yet. For now it is not utilized and is hacked to be
595 * @todo: Actually use this instruction.
597 bool doneTargCalc() { return false; }
599 void setBranchPred(bool prediction) { predictTaken = prediction; }
605 bool procDelaySlotOnMispred;
607 void setSquashInfo(unsigned stage_num);
609 ////////////////////////////////////////////
613 ////////////////////////////////////////////
615 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
617 Fault writeMem(uint8_t *data, unsigned size,
618 Addr addr, unsigned flags, uint64_t *res);
620 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
621 * Access Only valid for memory operations.
625 /** Completes a memory access - Only valid for memory operations. */
626 Fault completeAcc(Packet *pkt);
628 /** Calculates Eff. Addr. part of a memory instruction. */
631 /** Read Effective Address from instruction & do memory access */
634 RequestPtr fetchMemReq;
635 RequestPtr dataMemReq;
640 { return memAddrReady; }
642 void setMemAddr(Addr addr)
643 { memAddr = addr; memAddrReady = true;}
646 { memAddrReady = false;}
651 /** Sets the effective address. */
652 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
654 /** Returns the effective address. */
655 const Addr &getEA() const { return instEffAddr; }
657 /** Returns whether or not the eff. addr. calculation has been completed.*/
658 bool doneEACalc() { return eaCalcDone; }
660 /** Returns whether or not the eff. addr. source registers are ready.
661 * Assume that src registers 1..n-1 are the ones that the
662 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
667 for (int i = 1; i < numSrcRegs(); ++i) {
668 if (!_readySrcRegIdx[i])
675 //////////////////////////////////////////////////
677 // SOURCE-DESTINATION REGISTER INDEXING
679 //////////////////////////////////////////////////
680 /** Returns the number of source registers. */
681 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
683 /** Returns the number of destination registers. */
684 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
686 // the following are used to track physical register usage
687 // for machines with separate int & FP reg files
688 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
689 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
691 /** Returns the logical register index of the i'th destination register. */
692 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
694 /** Returns the logical register index of the i'th source register. */
695 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
697 //////////////////////////////////////////////////
699 // RENAME/PHYSICAL REGISTER FILE SUPPORT
701 //////////////////////////////////////////////////
702 /** Returns the physical register index of the i'th destination
705 PhysRegIndex renamedDestRegIdx(int idx) const
707 return _destRegIdx[idx];
710 /** Returns the physical register index of the i'th source register. */
711 PhysRegIndex renamedSrcRegIdx(int idx) const
713 return _srcRegIdx[idx];
716 /** Flattens a source architectural register index into a logical index.
718 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
720 _flatSrcRegIdx[idx] = flattened_src;
723 /** Flattens a destination architectural register index into a logical
726 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
728 _flatDestRegIdx[idx] = flattened_dest;
731 /** Returns the flattened register index of the i'th destination
734 TheISA::RegIndex flattenedDestRegIdx(int idx) const
736 return _flatDestRegIdx[idx];
739 /** Returns the flattened register index of the i'th source register */
740 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
742 return _flatSrcRegIdx[idx];
745 /** Returns the physical register index of the previous physical register
746 * that remapped to the same logical register index.
748 PhysRegIndex prevDestRegIdx(int idx) const
750 return _prevDestRegIdx[idx];
753 /** Returns if a source register is ready. */
754 bool isReadySrcRegIdx(int idx) const
756 return this->_readySrcRegIdx[idx];
759 /** Records that one of the source registers is ready. */
760 void markSrcRegReady()
762 if (++readyRegs == numSrcRegs()) {
763 status.set(CanIssue);
767 /** Marks a specific register as ready. */
768 void markSrcRegReady(RegIndex src_idx)
770 _readySrcRegIdx[src_idx] = true;
775 /** Renames a destination register to a physical register. Also records
776 * the previous physical register that the logical register mapped to.
778 void renameDestReg(int idx,
779 PhysRegIndex renamed_dest,
780 PhysRegIndex previous_rename)
782 _destRegIdx[idx] = renamed_dest;
783 _prevDestRegIdx[idx] = previous_rename;
786 /** Renames a source logical register to the physical register which
787 * has/will produce that logical register's result.
788 * @todo: add in whether or not the source register is ready.
790 void renameSrcReg(int idx, PhysRegIndex renamed_src)
792 _srcRegIdx[idx] = renamed_src;
796 PhysRegIndex readDestRegIdx(int idx)
798 return _destRegIdx[idx];
801 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
803 _destRegIdx[idx] = dest_idx;
806 int getDestIdxNum(PhysRegIndex dest_idx)
808 for (int i=0; i < staticInst->numDestRegs(); i++) {
809 if (_flatDestRegIdx[i] == dest_idx)
816 PhysRegIndex readSrcRegIdx(int idx)
818 return _srcRegIdx[idx];
821 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
823 _srcRegIdx[idx] = src_idx;
826 int getSrcIdxNum(PhysRegIndex src_idx)
828 for (int i=0; i < staticInst->numSrcRegs(); i++) {
829 if (_srcRegIdx[i] == src_idx)
836 ////////////////////////////////////////////////////
838 // SOURCE-DESTINATION REGISTER VALUES
840 ////////////////////////////////////////////////////
842 /** Functions that sets an integer or floating point
843 * source register to a value. */
844 void setIntSrc(int idx, uint64_t val);
845 void setFloatSrc(int idx, FloatReg val);
846 void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val);
848 TheISA::IntReg* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
849 uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; }
851 /** These Instructions read a integer/float/misc. source register
852 * value in the instruction. The instruction's execute function will
853 * call these and it is the interface that is used by the ISA descr.
854 * language (which is why the name isnt readIntSrc(...)) Note: That
855 * the source reg. value is set using the setSrcReg() function.
857 IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
858 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
859 TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
860 MiscReg readMiscReg(int misc_reg);
861 MiscReg readMiscRegNoEffect(int misc_reg);
862 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
863 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
865 /** Returns the result value instruction. */
866 ResultType resultType(int idx)
868 return instResult[idx].type;
871 IntReg readIntResult(int idx)
873 return instResult[idx].res.intVal;
876 FloatReg readFloatResult(int idx)
878 return instResult[idx].res.fpVal.f;
881 FloatRegBits readFloatBitsResult(int idx)
883 return instResult[idx].res.fpVal.i;
886 Tick readResultTime(int idx) { return instResult[idx].tick; }
888 IntReg* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; }
890 /** This is the interface that an instruction will use to write
891 * it's destination register.
893 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
894 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
895 void setFloatRegOperandBits(const StaticInst *si, int idx,
896 TheISA::FloatRegBits val);
897 void setMiscReg(int misc_reg, const MiscReg &val);
898 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
899 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
900 void setMiscRegOperandNoEffect(const StaticInst *si, int idx,
903 virtual uint64_t readRegOtherThread(unsigned idx,
904 ThreadID tid = InvalidThreadID);
905 virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
906 ThreadID tid = InvalidThreadID);
908 /** Returns the number of consecutive store conditional failures. */
909 unsigned readStCondFailures()
910 { return thread->storeCondFailures; }
912 /** Sets the number of consecutive store conditional failures. */
913 void setStCondFailures(unsigned sc_failures)
914 { thread->storeCondFailures = sc_failures; }
916 //////////////////////////////////////////////////////////////
918 // INSTRUCTION STATUS FLAGS (READ/SET)
920 //////////////////////////////////////////////////////////////
921 /** Sets this instruction as entered on the CPU Reg Dep Map */
922 void setRegDepEntry() { status.set(RegDepMapEntry); }
924 /** Unsets this instruction as entered on the CPU Reg Dep Map */
925 void clearRegDepEntry() { status.reset(RegDepMapEntry); }
927 /** Returns whether or not the entry is on the CPU Reg Dep Map */
928 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
930 /** Sets this instruction as entered on the CPU Reg Dep Map */
931 void setRemoveList() { status.set(RemoveList); }
933 /** Returns whether or not the entry is on the CPU Reg Dep Map */
934 bool isRemoveList() const { return status[RemoveList]; }
936 /** Sets this instruction as completed. */
937 void setCompleted() { status.set(Completed); }
939 /** Returns whether or not this instruction is completed. */
940 bool isCompleted() const { return status[Completed]; }
942 /** Marks the result as ready. */
943 void setResultReady() { status.set(ResultReady); }
945 /** Returns whether or not the result is ready. */
946 bool isResultReady() const { return status[ResultReady]; }
948 /** Sets this instruction as ready to issue. */
949 void setCanIssue() { status.set(CanIssue); }
951 /** Returns whether or not this instruction is ready to issue. */
952 bool readyToIssue() const { return status[CanIssue]; }
954 /** Sets this instruction as issued from the IQ. */
955 void setIssued() { status.set(Issued); }
957 /** Returns whether or not this instruction has issued. */
958 bool isIssued() const { return status[Issued]; }
960 /** Sets this instruction as executed. */
961 void setExecuted() { status.set(Executed); }
963 /** Returns whether or not this instruction has executed. */
964 bool isExecuted() const { return status[Executed]; }
966 /** Sets this instruction as ready to commit. */
967 void setCanCommit() { status.set(CanCommit); }
969 /** Clears this instruction as being ready to commit. */
970 void clearCanCommit() { status.reset(CanCommit); }
972 /** Returns whether or not this instruction is ready to commit. */
973 bool readyToCommit() const { return status[CanCommit]; }
975 void setAtCommit() { status.set(AtCommit); }
977 bool isAtCommit() { return status[AtCommit]; }
979 /** Sets this instruction as committed. */
980 void setCommitted() { status.set(Committed); }
982 /** Returns whether or not this instruction is committed. */
983 bool isCommitted() const { return status[Committed]; }
985 /** Sets this instruction as squashed. */
986 void setSquashed() { status.set(Squashed); }
988 /** Returns whether or not this instruction is squashed. */
989 bool isSquashed() const { return status[Squashed]; }
991 /** Temporarily sets this instruction as a serialize before instruction. */
992 void setSerializeBefore() { status.set(SerializeBefore); }
994 /** Clears the serializeBefore part of this instruction. */
995 void clearSerializeBefore() { status.reset(SerializeBefore); }
997 /** Checks if this serializeBefore is only temporarily set. */
998 bool isTempSerializeBefore() { return status[SerializeBefore]; }
1000 /** Temporarily sets this instruction as a serialize after instruction. */
1001 void setSerializeAfter() { status.set(SerializeAfter); }
1003 /** Clears the serializeAfter part of this instruction.*/
1004 void clearSerializeAfter() { status.reset(SerializeAfter); }
1006 /** Checks if this serializeAfter is only temporarily set. */
1007 bool isTempSerializeAfter() { return status[SerializeAfter]; }
1009 /** Sets the serialization part of this instruction as handled. */
1010 void setSerializeHandled() { status.set(SerializeHandled); }
1012 /** Checks if the serialization part of this instruction has been
1013 * handled. This does not apply to the temporary serializing
1014 * state; it only applies to this instruction's own permanent
1015 * serializing state.
1017 bool isSerializeHandled() { return status[SerializeHandled]; }
1020 /** Instruction effective address.
1021 * @todo: Consider if this is necessary or not.
1025 /** Whether or not the effective address calculation is completed.
1026 * @todo: Consider if this is necessary or not.
1031 /** Load queue index. */
1034 /** Store queue index. */
1037 /** Iterator pointing to this BaseDynInst in the list of all insts. */
1042 /** Returns iterator to this instruction in the list of all insts. */
1043 ListIt getInstListIt() { return instListIt; }
1045 /** Sets iterator for this instruction in the list of all insts. */
1046 void setInstListIt(ListIt _instListIt) { onInstList = true; instListIt = _instListIt; }
1048 /** Count of total number of dynamic instructions. */
1049 static int instcount;
1051 void resetInstCount();
1053 /** Dumps out contents of this BaseDynInst. */
1056 /** Dumps out contents of this BaseDynInst into given string. */
1057 void dump(std::string &outstring);
1059 //inline int curCount() { return curCount(); }
1063 #endif // __CPU_BASE_DYN_INST_HH__