src/cpu/inorder/inorder_dyn_inst.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Kevin Lim
  30  *          Korey Sewell
  31  */
  32
  33 #ifndef __CPU_INORDER_DYN_INST_HH__
  34 #define __CPU_INORDER_DYN_INST_HH__
  35
  36 #include <bitset>
  37 #include <list>
  38 #include <string>
  39
  40 #include "arch/isa_traits.hh"
  41 #include "arch/faults.hh"
  42 #include "arch/types.hh"
  43 #include "arch/mt.hh"
  44 #include "base/fast_alloc.hh"
  45 #include "base/trace.hh"
  46 #include "cpu/inorder/inorder_trace.hh"
  47 #include "config/full_system.hh"
  48 #include "cpu/thread_context.hh"
  49 #include "cpu/exetrace.hh"
  50 #include "cpu/inst_seq.hh"
  51 #include "cpu/op_class.hh"
  52 #include "cpu/static_inst.hh"
  53 #include "cpu/inorder/thread_state.hh"
  54 #include "cpu/inorder/resource.hh"
  55 #include "cpu/inorder/pipeline_traits.hh"
  56 #include "mem/packet.hh"
  57 #include "sim/system.hh"
  58
  59 /**
  60  * @file
  61  * Defines a dynamic instruction context for a inorder CPU model.
  62  */
  63
  64 // Forward declaration.
  65 class StaticInstPtr;
  66 class ResourceRequest;
  67
  68 class InOrderDynInst : public FastAlloc, public RefCounted
  69 {
  70   public:
  71     // Binary machine instruction type.
  72     typedef TheISA::MachInst MachInst;
  73     // Extended machine instruction type
  74     typedef TheISA::ExtMachInst ExtMachInst;
  75     // Logical register index type.
  76     typedef TheISA::RegIndex RegIndex;
  77     // Integer register type.
  78     typedef TheISA::IntReg IntReg;
  79     // Floating point register type.
  80     typedef TheISA::FloatReg FloatReg;
  81     // Floating point register type.
  82     typedef TheISA::MiscReg MiscReg;
  83
  84     typedef short int PhysRegIndex;
  85
  86     /** The refcounted DynInst pointer to be used.  In most cases this is
  87      *  what should be used, and not DynInst*.
  88      */
  89     typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
  90
  91     // The list of instructions iterator type.
  92     typedef std::list<DynInstPtr>::iterator ListIt;
  93
  94     enum {
  95         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
  96         MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
  97     };
  98
  99   public:
 100     /** BaseDynInst constructor given a binary instruction.
 101      *  @param inst The binary instruction.
 102      *  @param PC The PC of the instruction.
 103      *  @param pred_PC The predicted next PC.
 104      *  @param seq_num The sequence number of the instruction.
 105      *  @param cpu Pointer to the instruction's CPU.
 106      */
 107     InOrderDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
 108                  InOrderCPU *cpu);
 109
 110     /** BaseDynInst constructor given a binary instruction.
 111      *  @param seq_num The sequence number of the instruction.
 112      *  @param cpu Pointer to the instruction's CPU.
 113      *  NOTE: Must set Binary Instrution through Member Function
 114      */
 115     InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state, InstSeqNum seq_num,
 116                  unsigned tid);
 117
 118     /** BaseDynInst constructor given a StaticInst pointer.
 119      *  @param _staticInst The StaticInst for this BaseDynInst.
 120      */
 121     InOrderDynInst(StaticInstPtr &_staticInst);
 122
 123     /** Skeleton Constructor. */
 124     InOrderDynInst();
 125
 126     /** InOrderDynInst destructor. */
 127     ~InOrderDynInst();
 128
 129   public:
 130     /** The sequence number of the instruction. */
 131     InstSeqNum seqNum;
 132
 133     /** The sequence number of the instruction. */
 134     InstSeqNum bdelaySeqNum;
 135
 136     enum Status {
 137         RegDepMapEntry,          /// Instruction has been entered onto the RegDepMap
 138         IqEntry,                 /// Instruction is in the IQ
 139         RobEntry,                /// Instruction is in the ROB
 140         LsqEntry,                /// Instruction is in the LSQ
 141         Completed,               /// Instruction has completed
 142         ResultReady,             /// Instruction has its result
 143         CanIssue,                /// Instruction can issue and execute
 144         Issued,                  /// Instruction has issued
 145         Executed,                /// Instruction has executed
 146         CanCommit,               /// Instruction can commit
 147         AtCommit,                /// Instruction has reached commit
 148         Committed,               /// Instruction has committed
 149         Squashed,                /// Instruction is squashed
 150         SquashedInIQ,            /// Instruction is squashed in the IQ
 151         SquashedInLSQ,           /// Instruction is squashed in the LSQ
 152         SquashedInROB,           /// Instruction is squashed in the ROB
 153         RecoverInst,             /// Is a recover instruction
 154         BlockingInst,            /// Is a blocking instruction
 155         ThreadsyncWait,          /// Is a thread synchronization instruction
 156         SerializeBefore,         /// Needs to serialize on
 157                                  /// instructions ahead of it
 158         SerializeAfter,          /// Needs to serialize instructions behind it
 159         SerializeHandled,        /// Serialization has been handled
 160         NumStatus
 161     };
 162
 163     /** The status of this BaseDynInst.  Several bits can be set. */
 164     std::bitset<NumStatus> status;
 165
 166     /** The thread this instruction is from. */
 167     short threadNumber;
 168
 169     /** data address space ID, for loads & stores. */
 170     short asid;
 171
 172     /** The virtual processor number */
 173     short virtProcNumber;
 174
 175     /** The StaticInst used by this BaseDynInst. */
 176     StaticInstPtr staticInst;
 177
 178     /** InstRecord that tracks this instructions. */
 179     Trace::InOrderTraceRecord *traceData;
 180
 181     /** Pointer to the Impl's CPU object. */
 182     InOrderCPU *cpu;
 183
 184     /** Pointer to the thread state. */
 185     InOrderThreadState *thread;
 186
 187     /** The kind of fault this instruction has generated. */
 188     Fault fault;
 189
 190     /** The memory request. */
 191     Request *req;
 192
 193     /** Pointer to the data for the memory access. */
 194     uint8_t *memData;
 195
 196     /**  Data used for a store for operation. */
 197     uint64_t loadData;
 198
 199     /**  Data used for a store for operation. */
 200     uint64_t storeData;
 201
 202     /** The resource schedule for this inst */
 203     ThePipeline::ResSchedule resSched;
 204
 205     /** List of active resource requests for this instruction */
 206     std::list<ResourceRequest*> reqList;
 207
 208     /** The effective virtual address (lds & stores only). */
 209     Addr effAddr;
 210
 211     /** The effective physical address. */
 212     Addr physEffAddr;
 213
 214     /** Effective virtual address for a copy source. */
 215     Addr copySrcEffAddr;
 216
 217     /** Effective physical address for a copy source. */
 218     Addr copySrcPhysEffAddr;
 219
 220     /** The memory request flags (from translation). */
 221     unsigned memReqFlags;
 222
 223     /** How many source registers are ready. */
 224     unsigned readyRegs;
 225
 226     /** An instruction src/dest has to be one of these types */
 227     union InstValue {
 228         uint64_t integer;
 229         double dbl;
 230     };
 231
 232     //@TODO: Naming Convention for Enums?
 233     enum ResultType {
 234         None,
 235         Integer,
 236         Float,
 237         Double
 238     };
 239
 240
 241     /** Result of an instruction execution */
 242     struct InstResult {
 243         ResultType type;
 244         InstValue val;
 245         Tick tick;
 246
 247         InstResult()
 248             : type(None), tick(0)
 249         {}
 250     };
 251
 252     /** The source of the instruction; assumes for now that there's only one
 253      *  destination register.
 254      */
 255     InstValue instSrc[MaxInstSrcRegs];
 256
 257     /** The result of the instruction; assumes for now that there's only one
 258      *  destination register.
 259      */
 260     InstResult instResult[MaxInstDestRegs];
 261
 262     /** PC of this instruction. */
 263     Addr PC;
 264
 265     /** Next non-speculative PC.  It is not filled in at fetch, but rather
 266      *  once the target of the branch is truly known (either decode or
 267      *  execute).
 268      */
 269     Addr nextPC;
 270
 271     /** Next next non-speculative PC.  It is not filled in at fetch, but rather
 272      *  once the target of the branch is truly known (either decode or
 273      *  execute).
 274      */
 275     Addr nextNPC;
 276
 277     /** Predicted next PC. */
 278     Addr predPC;
 279
 280     /** Predicted next NPC. */
 281     Addr predNPC;
 282
 283     /** Predicted next microPC */
 284     Addr predMicroPC;
 285
 286     /** Address to fetch from */
 287     Addr fetchAddr;
 288
 289     /** Address to get/write data from/to */
 290     Addr memAddr;
 291
 292     /** Whether or not the source register is ready.
 293      *  @todo: Not sure this should be here vs the derived class.
 294      */
 295     bool _readySrcRegIdx[MaxInstSrcRegs];
 296
 297     /** Physical register index of the destination registers of this
 298      *  instruction.
 299      */
 300     PhysRegIndex _destRegIdx[MaxInstDestRegs];
 301
 302     /** Physical register index of the source registers of this
 303      *  instruction.
 304      */
 305     PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
 306
 307     /** Physical register index of the previous producers of the
 308      *  architected destinations.
 309      */
 310     PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
 311
 312     int nextStage;
 313
 314     /* vars to keep track of InstStage's - used for resource sched defn */
 315     int nextInstStageNum;
 316     ThePipeline::InstStage *currentInstStage;
 317     std::list<ThePipeline::InstStage*> instStageList;
 318
 319   private:
 320     /** Function to initialize variables in the constructors. */
 321     void initVars();
 322
 323   public:
 324     Tick memTime;
 325
 326     ////////////////////////////////////////////////////////////
 327     //
 328     //  BASE INSTRUCTION INFORMATION.
 329     //
 330     ////////////////////////////////////////////////////////////
 331     std::string instName() { return staticInst->getName(); }
 332
 333
 334     void setMachInst(ExtMachInst inst);
 335
 336     /** Sets the StaticInst. */
 337     void setStaticInst(StaticInstPtr &static_inst);
 338
 339     /** Sets the sequence number. */
 340     void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
 341
 342     /** Sets the ASID. */
 343     void setASID(short addr_space_id) { asid = addr_space_id; }
 344
 345     /** Reads the thread id. */
 346     short readTid() { return threadNumber; }
 347
 348     /** Sets the thread id. */
 349     void setTid(unsigned tid) { threadNumber = tid; }
 350
 351     void setVpn(int id) { virtProcNumber = id; }
 352
 353     int readVpn() { return virtProcNumber; }
 354
 355     /** Sets the pointer to the thread state. */
 356     void setThreadState(InOrderThreadState *state) { thread = state; }
 357
 358     /** Returns the thread context. */
 359     ThreadContext *tcBase() { return thread->getTC(); }
 360
 361     /** Returns the fault type. */
 362     Fault getFault() { return fault; }
 363
 364     ////////////////////////////////////////////////////////////
 365     //
 366     //  INSTRUCTION TYPES -  Forward checks to StaticInst object.
 367     //
 368     ////////////////////////////////////////////////////////////
 369     bool isNop()          const { return staticInst->isNop(); }
 370     bool isMemRef()       const { return staticInst->isMemRef(); }
 371     bool isLoad()         const { return staticInst->isLoad(); }
 372     bool isStore()        const { return staticInst->isStore(); }
 373     bool isStoreConditional() const
 374     { return staticInst->isStoreConditional(); }
 375     bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
 376     bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
 377     bool isCopy()         const { return staticInst->isCopy(); }
 378     bool isInteger()      const { return staticInst->isInteger(); }
 379     bool isFloating()     const { return staticInst->isFloating(); }
 380     bool isControl()      const { return staticInst->isControl(); }
 381     bool isCall()         const { return staticInst->isCall(); }
 382     bool isReturn()       const { return staticInst->isReturn(); }
 383     bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
 384     bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
 385     bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
 386     bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
 387     bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
 388
 389     bool isThreadSync()   const { return staticInst->isThreadSync(); }
 390     bool isSerializing()  const { return staticInst->isSerializing(); }
 391     bool isSerializeBefore() const
 392     { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
 393     bool isSerializeAfter() const
 394     { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
 395     bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
 396     bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
 397     bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
 398     bool isQuiesce() const { return staticInst->isQuiesce(); }
 399     bool isIprAccess() const { return staticInst->isIprAccess(); }
 400     bool isUnverifiable() const { return staticInst->isUnverifiable(); }
 401
 402     /////////////////////////////////////////////
 403     //
 404     // RESOURCE SCHEDULING
 405     //
 406     /////////////////////////////////////////////
 407
 408     void setNextStage(int stage_num) { nextStage = stage_num; }
 409     int getNextStage() { return nextStage; }
 410
 411     ThePipeline::InstStage *addStage();
 412     ThePipeline::InstStage *addStage(int stage);
 413     ThePipeline::InstStage *currentStage() { return currentInstStage; }
 414     void deleteStages();
 415
 416     /** Add A Entry To Reource Schedule */
 417     void addToSched(ThePipeline::ScheduleEntry* sched_entry)
 418     { resSched.push(sched_entry); }
 419
 420
 421     /** Print Resource Schedule */
 422     /** @NOTE: DEBUG ONLY */
 423     void printSched()
 424     {
 425         ThePipeline::ResSchedule tempSched;
 426         std::cerr << "\tInst. Res. Schedule: ";
 427         while (!resSched.empty()) {
 428             std::cerr << '\t' << resSched.top()->stageNum << "-"
 429                  << resSched.top()->resNum << ", ";
 430
 431             tempSched.push(resSched.top());
 432             resSched.pop();
 433         }
 434
 435         std::cerr << std::endl;
 436         resSched = tempSched;
 437     }
 438
 439     /** Return Next Resource Stage To Be Used */
 440     int nextResStage()
 441     {
 442         if (resSched.empty())
 443             return -1;
 444         else
 445             return resSched.top()->stageNum;
 446     }
 447
 448
 449     /** Return Next Resource To Be Used */
 450     int nextResource()
 451     {
 452         if (resSched.empty())
 453             return -1;
 454         else
 455             return resSched.top()->resNum;
 456     }
 457
 458     /** Remove & Deallocate a schedule entry */
 459     void popSchedEntry()
 460     {
 461         if (!resSched.empty()) {
 462             ThePipeline::ScheduleEntry* sked = resSched.top();
 463             resSched.pop();
 464             delete sked;
 465         }
 466     }
 467
 468     /** Release a Resource Request (Currently Unused) */
 469     void releaseReq(ResourceRequest* req);
 470
 471     ////////////////////////////////////////////
 472     //
 473     // INSTRUCTION EXECUTION
 474     //
 475     ////////////////////////////////////////////
 476     /** Returns the opclass of this instruction. */
 477     OpClass opClass() const { return staticInst->opClass(); }
 478
 479     /** Executes the instruction.*/
 480     Fault execute();
 481
 482     unsigned curResSlot;
 483
 484     unsigned getCurResSlot() { return curResSlot; }
 485
 486     void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
 487
 488     /** Calls a syscall. */
 489     void syscall(int64_t callnum);
 490     void prefetch(Addr addr, unsigned flags);
 491     void writeHint(Addr addr, int size, unsigned flags);
 492     Fault copySrcTranslate(Addr src);
 493     Fault copy(Addr dest);
 494
 495     ////////////////////////////////////////////////////////////
 496     //
 497     // MULTITHREADING INTERFACE TO CPU MODELS
 498     //
 499     ////////////////////////////////////////////////////////////
 500     virtual void deallocateContext(int thread_num);
 501
 502     virtual void enableVirtProcElement(unsigned vpe);
 503     virtual void disableVirtProcElement(unsigned vpe);
 504
 505     virtual void enableMultiThreading(unsigned vpe);
 506     virtual void disableMultiThreading(unsigned vpe);
 507
 508     ////////////////////////////////////////////////////////////
 509     //
 510     //  PROGRAM COUNTERS - PC/NPC/NPC
 511     //
 512     ////////////////////////////////////////////////////////////
 513     /** Read the PC of this instruction. */
 514     const Addr readPC() const { return PC; }
 515
 516     /** Sets the PC of this instruction. */
 517     void setPC(Addr pc) { PC = pc; }
 518
 519     /** Returns the next PC.  This could be the speculative next PC if it is
 520      *  called prior to the actual branch target being calculated.
 521      */
 522     Addr readNextPC() { return nextPC; }
 523
 524     /** Set the next PC of this instruction (its actual target). */
 525     void setNextPC(uint64_t val) { nextPC = val; }
 526
 527     /** Returns the next NPC.  This could be the speculative next NPC if it is
 528      *  called prior to the actual branch target being calculated.
 529      */
 530     Addr readNextNPC()
 531     {
 532 #if ISA_HAS_DELAY_SLOT
 533         return nextNPC;
 534 #else
 535         return nextPC + sizeof(TheISA::MachInst);
 536 #endif
 537     }
 538
 539     /** Set the next PC of this instruction (its actual target). */
 540     void setNextNPC(uint64_t val) { nextNPC = val; }
 541
 542     ////////////////////////////////////////////////////////////
 543     //
 544     // BRANCH PREDICTION
 545     //
 546     ////////////////////////////////////////////////////////////
 547     /** Set the predicted target of this current instruction. */
 548     void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
 549
 550     /** Returns the predicted target of the branch. */
 551     Addr readPredTarg() { return predPC; }
 552
 553     /** Returns the predicted PC immediately after the branch. */
 554     Addr readPredPC() { return predPC; }
 555
 556     /** Returns the predicted PC two instructions after the branch */
 557     Addr readPredNPC() { return predNPC; }
 558
 559     /** Returns the predicted micro PC after the branch */
 560     Addr readPredMicroPC() { return predMicroPC; }
 561
 562     /** Returns whether the instruction was predicted taken or not. */
 563     bool predTaken() { return predictTaken; }
 564
 565     /** Returns whether the instruction mispredicted. */
 566     bool mispredicted()
 567     {
 568 #if ISA_HAS_DELAY_SLOT
 569         return predPC != nextNPC;
 570 #else
 571         return predPC != nextPC;
 572 #endif
 573     }
 574
 575     /** Returns whether the instruction mispredicted. */
 576     bool mistargeted() { return predPC != nextNPC; }
 577
 578     /** Returns the branch target address. */
 579     Addr branchTarget() const { return staticInst->branchTarget(PC); }
 580
 581     /** Checks whether or not this instruction has had its branch target
 582      *  calculated yet.  For now it is not utilized and is hacked to be
 583      *  always false.
 584      *  @todo: Actually use this instruction.
 585      */
 586     bool doneTargCalc() { return false; }
 587
 588     void setBranchPred(bool prediction) { predictTaken = prediction; }
 589
 590     int squashingStage;
 591
 592     bool predictTaken;
 593
 594     bool procDelaySlotOnMispred;
 595
 596     ////////////////////////////////////////////
 597     //
 598     // MEMORY ACCESS
 599     //
 600     ////////////////////////////////////////////
 601     /**
 602      * Does a read to a given address.
 603      * @param addr The address to read.
 604      * @param data The read's data is written into this parameter.
 605      * @param flags The request's flags.
 606      * @return Returns any fault due to the read.
 607      */
 608     template <class T>
 609     Fault read(Addr addr, T &data, unsigned flags);
 610
 611     /**
 612      * Does a write to a given address.
 613      * @param data The data to be written.
 614      * @param addr The address to write to.
 615      * @param flags The request's flags.
 616      * @param res The result of the write (for load locked/store conditionals).
 617      * @return Returns any fault due to the write.
 618      */
 619     template <class T>
 620     Fault write(T data, Addr addr, unsigned flags,
 621                         uint64_t *res);
 622
 623     /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory Access
 624      *  Only valid for memory operations.
 625      */
 626     Fault initiateAcc();
 627
 628     /** Completes a memory access - Only valid for memory operations. */
 629     Fault completeAcc(Packet *pkt);
 630
 631     /** Calculates Eff. Addr.  part of a memory instruction.  */
 632     Fault calcEA();
 633
 634     /** Read Effective Address from instruction & do memory access */
 635     Fault memAccess();
 636
 637     RequestPtr memReq;
 638
 639     bool memAddrReady;
 640
 641     bool validMemAddr()
 642     { return memAddrReady; }
 643
 644     void setMemAddr(Addr addr)
 645     { memAddr = addr; memAddrReady = true;}
 646
 647     void unsetMemAddr()
 648     { memAddrReady = false;}
 649
 650     Addr getMemAddr()
 651     { return memAddr; }
 652
 653     int getMemAccSize() { return staticInst->memAccSize(this); }
 654
 655     int getMemFlags() { return staticInst->memAccFlags(); }
 656
 657     /** Sets the effective address. */
 658     void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
 659
 660     /** Returns the effective address. */
 661     const Addr &getEA() const { return instEffAddr; }
 662
 663     /** Returns whether or not the eff. addr. calculation has been completed. */
 664     bool doneEACalc() { return eaCalcDone; }
 665
 666     /** Returns whether or not the eff. addr. source registers are ready.
 667      *  Assume that src registers 1..n-1 are the ones that the
 668      *  EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 669      *  stored)
 670      */
 671     bool eaSrcsReady()
 672     {
 673         for (int i = 1; i < numSrcRegs(); ++i) {
 674             if (!_readySrcRegIdx[i])
 675                 return false;
 676         }
 677
 678         return true;
 679     }
 680
 681     //////////////////////////////////////////////////
 682     //
 683     // SOURCE-DESTINATION REGISTER INDEXING
 684     //
 685     //////////////////////////////////////////////////
 686     /** Returns the number of source registers. */
 687     int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
 688
 689     /** Returns the number of destination registers. */
 690     int8_t numDestRegs() const { return staticInst->numDestRegs(); }
 691
 692     // the following are used to track physical register usage
 693     // for machines with separate int & FP reg files
 694     int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
 695     int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
 696
 697     /** Returns the logical register index of the i'th destination register. */
 698     RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
 699
 700     /** Returns the logical register index of the i'th source register. */
 701     RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
 702
 703     //////////////////////////////////////////////////
 704     //
 705     // RENAME/PHYSICAL REGISTER FILE SUPPORT
 706     //
 707     //////////////////////////////////////////////////
 708     /** Returns the physical register index of the i'th destination
 709      *  register.
 710      */
 711     PhysRegIndex renamedDestRegIdx(int idx) const
 712     {
 713         return _destRegIdx[idx];
 714     }
 715
 716     /** Returns the physical register index of the i'th source register. */
 717     PhysRegIndex renamedSrcRegIdx(int idx) const
 718     {
 719         return _srcRegIdx[idx];
 720     }
 721
 722     /** Returns the physical register index of the previous physical register
 723      *  that remapped to the same logical register index.
 724      */
 725     PhysRegIndex prevDestRegIdx(int idx) const
 726     {
 727         return _prevDestRegIdx[idx];
 728     }
 729
 730     /** Returns if a source register is ready. */
 731     bool isReadySrcRegIdx(int idx) const
 732     {
 733         return this->_readySrcRegIdx[idx];
 734     }
 735
 736     /** Records that one of the source registers is ready. */
 737     void markSrcRegReady()
 738     {
 739         if (++readyRegs == numSrcRegs()) {
 740             status.set(CanIssue);
 741         }
 742     }
 743
 744     /** Marks a specific register as ready. */
 745     void markSrcRegReady(RegIndex src_idx)
 746     {
 747         _readySrcRegIdx[src_idx] = true;
 748
 749         markSrcRegReady();
 750     }
 751
 752     /** Renames a destination register to a physical register.  Also records
 753      *  the previous physical register that the logical register mapped to.
 754      */
 755     void renameDestReg(int idx,
 756                        PhysRegIndex renamed_dest,
 757                        PhysRegIndex previous_rename)
 758     {
 759         _destRegIdx[idx] = renamed_dest;
 760         _prevDestRegIdx[idx] = previous_rename;
 761     }
 762
 763     /** Renames a source logical register to the physical register which
 764      *  has/will produce that logical register's result.
 765      *  @todo: add in whether or not the source register is ready.
 766      */
 767     void renameSrcReg(int idx, PhysRegIndex renamed_src)
 768     {
 769         _srcRegIdx[idx] = renamed_src;
 770     }
 771
 772
 773     PhysRegIndex readDestRegIdx(int idx)
 774     {
 775         return _destRegIdx[idx];
 776     }
 777
 778     void setDestRegIdx(int idx, PhysRegIndex dest_idx)
 779     {
 780         _destRegIdx[idx] = dest_idx;
 781     }
 782
 783     int getDestIdxNum(PhysRegIndex dest_idx)
 784     {
 785         for (int i=0; i < staticInst->numDestRegs(); i++) {
 786             if (_destRegIdx[i] == dest_idx)
 787                 return i;
 788         }
 789
 790         return -1;
 791     }
 792
 793     PhysRegIndex readSrcRegIdx(int idx)
 794     {
 795         return _srcRegIdx[idx];
 796     }
 797
 798     void setSrcRegIdx(int idx, PhysRegIndex src_idx)
 799     {
 800         _srcRegIdx[idx] = src_idx;
 801     }
 802
 803     int getSrcIdxNum(PhysRegIndex src_idx)
 804     {
 805         for (int i=0; i < staticInst->numSrcRegs(); i++) {
 806             if (_srcRegIdx[i] == src_idx)
 807                 return i;
 808         }
 809
 810         return -1;
 811     }
 812
 813     ////////////////////////////////////////////////////
 814     //
 815     // SOURCE-DESTINATION REGISTER VALUES
 816     //
 817     ////////////////////////////////////////////////////
 818
 819     /** Functions that sets an integer or floating point
 820      *  source register to a value. */
 821     void setIntSrc(int idx, uint64_t val);
 822     void setFloatSrc(int idx, FloatReg val, int width = 32);
 823     void setFloatRegBitsSrc(int idx, uint64_t val);
 824
 825     uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
 826     uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
 827
 828     /** These Instructions read a integer/float/misc. source register
 829      *  value in the instruction. The instruction's execute function will
 830      *  call these and it is the interface that is used by the ISA descr.
 831      *  language (which is why the name isnt readIntSrc(...)) Note: That
 832      *  the source reg. value is set using the setSrcReg() function.
 833      */
 834     IntReg readIntRegOperand(const StaticInst *si, int idx, unsigned tid=0);
 835     FloatReg readFloatRegOperand(const StaticInst *si, int idx,
 836                           int width = TheISA::SingleWidth);
 837     TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
 838                                   int width = TheISA::SingleWidth);
 839     MiscReg readMiscReg(int misc_reg);
 840     MiscReg readMiscRegNoEffect(int misc_reg);
 841     MiscReg readMiscRegOperand(const StaticInst *si, int idx);
 842     MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
 843
 844     /** Returns the result value instruction. */
 845     ResultType resultType(int idx)
 846     {
 847         return instResult[idx].type;
 848     }
 849
 850     uint64_t readIntResult(int idx)
 851     {
 852         return instResult[idx].val.integer;
 853     }
 854
 855     /** Depending on type, return Float or Double */
 856     double readFloatResult(int idx)
 857     {
 858         //assert(instResult[idx].type != Integer && instResult[idx].type != None);
 859         //@todo: TypeCast FLOAT onto DOUBLE instead of separate value
 860        return (instResult[idx].type == Float) ?
 861            (float) instResult[idx].val.dbl : instResult[idx].val.dbl;
 862     }
 863
 864     double readDoubleResult(int idx)
 865     {
 866         assert(instResult[idx].type == Double);
 867         return instResult[idx].val.dbl;
 868     }
 869
 870     Tick readResultTime(int idx) { return instResult[idx].tick; }
 871
 872     uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
 873
 874     /** This is the interface that an instruction will use to write
 875      *  it's destination register.
 876      */
 877     void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
 878     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
 879                      int width = TheISA::SingleWidth);
 880     void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val,
 881                          int width = TheISA::SingleWidth);
 882     void setMiscReg(int misc_reg, const MiscReg &val);
 883     void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 884     void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
 885     void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val);
 886
 887     virtual uint64_t readRegOtherThread(unsigned idx, int tid = -1);
 888     virtual void setRegOtherThread(unsigned idx, const uint64_t &val, int tid = -1);
 889
 890     /** Sets the number of consecutive store conditional failures. */
 891     void setStCondFailures(unsigned sc_failures)
 892     { thread->storeCondFailures = sc_failures; }
 893
 894     //////////////////////////////////////////////////////////////
 895     //
 896     // INSTRUCTION STATUS FLAGS (READ/SET)
 897     //
 898     //////////////////////////////////////////////////////////////
 899     /** Sets this instruction as entered on the CPU Reg Dep Map */
 900     void setRegDepEntry() { status.set(RegDepMapEntry); }
 901
 902     /** Returns whether or not the entry is on the CPU Reg Dep Map */
 903     bool isRegDepEntry() const { return status[RegDepMapEntry]; }
 904
 905     /** Sets this instruction as completed. */
 906     void setCompleted() { status.set(Completed); }
 907
 908     /** Returns whether or not this instruction is completed. */
 909     bool isCompleted() const { return status[Completed]; }
 910
 911     /** Marks the result as ready. */
 912     void setResultReady() { status.set(ResultReady); }
 913
 914     /** Returns whether or not the result is ready. */
 915     bool isResultReady() const { return status[ResultReady]; }
 916
 917     /** Sets this instruction as ready to issue. */
 918     void setCanIssue() { status.set(CanIssue); }
 919
 920     /** Returns whether or not this instruction is ready to issue. */
 921     bool readyToIssue() const { return status[CanIssue]; }
 922
 923     /** Sets this instruction as issued from the IQ. */
 924     void setIssued() { status.set(Issued); }
 925
 926     /** Returns whether or not this instruction has issued. */
 927     bool isIssued() const { return status[Issued]; }
 928
 929     /** Sets this instruction as executed. */
 930     void setExecuted() { status.set(Executed); }
 931
 932     /** Returns whether or not this instruction has executed. */
 933     bool isExecuted() const { return status[Executed]; }
 934
 935     /** Sets this instruction as ready to commit. */
 936     void setCanCommit() { status.set(CanCommit); }
 937
 938     /** Clears this instruction as being ready to commit. */
 939     void clearCanCommit() { status.reset(CanCommit); }
 940
 941     /** Returns whether or not this instruction is ready to commit. */
 942     bool readyToCommit() const { return status[CanCommit]; }
 943
 944     void setAtCommit() { status.set(AtCommit); }
 945
 946     bool isAtCommit() { return status[AtCommit]; }
 947
 948     /** Sets this instruction as committed. */
 949     void setCommitted() { status.set(Committed); }
 950
 951     /** Returns whether or not this instruction is committed. */
 952     bool isCommitted() const { return status[Committed]; }
 953
 954     /** Sets this instruction as squashed. */
 955     void setSquashed() { status.set(Squashed); }
 956
 957     /** Returns whether or not this instruction is squashed. */
 958     bool isSquashed() const { return status[Squashed]; }
 959
 960     /** Temporarily sets this instruction as a serialize before instruction. */
 961     void setSerializeBefore() { status.set(SerializeBefore); }
 962
 963     /** Clears the serializeBefore part of this instruction. */
 964     void clearSerializeBefore() { status.reset(SerializeBefore); }
 965
 966     /** Checks if this serializeBefore is only temporarily set. */
 967     bool isTempSerializeBefore() { return status[SerializeBefore]; }
 968
 969     /** Temporarily sets this instruction as a serialize after instruction. */
 970     void setSerializeAfter() { status.set(SerializeAfter); }
 971
 972     /** Clears the serializeAfter part of this instruction.*/
 973     void clearSerializeAfter() { status.reset(SerializeAfter); }
 974
 975     /** Checks if this serializeAfter is only temporarily set. */
 976     bool isTempSerializeAfter() { return status[SerializeAfter]; }
 977
 978     /** Sets the serialization part of this instruction as handled. */
 979     void setSerializeHandled() { status.set(SerializeHandled); }
 980
 981     /** Checks if the serialization part of this instruction has been
 982      *  handled.  This does not apply to the temporary serializing
 983      *  state; it only applies to this instruction's own permanent
 984      *  serializing state.
 985      */
 986     bool isSerializeHandled() { return status[SerializeHandled]; }
 987
 988   private:
 989     /** Instruction effective address.
 990      *  @todo: Consider if this is necessary or not.
 991      */
 992     Addr instEffAddr;
 993
 994     /** Whether or not the effective address calculation is completed.
 995      *  @todo: Consider if this is necessary or not.
 996      */
 997     bool eaCalcDone;
 998
 999   public:
1000     /** Whether or not the memory operation is done. */
1001     bool memOpDone;
1002
1003   public:
1004     /** Load queue index. */
1005     int16_t lqIdx;
1006
1007     /** Store queue index. */
1008     int16_t sqIdx;
1009
1010     /** Iterator pointing to this BaseDynInst in the list of all insts. */
1011     ListIt instListIt;
1012
1013     /** Returns iterator to this instruction in the list of all insts. */
1014     ListIt &getInstListIt() { return instListIt; }
1015
1016     /** Sets iterator for this instruction in the list of all insts. */
1017     void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
1018
1019     /** Count of total number of dynamic instructions. */
1020     static int instcount;
1021
1022     /** Dumps out contents of this BaseDynInst. */
1023     void dump();
1024
1025     /** Dumps out contents of this BaseDynInst into given string. */
1026     void dump(std::string &outstring);
1027
1028
1029   //inline int curCount() { return curCount(); }
1030 };
1031
1032
1033 #endif // __CPU_BASE_DYN_INST_HH__