2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2004-2006 The Regents of The University of Michigan
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33 #ifndef __CPU_INORDER_DYN_INST_HH__
34 #define __CPU_INORDER_DYN_INST_HH__
40 #include "arch/faults.hh"
41 #include "arch/isa_traits.hh"
43 #include "arch/types.hh"
44 #include "arch/utility.hh"
45 #include "base/fast_alloc.hh"
46 #include "base/trace.hh"
47 #include "base/types.hh"
48 #include "config/full_system.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/exetrace.hh"
51 #include "cpu/inorder/inorder_trace.hh"
52 #include "cpu/inorder/pipeline_traits.hh"
53 #include "cpu/inorder/resource.hh"
54 #include "cpu/inorder/resource_sked.hh"
55 #include "cpu/inorder/thread_state.hh"
56 #include "cpu/inst_seq.hh"
57 #include "cpu/op_class.hh"
58 #include "cpu/static_inst.hh"
59 #include "cpu/thread_context.hh"
60 #include "mem/packet.hh"
61 #include "sim/system.hh"
63 #if THE_ISA == ALPHA_ISA
64 #include "arch/alpha/ev5.hh"
69 * Defines a dynamic instruction context for a inorder CPU model.
72 // Forward declaration.
74 class ResourceRequest;
77 class InOrderDynInst : public FastAlloc, public RefCounted
80 // Binary machine instruction type.
81 typedef TheISA::MachInst MachInst;
82 // Extended machine instruction type
83 typedef TheISA::ExtMachInst ExtMachInst;
84 // Logical register index type.
85 typedef TheISA::RegIndex RegIndex;
86 // Integer register type.
87 typedef TheISA::IntReg IntReg;
88 // Floating point register type.
89 typedef TheISA::FloatReg FloatReg;
90 // Floating point register type.
91 typedef TheISA::MiscReg MiscReg;
93 typedef short int PhysRegIndex;
95 /** The refcounted DynInst pointer to be used. In most cases this is
96 * what should be used, and not DynInst*.
98 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
100 // The list of instructions iterator type.
101 typedef std::list<DynInstPtr>::iterator ListIt;
104 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
105 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
109 /** BaseDynInst constructor given a binary instruction.
110 * @param inst The binary instruction.
111 * @param PC The PC of the instruction.
112 * @param predPC The predicted next PC.
113 * @param seq_num The sequence number of the instruction.
114 * @param cpu Pointer to the instruction's CPU.
116 InOrderDynInst(ExtMachInst inst, const TheISA::PCState &PC,
117 const TheISA::PCState &predPC, InstSeqNum seq_num,
120 /** BaseDynInst constructor given a binary instruction.
121 * @param seq_num The sequence number of the instruction.
122 * @param cpu Pointer to the instruction's CPU.
123 * NOTE: Must set Binary Instrution through Member Function
125 InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
126 InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
128 /** BaseDynInst constructor given a StaticInst pointer.
129 * @param _staticInst The StaticInst for this BaseDynInst.
131 InOrderDynInst(StaticInstPtr &_staticInst);
133 /** Skeleton Constructor. */
136 /** InOrderDynInst destructor. */
140 /** The sequence number of the instruction. */
143 /** The sequence number of the instruction. */
144 InstSeqNum bdelaySeqNum;
147 RegDepMapEntry, /// Instruction is entered onto the RegDepMap
148 IqEntry, /// Instruction is in the IQ
149 RobEntry, /// Instruction is in the ROB
150 LsqEntry, /// Instruction is in the LSQ
151 Completed, /// Instruction has completed
152 ResultReady, /// Instruction has its result
153 CanIssue, /// Instruction can issue and execute
154 Issued, /// Instruction has issued
155 Executed, /// Instruction has executed
156 CanCommit, /// Instruction can commit
157 AtCommit, /// Instruction has reached commit
158 Committed, /// Instruction has committed
159 Squashed, /// Instruction is squashed
160 SquashedInIQ, /// Instruction is squashed in the IQ
161 SquashedInLSQ, /// Instruction is squashed in the LSQ
162 SquashedInROB, /// Instruction is squashed in the ROB
163 RecoverInst, /// Is a recover instruction
164 BlockingInst, /// Is a blocking instruction
165 ThreadsyncWait, /// Is a thread synchronization instruction
166 SerializeBefore, /// Needs to serialize on
167 /// instructions ahead of it
168 SerializeAfter, /// Needs to serialize instructions behind it
169 SerializeHandled, /// Serialization has been handled
170 RemoveList, /// Is Instruction on Remove List?
174 /** The status of this BaseDynInst. Several bits can be set. */
175 std::bitset<NumStatus> status;
177 /** The thread this instruction is from. */
180 /** data address space ID, for loads & stores. */
183 /** The virtual processor number */
184 short virtProcNumber;
186 /** The StaticInst used by this BaseDynInst. */
187 StaticInstPtr staticInst;
189 /** InstRecord that tracks this instructions. */
190 Trace::InOrderTraceRecord *traceData;
192 /** Pointer to the Impl's CPU object. */
195 /** Pointer to the thread state. */
196 InOrderThreadState *thread;
198 /** The kind of fault this instruction has generated. */
201 /** The memory request. */
204 /** Pointer to the data for the memory access. */
207 /** Data used for a store for operation. */
210 /** Data used for a store for operation. */
213 /** List of active resource requests for this instruction */
214 std::list<ResourceRequest*> reqList;
216 /** The effective virtual address (lds & stores only). */
219 /** The effective physical address. */
222 /** Effective virtual address for a copy source. */
225 /** Effective physical address for a copy source. */
226 Addr copySrcPhysEffAddr;
228 /** The memory request flags (from translation). */
229 unsigned memReqFlags;
231 /** How many source registers are ready. */
234 /** An instruction src/dest has to be one of these types */
240 //@TODO: Naming Convention for Enums?
249 /** Result of an instruction execution */
256 : type(None), tick(0)
260 /** The source of the instruction; assumes for now that there's only one
261 * destination register.
263 InstValue instSrc[MaxInstSrcRegs];
265 /** The result of the instruction; assumes for now that there's only one
266 * destination register.
268 InstResult instResult[MaxInstDestRegs];
270 /** PC of this instruction. */
273 /** Predicted next PC. */
274 TheISA::PCState predPC;
276 /** Address to fetch from */
279 /** Address to get/write data from/to */
282 /** Whether or not the source register is ready.
283 * @todo: Not sure this should be here vs the derived class.
285 bool _readySrcRegIdx[MaxInstSrcRegs];
287 /** Physical register index of the destination registers of this
290 PhysRegIndex _destRegIdx[MaxInstDestRegs];
292 /** Physical register index of the source registers of this
295 PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
297 /** Physical register index of the previous producers of the
298 * architected destinations.
300 PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
305 /** Function to initialize variables in the constructors. */
311 PacketDataPtr splitMemData;
312 RequestPtr splitMemReq;
317 uint8_t split2ndData;
318 PacketDataPtr split2ndDataPtr;
319 unsigned split2ndFlags;
322 uint64_t *split2ndStoreDataPtr;
325 ////////////////////////////////////////////////////////////
327 // BASE INSTRUCTION INFORMATION.
329 ////////////////////////////////////////////////////////////
330 std::string instName() { return staticInst->getName(); }
332 void setMachInst(ExtMachInst inst);
334 ExtMachInst getMachInst() { return staticInst->machInst; }
336 /** Sets the StaticInst. */
337 void setStaticInst(StaticInstPtr &static_inst);
339 /** Sets the sequence number. */
340 void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
342 /** Sets the ASID. */
343 void setASID(short addr_space_id) { asid = addr_space_id; }
345 /** Reads the thread id. */
346 short readTid() { return threadNumber; }
348 /** Sets the thread id. */
349 void setTid(ThreadID tid) { threadNumber = tid; }
351 void setVpn(int id) { virtProcNumber = id; }
353 int readVpn() { return virtProcNumber; }
355 /** Sets the pointer to the thread state. */
356 void setThreadState(InOrderThreadState *state) { thread = state; }
358 /** Returns the thread context. */
359 ThreadContext *tcBase() { return thread->getTC(); }
361 /** Returns the fault type. */
362 Fault getFault() { return fault; }
364 ////////////////////////////////////////////////////////////
366 // INSTRUCTION TYPES - Forward checks to StaticInst object.
368 ////////////////////////////////////////////////////////////
369 bool isNop() const { return staticInst->isNop(); }
370 bool isMemRef() const { return staticInst->isMemRef(); }
371 bool isLoad() const { return staticInst->isLoad(); }
372 bool isStore() const { return staticInst->isStore(); }
373 bool isStoreConditional() const
374 { return staticInst->isStoreConditional(); }
375 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
376 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
377 bool isCopy() const { return staticInst->isCopy(); }
378 bool isInteger() const { return staticInst->isInteger(); }
379 bool isFloating() const { return staticInst->isFloating(); }
380 bool isControl() const { return staticInst->isControl(); }
381 bool isCall() const { return staticInst->isCall(); }
382 bool isReturn() const { return staticInst->isReturn(); }
383 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
384 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
385 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
386 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
387 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
389 bool isThreadSync() const { return staticInst->isThreadSync(); }
390 bool isSerializing() const { return staticInst->isSerializing(); }
391 bool isSerializeBefore() const
392 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
393 bool isSerializeAfter() const
394 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
395 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
396 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
397 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
398 bool isQuiesce() const { return staticInst->isQuiesce(); }
399 bool isIprAccess() const { return staticInst->isIprAccess(); }
400 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
402 /////////////////////////////////////////////
404 // RESOURCE SCHEDULING
406 /////////////////////////////////////////////
407 typedef ThePipeline::RSkedPtr RSkedPtr;
411 RSkedIt frontSked_end;
414 RSkedIt backSked_end;
416 RSkedIt curSkedEntry;
418 void setFrontSked(RSkedPtr front_sked)
420 frontSked = front_sked;
421 frontSked_end.init(frontSked);
422 frontSked_end = frontSked->end();
423 //DPRINTF(InOrderDynInst, "Set FrontSked End to : %x \n" ,
424 // frontSked_end.getIt()/*, frontSked->end()*/);
425 //assert(frontSked_end == frontSked->end());
427 // This initializes instruction to be able
428 // to walk the resource schedule
429 curSkedEntry.init(frontSked);
430 curSkedEntry = frontSked->begin();
433 void setBackSked(RSkedPtr back_sked)
435 backSked = back_sked;
436 backSked_end.init(backSked);
437 backSked_end = backSked->end();
440 void setNextStage(int stage_num) { nextStage = stage_num; }
441 int getNextStage() { return nextStage; }
443 /** Print Resource Schedule */
446 if (frontSked != NULL) {
450 if (backSked != NULL) {
455 /** Return Next Resource Stage To Be Used */
458 assert((inFrontEnd && curSkedEntry != frontSked_end) ||
459 (!inFrontEnd && curSkedEntry != backSked_end));
461 return curSkedEntry->stageNum;
465 /** Return Next Resource To Be Used */
468 assert((inFrontEnd && curSkedEntry != frontSked_end) ||
469 (!inFrontEnd && curSkedEntry != backSked_end));
471 return curSkedEntry->resNum;
474 /** Finish using a schedule entry, increment to next entry */
475 bool finishSkedEntry()
479 if (inFrontEnd && curSkedEntry == frontSked_end) {
480 assert(backSked != NULL);
481 curSkedEntry.init(backSked);
482 curSkedEntry = backSked->begin();
484 } else if (!inFrontEnd && curSkedEntry == backSked_end) {
491 /** Release a Resource Request (Currently Unused) */
492 void releaseReq(ResourceRequest* req);
494 ////////////////////////////////////////////
496 // INSTRUCTION EXECUTION
498 ////////////////////////////////////////////
499 /** Returns the opclass of this instruction. */
500 OpClass opClass() const { return staticInst->opClass(); }
502 /** Executes the instruction.*/
507 unsigned getCurResSlot() { return curResSlot; }
509 void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
511 /** Calls a syscall. */
513 /** Calls hardware return from error interrupt. */
515 /** Traps to handle specified fault. */
516 void trap(Fault fault);
517 bool simPalCheck(int palFunc);
519 /** Calls a syscall. */
520 void syscall(int64_t callnum);
523 ////////////////////////////////////////////////////////////
525 // MULTITHREADING INTERFACE TO CPU MODELS
527 ////////////////////////////////////////////////////////////
528 virtual void deallocateContext(int thread_num);
530 ////////////////////////////////////////////////////////////
532 // PROGRAM COUNTERS - PC/NPC/NPC
534 ////////////////////////////////////////////////////////////
535 /** Read the PC of this instruction. */
536 const TheISA::PCState &pcState() const { return pc; }
538 /** Sets the PC of this instruction. */
539 void pcState(const TheISA::PCState &_pc) { pc = _pc; }
541 const Addr instAddr() { return pc.instAddr(); }
542 const Addr nextInstAddr() { return pc.nextInstAddr(); }
543 const MicroPC microPC() { return pc.microPC(); }
545 ////////////////////////////////////////////////////////////
549 ////////////////////////////////////////////////////////////
550 /** Set the predicted target of this current instruction. */
551 void setPredTarg(const TheISA::PCState &predictedPC)
552 { predPC = predictedPC; }
554 /** Returns the predicted target of the branch. */
555 TheISA::PCState readPredTarg() { return predPC; }
557 /** Returns the predicted PC immediately after the branch. */
558 Addr predInstAddr() { return predPC.instAddr(); }
560 /** Returns the predicted PC two instructions after the branch */
561 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
563 /** Returns the predicted micro PC after the branch */
564 Addr readPredMicroPC() { return predPC.microPC(); }
566 /** Returns whether the instruction was predicted taken or not. */
567 bool predTaken() { return predictTaken; }
569 /** Returns whether the instruction mispredicted. */
573 TheISA::PCState nextPC = pc;
574 TheISA::advancePC(nextPC, staticInst);
575 return !(nextPC == predPC);
578 /** Returns the branch target address. */
579 TheISA::PCState branchTarget() const
580 { return staticInst->branchTarget(pc); }
582 /** Checks whether or not this instruction has had its branch target
583 * calculated yet. For now it is not utilized and is hacked to be
585 * @todo: Actually use this instruction.
587 bool doneTargCalc() { return false; }
589 void setBranchPred(bool prediction) { predictTaken = prediction; }
595 bool procDelaySlotOnMispred;
597 ////////////////////////////////////////////
601 ////////////////////////////////////////////
603 * Does a read to a given address.
604 * @param addr The address to read.
605 * @param data The read's data is written into this parameter.
606 * @param flags The request's flags.
607 * @return Returns any fault due to the read.
610 Fault read(Addr addr, T &data, unsigned flags);
612 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
615 * Does a write to a given address.
616 * @param data The data to be written.
617 * @param addr The address to write to.
618 * @param flags The request's flags.
619 * @param res The result of the write (for load locked/store conditionals).
620 * @return Returns any fault due to the write.
623 Fault write(T data, Addr addr, unsigned flags,
626 Fault writeBytes(uint8_t *data, unsigned size,
627 Addr addr, unsigned flags, uint64_t *res);
629 /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
630 * Access Only valid for memory operations.
634 /** Completes a memory access - Only valid for memory operations. */
635 Fault completeAcc(Packet *pkt);
637 /** Calculates Eff. Addr. part of a memory instruction. */
640 /** Read Effective Address from instruction & do memory access */
643 RequestPtr fetchMemReq;
644 RequestPtr dataMemReq;
649 { return memAddrReady; }
651 void setMemAddr(Addr addr)
652 { memAddr = addr; memAddrReady = true;}
655 { memAddrReady = false;}
660 /** Sets the effective address. */
661 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
663 /** Returns the effective address. */
664 const Addr &getEA() const { return instEffAddr; }
666 /** Returns whether or not the eff. addr. calculation has been completed.*/
667 bool doneEACalc() { return eaCalcDone; }
669 /** Returns whether or not the eff. addr. source registers are ready.
670 * Assume that src registers 1..n-1 are the ones that the
671 * EA calc depends on. (i.e. src reg 0 is the source of the data to be
676 for (int i = 1; i < numSrcRegs(); ++i) {
677 if (!_readySrcRegIdx[i])
684 //////////////////////////////////////////////////
686 // SOURCE-DESTINATION REGISTER INDEXING
688 //////////////////////////////////////////////////
689 /** Returns the number of source registers. */
690 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
692 /** Returns the number of destination registers. */
693 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
695 // the following are used to track physical register usage
696 // for machines with separate int & FP reg files
697 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
698 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
700 /** Returns the logical register index of the i'th destination register. */
701 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
703 /** Returns the logical register index of the i'th source register. */
704 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
706 //////////////////////////////////////////////////
708 // RENAME/PHYSICAL REGISTER FILE SUPPORT
710 //////////////////////////////////////////////////
711 /** Returns the physical register index of the i'th destination
714 PhysRegIndex renamedDestRegIdx(int idx) const
716 return _destRegIdx[idx];
719 /** Returns the physical register index of the i'th source register. */
720 PhysRegIndex renamedSrcRegIdx(int idx) const
722 return _srcRegIdx[idx];
725 /** Returns the physical register index of the previous physical register
726 * that remapped to the same logical register index.
728 PhysRegIndex prevDestRegIdx(int idx) const
730 return _prevDestRegIdx[idx];
733 /** Returns if a source register is ready. */
734 bool isReadySrcRegIdx(int idx) const
736 return this->_readySrcRegIdx[idx];
739 /** Records that one of the source registers is ready. */
740 void markSrcRegReady()
742 if (++readyRegs == numSrcRegs()) {
743 status.set(CanIssue);
747 /** Marks a specific register as ready. */
748 void markSrcRegReady(RegIndex src_idx)
750 _readySrcRegIdx[src_idx] = true;
755 /** Renames a destination register to a physical register. Also records
756 * the previous physical register that the logical register mapped to.
758 void renameDestReg(int idx,
759 PhysRegIndex renamed_dest,
760 PhysRegIndex previous_rename)
762 _destRegIdx[idx] = renamed_dest;
763 _prevDestRegIdx[idx] = previous_rename;
766 /** Renames a source logical register to the physical register which
767 * has/will produce that logical register's result.
768 * @todo: add in whether or not the source register is ready.
770 void renameSrcReg(int idx, PhysRegIndex renamed_src)
772 _srcRegIdx[idx] = renamed_src;
776 PhysRegIndex readDestRegIdx(int idx)
778 return _destRegIdx[idx];
781 void setDestRegIdx(int idx, PhysRegIndex dest_idx)
783 _destRegIdx[idx] = dest_idx;
786 int getDestIdxNum(PhysRegIndex dest_idx)
788 for (int i=0; i < staticInst->numDestRegs(); i++) {
789 if (_destRegIdx[i] == dest_idx)
796 PhysRegIndex readSrcRegIdx(int idx)
798 return _srcRegIdx[idx];
801 void setSrcRegIdx(int idx, PhysRegIndex src_idx)
803 _srcRegIdx[idx] = src_idx;
806 int getSrcIdxNum(PhysRegIndex src_idx)
808 for (int i=0; i < staticInst->numSrcRegs(); i++) {
809 if (_srcRegIdx[i] == src_idx)
816 ////////////////////////////////////////////////////
818 // SOURCE-DESTINATION REGISTER VALUES
820 ////////////////////////////////////////////////////
822 /** Functions that sets an integer or floating point
823 * source register to a value. */
824 void setIntSrc(int idx, uint64_t val);
825 void setFloatSrc(int idx, FloatReg val);
826 void setFloatRegBitsSrc(int idx, uint64_t val);
828 uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
829 uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
831 /** These Instructions read a integer/float/misc. source register
832 * value in the instruction. The instruction's execute function will
833 * call these and it is the interface that is used by the ISA descr.
834 * language (which is why the name isnt readIntSrc(...)) Note: That
835 * the source reg. value is set using the setSrcReg() function.
837 IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
838 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
839 TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
840 MiscReg readMiscReg(int misc_reg);
841 MiscReg readMiscRegNoEffect(int misc_reg);
842 MiscReg readMiscRegOperand(const StaticInst *si, int idx);
843 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
845 /** Returns the result value instruction. */
846 ResultType resultType(int idx)
848 return instResult[idx].type;
851 uint64_t readIntResult(int idx)
853 return instResult[idx].val.integer;
856 /** Depending on type, return Float or Double */
857 double readFloatResult(int idx)
859 return instResult[idx].val.dbl;
862 Tick readResultTime(int idx) { return instResult[idx].tick; }
864 uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
866 /** This is the interface that an instruction will use to write
867 * it's destination register.
869 void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
870 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
871 void setFloatRegOperandBits(const StaticInst *si, int idx,
872 TheISA::FloatRegBits val);
873 void setMiscReg(int misc_reg, const MiscReg &val);
874 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
875 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
876 void setMiscRegOperandNoEffect(const StaticInst *si, int idx,
879 virtual uint64_t readRegOtherThread(unsigned idx,
880 ThreadID tid = InvalidThreadID);
881 virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
882 ThreadID tid = InvalidThreadID);
884 /** Sets the number of consecutive store conditional failures. */
885 void setStCondFailures(unsigned sc_failures)
886 { thread->storeCondFailures = sc_failures; }
888 //////////////////////////////////////////////////////////////
890 // INSTRUCTION STATUS FLAGS (READ/SET)
892 //////////////////////////////////////////////////////////////
893 /** Sets this instruction as entered on the CPU Reg Dep Map */
894 void setRegDepEntry() { status.set(RegDepMapEntry); }
896 /** Returns whether or not the entry is on the CPU Reg Dep Map */
897 bool isRegDepEntry() const { return status[RegDepMapEntry]; }
899 /** Sets this instruction as entered on the CPU Reg Dep Map */
900 void setRemoveList() { status.set(RemoveList); }
902 /** Returns whether or not the entry is on the CPU Reg Dep Map */
903 bool isRemoveList() const { return status[RemoveList]; }
905 /** Sets this instruction as completed. */
906 void setCompleted() { status.set(Completed); }
908 /** Returns whether or not this instruction is completed. */
909 bool isCompleted() const { return status[Completed]; }
911 /** Marks the result as ready. */
912 void setResultReady() { status.set(ResultReady); }
914 /** Returns whether or not the result is ready. */
915 bool isResultReady() const { return status[ResultReady]; }
917 /** Sets this instruction as ready to issue. */
918 void setCanIssue() { status.set(CanIssue); }
920 /** Returns whether or not this instruction is ready to issue. */
921 bool readyToIssue() const { return status[CanIssue]; }
923 /** Sets this instruction as issued from the IQ. */
924 void setIssued() { status.set(Issued); }
926 /** Returns whether or not this instruction has issued. */
927 bool isIssued() const { return status[Issued]; }
929 /** Sets this instruction as executed. */
930 void setExecuted() { status.set(Executed); }
932 /** Returns whether or not this instruction has executed. */
933 bool isExecuted() const { return status[Executed]; }
935 /** Sets this instruction as ready to commit. */
936 void setCanCommit() { status.set(CanCommit); }
938 /** Clears this instruction as being ready to commit. */
939 void clearCanCommit() { status.reset(CanCommit); }
941 /** Returns whether or not this instruction is ready to commit. */
942 bool readyToCommit() const { return status[CanCommit]; }
944 void setAtCommit() { status.set(AtCommit); }
946 bool isAtCommit() { return status[AtCommit]; }
948 /** Sets this instruction as committed. */
949 void setCommitted() { status.set(Committed); }
951 /** Returns whether or not this instruction is committed. */
952 bool isCommitted() const { return status[Committed]; }
954 /** Sets this instruction as squashed. */
955 void setSquashed() { status.set(Squashed); }
957 /** Returns whether or not this instruction is squashed. */
958 bool isSquashed() const { return status[Squashed]; }
960 /** Temporarily sets this instruction as a serialize before instruction. */
961 void setSerializeBefore() { status.set(SerializeBefore); }
963 /** Clears the serializeBefore part of this instruction. */
964 void clearSerializeBefore() { status.reset(SerializeBefore); }
966 /** Checks if this serializeBefore is only temporarily set. */
967 bool isTempSerializeBefore() { return status[SerializeBefore]; }
969 /** Temporarily sets this instruction as a serialize after instruction. */
970 void setSerializeAfter() { status.set(SerializeAfter); }
972 /** Clears the serializeAfter part of this instruction.*/
973 void clearSerializeAfter() { status.reset(SerializeAfter); }
975 /** Checks if this serializeAfter is only temporarily set. */
976 bool isTempSerializeAfter() { return status[SerializeAfter]; }
978 /** Sets the serialization part of this instruction as handled. */
979 void setSerializeHandled() { status.set(SerializeHandled); }
981 /** Checks if the serialization part of this instruction has been
982 * handled. This does not apply to the temporary serializing
983 * state; it only applies to this instruction's own permanent
986 bool isSerializeHandled() { return status[SerializeHandled]; }
989 /** Instruction effective address.
990 * @todo: Consider if this is necessary or not.
994 /** Whether or not the effective address calculation is completed.
995 * @todo: Consider if this is necessary or not.
1000 /** Whether or not the memory operation is done. */
1004 /** Load queue index. */
1007 /** Store queue index. */
1010 /** Iterator pointing to this BaseDynInst in the list of all insts. */
1013 /** Returns iterator to this instruction in the list of all insts. */
1014 ListIt &getInstListIt() { return instListIt; }
1016 /** Sets iterator for this instruction in the list of all insts. */
1017 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
1019 /** Count of total number of dynamic instructions. */
1020 static int instcount;
1022 void resetInstCount();
1024 /** Dumps out contents of this BaseDynInst. */
1027 /** Dumps out contents of this BaseDynInst into given string. */
1028 void dump(std::string &outstring);
1030 //inline int curCount() { return curCount(); }
1034 #endif // __CPU_BASE_DYN_INST_HH__