src/cpu/inorder/inorder_dyn_inst.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Kevin Lim
  30  *          Korey Sewell
  31  */
  32
  33 #ifndef __CPU_INORDER_DYN_INST_HH__
  34 #define __CPU_INORDER_DYN_INST_HH__
  35
  36 #include <bitset>
  37 #include <list>
  38 #include <string>
  39
  40 #include "arch/faults.hh"
  41 #include "base/fast_alloc.hh"
  42 #include "base/trace.hh"
  43 #include "cpu/inorder/inorder_trace.hh"
  44 #include "config/full_system.hh"
  45 #include "cpu/thread_context.hh"
  46 #include "cpu/exetrace.hh"
  47 #include "cpu/inst_seq.hh"
  48 #include "cpu/op_class.hh"
  49 #include "cpu/static_inst.hh"
  50 #include "cpu/inorder/thread_state.hh"
  51 #include "cpu/inorder/resource.hh"
  52 #include "cpu/inorder/pipeline_traits.hh"
  53 #include "mem/packet.hh"
  54 #include "sim/system.hh"
  55
  56 /**
  57  * @file
  58  * Defines a dynamic instruction context for a inorder CPU model.
  59  */
  60
  61 // Forward declaration.
  62 class StaticInstPtr;
  63 class ResourceRequest;
  64
  65 class InOrderDynInst : public FastAlloc, public RefCounted
  66 {
  67   public:
  68     // Binary machine instruction type.
  69     typedef TheISA::MachInst MachInst;
  70     // Extended machine instruction type
  71     typedef TheISA::ExtMachInst ExtMachInst;
  72     // Logical register index type.
  73     typedef TheISA::RegIndex RegIndex;
  74     // Integer register type.
  75     typedef TheISA::IntReg IntReg;
  76     // Floating point register type.
  77     typedef TheISA::FloatReg FloatReg;
  78     // Floating point register type.
  79     typedef TheISA::MiscReg MiscReg;
  80
  81     typedef short int PhysRegIndex;
  82
  83     /** The refcounted DynInst pointer to be used.  In most cases this is
  84      *  what should be used, and not DynInst*.
  85      */
  86     typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
  87
  88     // The list of instructions iterator type.
  89     typedef std::list<DynInstPtr>::iterator ListIt;
  90
  91     enum {
  92         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
  93         MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
  94     };
  95
  96   public:
  97     /** BaseDynInst constructor given a binary instruction.
  98      *  @param inst The binary instruction.
  99      *  @param PC The PC of the instruction.
 100      *  @param pred_PC The predicted next PC.
 101      *  @param seq_num The sequence number of the instruction.
 102      *  @param cpu Pointer to the instruction's CPU.
 103      */
 104     InOrderDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
 105                  InOrderCPU *cpu);
 106
 107     /** BaseDynInst constructor given a binary instruction.
 108      *  @param seq_num The sequence number of the instruction.
 109      *  @param cpu Pointer to the instruction's CPU.
 110      *  NOTE: Must set Binary Instrution through Member Function
 111      */
 112     InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state, InstSeqNum seq_num,
 113                  unsigned tid);
 114
 115     /** BaseDynInst constructor given a StaticInst pointer.
 116      *  @param _staticInst The StaticInst for this BaseDynInst.
 117      */
 118     InOrderDynInst(StaticInstPtr &_staticInst);
 119
 120     /** Skeleton Constructor. */
 121     InOrderDynInst();
 122
 123     /** InOrderDynInst destructor. */
 124     ~InOrderDynInst();
 125
 126   public:
 127     /** The sequence number of the instruction. */
 128     InstSeqNum seqNum;
 129
 130     /** The sequence number of the instruction. */
 131     InstSeqNum bdelaySeqNum;
 132
 133     enum Status {
 134         RegDepMapEntry,          /// Instruction has been entered onto the RegDepMap
 135         IqEntry,                 /// Instruction is in the IQ
 136         RobEntry,                /// Instruction is in the ROB
 137         LsqEntry,                /// Instruction is in the LSQ
 138         Completed,               /// Instruction has completed
 139         ResultReady,             /// Instruction has its result
 140         CanIssue,                /// Instruction can issue and execute
 141         Issued,                  /// Instruction has issued
 142         Executed,                /// Instruction has executed
 143         CanCommit,               /// Instruction can commit
 144         AtCommit,                /// Instruction has reached commit
 145         Committed,               /// Instruction has committed
 146         Squashed,                /// Instruction is squashed
 147         SquashedInIQ,            /// Instruction is squashed in the IQ
 148         SquashedInLSQ,           /// Instruction is squashed in the LSQ
 149         SquashedInROB,           /// Instruction is squashed in the ROB
 150         RecoverInst,             /// Is a recover instruction
 151         BlockingInst,            /// Is a blocking instruction
 152         ThreadsyncWait,          /// Is a thread synchronization instruction
 153         SerializeBefore,         /// Needs to serialize on
 154                                  /// instructions ahead of it
 155         SerializeAfter,          /// Needs to serialize instructions behind it
 156         SerializeHandled,        /// Serialization has been handled
 157         NumStatus
 158     };
 159
 160     /** The status of this BaseDynInst.  Several bits can be set. */
 161     std::bitset<NumStatus> status;
 162
 163     /** The thread this instruction is from. */
 164     short threadNumber;
 165
 166     /** data address space ID, for loads & stores. */
 167     short asid;
 168
 169     /** The virtual processor number */
 170     short virtProcNumber;
 171
 172     /** The StaticInst used by this BaseDynInst. */
 173     StaticInstPtr staticInst;
 174
 175     /** InstRecord that tracks this instructions. */
 176     Trace::InOrderTraceRecord *traceData;
 177
 178     /** Pointer to the Impl's CPU object. */
 179     InOrderCPU *cpu;
 180
 181     /** Pointer to the thread state. */
 182     InOrderThreadState *thread;
 183
 184     /** The kind of fault this instruction has generated. */
 185     Fault fault;
 186
 187     /** The memory request. */
 188     Request *req;
 189
 190     /** Pointer to the data for the memory access. */
 191     uint8_t *memData;
 192
 193     /**  Data used for a store for operation. */
 194     uint64_t loadData;
 195
 196     /**  Data used for a store for operation. */
 197     uint64_t storeData;
 198
 199     /** The resource schedule for this inst */
 200     ThePipeline::ResSchedule resSched;
 201
 202     /** List of active resource requests for this instruction */
 203     std::list<ResourceRequest*> reqList;
 204
 205     /** The effective virtual address (lds & stores only). */
 206     Addr effAddr;
 207
 208     /** The effective physical address. */
 209     Addr physEffAddr;
 210
 211     /** Effective virtual address for a copy source. */
 212     Addr copySrcEffAddr;
 213
 214     /** Effective physical address for a copy source. */
 215     Addr copySrcPhysEffAddr;
 216
 217     /** The memory request flags (from translation). */
 218     unsigned memReqFlags;
 219
 220     /** How many source registers are ready. */
 221     unsigned readyRegs;
 222
 223     /** An instruction src/dest has to be one of these types */
 224     union InstValue {
 225         uint64_t integer;
 226         float fp;
 227         double dbl;
 228     };
 229
 230     /** Result of an instruction execution */
 231     struct InstResult {
 232         InstValue val;
 233         Tick tick;
 234     };
 235
 236     /** The source of the instruction; assumes for now that there's only one
 237      *  destination register.
 238      */
 239     InstValue instSrc[MaxInstSrcRegs];
 240
 241     /** The result of the instruction; assumes for now that there's only one
 242      *  destination register.
 243      */
 244     InstResult instResult[MaxInstDestRegs];
 245
 246     /** PC of this instruction. */
 247     Addr PC;
 248
 249     /** Next non-speculative PC.  It is not filled in at fetch, but rather
 250      *  once the target of the branch is truly known (either decode or
 251      *  execute).
 252      */
 253     Addr nextPC;
 254
 255     /** Next next non-speculative PC.  It is not filled in at fetch, but rather
 256      *  once the target of the branch is truly known (either decode or
 257      *  execute).
 258      */
 259     Addr nextNPC;
 260
 261     /** Predicted next PC. */
 262     Addr predPC;
 263
 264     /** Address to fetch from */
 265     Addr fetchAddr;
 266
 267     /** Address to get/write data from/to */
 268     Addr memAddr;
 269
 270     /** Whether or not the source register is ready.
 271      *  @todo: Not sure this should be here vs the derived class.
 272      */
 273     bool _readySrcRegIdx[MaxInstSrcRegs];
 274
 275     /** Physical register index of the destination registers of this
 276      *  instruction.
 277      */
 278     PhysRegIndex _destRegIdx[MaxInstDestRegs];
 279
 280     /** Physical register index of the source registers of this
 281      *  instruction.
 282      */
 283     PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
 284
 285     /** Physical register index of the previous producers of the
 286      *  architected destinations.
 287      */
 288     PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
 289
 290     int nextStage;
 291
 292     /* vars to keep track of InstStage's - used for resource sched defn */
 293     int nextInstStageNum;
 294     ThePipeline::InstStage *currentInstStage;
 295     std::list<ThePipeline::InstStage*> instStageList;
 296
 297   private:
 298     /** Function to initialize variables in the constructors. */
 299     void initVars();
 300
 301   public:
 302     Tick memTime;
 303
 304     ////////////////////////////////////////////////////////////
 305     //
 306     //  BASE INSTRUCTION INFORMATION.
 307     //
 308     ////////////////////////////////////////////////////////////
 309     void setMachInst(ExtMachInst inst);
 310
 311     /** Sets the StaticInst. */
 312     void setStaticInst(StaticInstPtr &static_inst);
 313
 314     /** Sets the sequence number. */
 315     void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
 316
 317     /** Sets the ASID. */
 318     void setASID(short addr_space_id) { asid = addr_space_id; }
 319
 320     /** Reads the thread id. */
 321     short readTid() { return threadNumber; }
 322
 323     /** Sets the thread id. */
 324     void setTid(unsigned tid) { threadNumber = tid; }
 325
 326     void setVpn(int id) { virtProcNumber = id; }
 327
 328     int readVpn() { return virtProcNumber; }
 329
 330     /** Sets the pointer to the thread state. */
 331     void setThreadState(InOrderThreadState *state) { thread = state; }
 332
 333     /** Returns the thread context. */
 334     ThreadContext *tcBase() { return thread->getTC(); }
 335
 336     /** Returns the fault type. */
 337     Fault getFault() { return fault; }
 338
 339     ////////////////////////////////////////////////////////////
 340     //
 341     //  INSTRUCTION TYPES -  Forward checks to StaticInst object.
 342     //
 343     ////////////////////////////////////////////////////////////
 344     bool isNop()          const { return staticInst->isNop(); }
 345     bool isMemRef()       const { return staticInst->isMemRef(); }
 346     bool isLoad()         const { return staticInst->isLoad(); }
 347     bool isStore()        const { return staticInst->isStore(); }
 348     bool isStoreConditional() const
 349     { return staticInst->isStoreConditional(); }
 350     bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
 351     bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
 352     bool isCopy()         const { return staticInst->isCopy(); }
 353     bool isInteger()      const { return staticInst->isInteger(); }
 354     bool isFloating()     const { return staticInst->isFloating(); }
 355     bool isControl()      const { return staticInst->isControl(); }
 356     bool isCall()         const { return staticInst->isCall(); }
 357     bool isReturn()       const { return staticInst->isReturn(); }
 358     bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
 359     bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
 360     bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
 361     bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
 362     bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
 363
 364     bool isThreadSync()   const { return staticInst->isThreadSync(); }
 365     bool isSerializing()  const { return staticInst->isSerializing(); }
 366     bool isSerializeBefore() const
 367     { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
 368     bool isSerializeAfter() const
 369     { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
 370     bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
 371     bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
 372     bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
 373     bool isQuiesce() const { return staticInst->isQuiesce(); }
 374     bool isIprAccess() const { return staticInst->isIprAccess(); }
 375     bool isUnverifiable() const { return staticInst->isUnverifiable(); }
 376
 377     /////////////////////////////////////////////
 378     //
 379     // RESOURCE SCHEDULING
 380     //
 381     /////////////////////////////////////////////
 382
 383     void setNextStage(int stage_num) { nextStage = stage_num; }
 384     int getNextStage() { return nextStage; }
 385
 386     ThePipeline::InstStage *addStage();
 387     ThePipeline::InstStage *addStage(int stage);
 388     ThePipeline::InstStage *currentStage() { return currentInstStage; }
 389     void deleteStages();
 390
 391     /** Add A Entry To Reource Schedule */
 392     void addToSched(ThePipeline::ScheduleEntry* sched_entry)
 393     { resSched.push(sched_entry); }
 394
 395
 396     /** Print Resource Schedule */
 397     void printSched()
 398     {
 399         using namespace ThePipeline;
 400
 401         ResSchedule tempSched;
 402         std::cerr << "\tInst. Res. Schedule: ";
 403         while (!resSched.empty()) {
 404             std::cerr << '\t' << resSched.top()->stageNum << "-"
 405                  << resSched.top()->resNum << ", ";
 406
 407             tempSched.push(resSched.top());
 408             resSched.pop();
 409         }
 410
 411         std::cerr << std::endl;
 412         resSched = tempSched;
 413     }
 414
 415     /** Return Next Resource Stage To Be Used */
 416     int nextResStage()
 417     {
 418         if (resSched.empty())
 419             return -1;
 420         else
 421             return resSched.top()->stageNum;
 422     }
 423
 424
 425     /** Return Next Resource To Be Used */
 426     int nextResource()
 427     {
 428         if (resSched.empty())
 429             return -1;
 430         else
 431             return resSched.top()->resNum;
 432     }
 433
 434     /** Remove & Deallocate a schedule entry */
 435     void popSchedEntry()
 436     {
 437         if (!resSched.empty()) {
 438             ThePipeline::ScheduleEntry* sked = resSched.top();
 439             resSched.pop();
 440             delete sked;
 441         }
 442     }
 443
 444     /** Release a Resource Request (Currently Unused) */
 445     void releaseReq(ResourceRequest* req);
 446
 447     ////////////////////////////////////////////
 448     //
 449     // INSTRUCTION EXECUTION
 450     //
 451     ////////////////////////////////////////////
 452     /** Returns the opclass of this instruction. */
 453     OpClass opClass() const { return staticInst->opClass(); }
 454
 455     /** Executes the instruction.*/
 456     Fault execute();
 457
 458     unsigned curResSlot;
 459
 460     unsigned getCurResSlot() { return curResSlot; }
 461
 462     void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
 463
 464     /** Calls a syscall. */
 465     void syscall(int64_t callnum);
 466     void prefetch(Addr addr, unsigned flags);
 467     void writeHint(Addr addr, int size, unsigned flags);
 468     Fault copySrcTranslate(Addr src);
 469     Fault copy(Addr dest);
 470
 471     ////////////////////////////////////////////////////////////
 472     //
 473     // MULTITHREADING INTERFACE TO CPU MODELS
 474     //
 475     ////////////////////////////////////////////////////////////
 476     virtual void deallocateContext(int thread_num);
 477
 478     virtual void enableVirtProcElement(unsigned vpe);
 479     virtual void disableVirtProcElement(unsigned vpe);
 480
 481     virtual void enableMultiThreading(unsigned vpe);
 482     virtual void disableMultiThreading(unsigned vpe);
 483
 484     ////////////////////////////////////////////////////////////
 485     //
 486     //  PROGRAM COUNTERS - PC/NPC/NPC
 487     //
 488     ////////////////////////////////////////////////////////////
 489     /** Read the PC of this instruction. */
 490     const Addr readPC() const { return PC; }
 491
 492     /** Sets the PC of this instruction. */
 493     void setPC(Addr pc) { PC = pc; }
 494
 495     /** Returns the next PC.  This could be the speculative next PC if it is
 496      *  called prior to the actual branch target being calculated.
 497      */
 498     Addr readNextPC() { return nextPC; }
 499
 500     /** Set the next PC of this instruction (its actual target). */
 501     void setNextPC(uint64_t val) { nextPC = val; }
 502
 503     /** Returns the next NPC.  This could be the speculative next NPC if it is
 504      *  called prior to the actual branch target being calculated.
 505      */
 506     Addr readNextNPC() { return nextNPC; }
 507
 508     /** Set the next PC of this instruction (its actual target). */
 509     void setNextNPC(uint64_t val) { nextNPC = val; }
 510
 511     ////////////////////////////////////////////////////////////
 512     //
 513     // BRANCH PREDICTION
 514     //
 515     ////////////////////////////////////////////////////////////
 516     /** Set the predicted target of this current instruction. */
 517     void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
 518
 519     /** Returns the predicted target of the branch. */
 520     Addr readPredTarg() { return predPC; }
 521
 522     /** Returns whether the instruction was predicted taken or not. */
 523     bool predTaken() { return predictTaken; }
 524
 525     /** Returns whether the instruction mispredicted. */
 526     bool mispredicted()
 527     {
 528         // Special case since a not-taken, cond. delay slot, effectively
 529         // nullifies the delay slot instruction
 530         if (isCondDelaySlot() && !predictTaken) {
 531             return predPC != nextPC;
 532         } else {
 533             return predPC != nextNPC;
 534         }
 535     }
 536
 537     /** Returns whether the instruction mispredicted. */
 538     bool mistargeted() { return predPC != nextNPC; }
 539
 540     /** Returns the branch target address. */
 541     Addr branchTarget() const { return staticInst->branchTarget(PC); }
 542
 543     /** Checks whether or not this instruction has had its branch target
 544      *  calculated yet.  For now it is not utilized and is hacked to be
 545      *  always false.
 546      *  @todo: Actually use this instruction.
 547      */
 548     bool doneTargCalc() { return false; }
 549
 550     void setBranchPred(bool prediction) { predictTaken = prediction; }
 551
 552     int squashingStage;
 553
 554     bool predictTaken;
 555
 556     bool procDelaySlotOnMispred;
 557
 558     ////////////////////////////////////////////
 559     //
 560     // MEMORY ACCESS
 561     //
 562     ////////////////////////////////////////////
 563     /**
 564      * Does a read to a given address.
 565      * @param addr The address to read.
 566      * @param data The read's data is written into this parameter.
 567      * @param flags The request's flags.
 568      * @return Returns any fault due to the read.
 569      */
 570     template <class T>
 571     Fault read(Addr addr, T &data, unsigned flags);
 572
 573     /**
 574      * Does a write to a given address.
 575      * @param data The data to be written.
 576      * @param addr The address to write to.
 577      * @param flags The request's flags.
 578      * @param res The result of the write (for load locked/store conditionals).
 579      * @return Returns any fault due to the write.
 580      */
 581     template <class T>
 582     Fault write(T data, Addr addr, unsigned flags,
 583                         uint64_t *res);
 584
 585     /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory Access
 586      *  Only valid for memory operations.
 587      */
 588     Fault initiateAcc();
 589
 590     /** Completes a memory access - Only valid for memory operations. */
 591     Fault completeAcc(Packet *pkt);
 592
 593     /** Calculates Eff. Addr.  part of a memory instruction.  */
 594     Fault calcEA();
 595
 596     /** Read Effective Address from instruction & do memory access */
 597     Fault memAccess();
 598
 599     RequestPtr memReq;
 600
 601     bool memAddrReady;
 602
 603     bool validMemAddr()
 604     { return memAddrReady; }
 605
 606     void setMemAddr(Addr addr)
 607     { memAddr = addr; memAddrReady = true;}
 608
 609     void unsetMemAddr()
 610     { memAddrReady = false;}
 611
 612     Addr getMemAddr()
 613     { return memAddr; }
 614
 615     int getMemAccSize() { return staticInst->memAccSize(this); }
 616
 617     int getMemFlags() { return staticInst->memAccFlags(); }
 618
 619     /** Sets the effective address. */
 620     void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
 621
 622     /** Returns the effective address. */
 623     const Addr &getEA() const { return instEffAddr; }
 624
 625     /** Returns whether or not the eff. addr. calculation has been completed. */
 626     bool doneEACalc() { return eaCalcDone; }
 627
 628     /** Returns whether or not the eff. addr. source registers are ready.
 629      *  Assume that src registers 1..n-1 are the ones that the
 630      *  EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 631      *  stored)
 632      */
 633     bool eaSrcsReady()
 634     {
 635         for (int i = 1; i < numSrcRegs(); ++i) {
 636             if (!_readySrcRegIdx[i])
 637                 return false;
 638         }
 639
 640         return true;
 641     }
 642
 643     //////////////////////////////////////////////////
 644     //
 645     // SOURCE-DESTINATION REGISTER INDEXING
 646     //
 647     //////////////////////////////////////////////////
 648     /** Returns the number of source registers. */
 649     int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
 650
 651     /** Returns the number of destination registers. */
 652     int8_t numDestRegs() const { return staticInst->numDestRegs(); }
 653
 654     // the following are used to track physical register usage
 655     // for machines with separate int & FP reg files
 656     int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
 657     int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
 658
 659     /** Returns the logical register index of the i'th destination register. */
 660     RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
 661
 662     /** Returns the logical register index of the i'th source register. */
 663     RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
 664
 665     //////////////////////////////////////////////////
 666     //
 667     // RENAME/PHYSICAL REGISTER FILE SUPPORT
 668     //
 669     //////////////////////////////////////////////////
 670     /** Returns the physical register index of the i'th destination
 671      *  register.
 672      */
 673     PhysRegIndex renamedDestRegIdx(int idx) const
 674     {
 675         return _destRegIdx[idx];
 676     }
 677
 678     /** Returns the physical register index of the i'th source register. */
 679     PhysRegIndex renamedSrcRegIdx(int idx) const
 680     {
 681         return _srcRegIdx[idx];
 682     }
 683
 684     /** Returns the physical register index of the previous physical register
 685      *  that remapped to the same logical register index.
 686      */
 687     PhysRegIndex prevDestRegIdx(int idx) const
 688     {
 689         return _prevDestRegIdx[idx];
 690     }
 691
 692     /** Returns if a source register is ready. */
 693     bool isReadySrcRegIdx(int idx) const
 694     {
 695         return this->_readySrcRegIdx[idx];
 696     }
 697
 698     /** Records that one of the source registers is ready. */
 699     void markSrcRegReady()
 700     {
 701         if (++readyRegs == numSrcRegs()) {
 702             status.set(CanIssue);
 703         }
 704     }
 705
 706     /** Marks a specific register as ready. */
 707     void markSrcRegReady(RegIndex src_idx)
 708     {
 709         _readySrcRegIdx[src_idx] = true;
 710
 711         markSrcRegReady();
 712     }
 713
 714     /** Renames a destination register to a physical register.  Also records
 715      *  the previous physical register that the logical register mapped to.
 716      */
 717     void renameDestReg(int idx,
 718                        PhysRegIndex renamed_dest,
 719                        PhysRegIndex previous_rename)
 720     {
 721         _destRegIdx[idx] = renamed_dest;
 722         _prevDestRegIdx[idx] = previous_rename;
 723     }
 724
 725     /** Renames a source logical register to the physical register which
 726      *  has/will produce that logical register's result.
 727      *  @todo: add in whether or not the source register is ready.
 728      */
 729     void renameSrcReg(int idx, PhysRegIndex renamed_src)
 730     {
 731         _srcRegIdx[idx] = renamed_src;
 732     }
 733
 734
 735     PhysRegIndex readDestRegIdx(int idx)
 736     {
 737         return _destRegIdx[idx];
 738     }
 739
 740     void setDestRegIdx(int idx, PhysRegIndex dest_idx)
 741     {
 742         _destRegIdx[idx] = dest_idx;
 743     }
 744
 745     int getDestIdxNum(PhysRegIndex dest_idx)
 746     {
 747         for (int i=0; i < staticInst->numDestRegs(); i++) {
 748             if (_destRegIdx[i] == dest_idx)
 749                 return i;
 750         }
 751
 752         return -1;
 753     }
 754
 755     PhysRegIndex readSrcRegIdx(int idx)
 756     {
 757         return _srcRegIdx[idx];
 758     }
 759
 760     void setSrcRegIdx(int idx, PhysRegIndex src_idx)
 761     {
 762         _srcRegIdx[idx] = src_idx;
 763     }
 764
 765     int getSrcIdxNum(PhysRegIndex src_idx)
 766     {
 767         for (int i=0; i < staticInst->numSrcRegs(); i++) {
 768             if (_srcRegIdx[i] == src_idx)
 769                 return i;
 770         }
 771
 772         return -1;
 773     }
 774
 775     ////////////////////////////////////////////////////
 776     //
 777     // SOURCE-DESTINATION REGISTER VALUES
 778     //
 779     ////////////////////////////////////////////////////
 780
 781     /** Functions that sets an integer or floating point
 782      *  source register to a value. */
 783     void setIntSrc(int idx, uint64_t val);
 784     void setFloatSrc(int idx, FloatReg val, int width = 32);
 785     void setFloatRegBitsSrc(int idx, uint64_t val);
 786
 787     uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
 788     uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
 789
 790     /** These Instructions read a integer/float/misc. source register
 791      *  value in the instruction. The instruction's execute function will
 792      *  call these and it is the interface that is used by the ISA descr.
 793      *  language (which is why the name isnt readIntSrc(...)) Note: That
 794      *  the source reg. value is set using the setSrcReg() function.
 795      */
 796     IntReg readIntRegOperand(const StaticInst *si, int idx, unsigned tid=0);
 797     FloatReg readFloatRegOperand(const StaticInst *si, int idx,
 798                           int width = TheISA::SingleWidth);
 799     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
 800                                   int width = TheISA::SingleWidth);
 801     MiscReg readMiscReg(int misc_reg);
 802     MiscReg readMiscRegNoEffect(int misc_reg);
 803     MiscReg readMiscRegOperand(const StaticInst *si, int idx);
 804     MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
 805
 806     /** Returns the result value instruction. */
 807     uint64_t readIntResult(int idx) { return instResult[idx].val.integer; }
 808     float readFloatResult(int idx) { return instResult[idx].val.fp; }
 809     double readDoubleResult(int idx) { return instResult[idx].val.dbl; }
 810     Tick readResultTime(int idx) { return instResult[idx].tick; }
 811
 812     uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
 813
 814     /** This is the interface that an instruction will use to write
 815      *  it's destination register.
 816      */
 817     void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
 818     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
 819                      int width = TheISA::SingleWidth);
 820     void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val,
 821                          int width = TheISA::SingleWidth);
 822     void setMiscReg(int misc_reg, const MiscReg &val);
 823     void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 824     void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
 825     void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val);
 826
 827     virtual uint64_t readRegOtherThread(unsigned idx, int tid = -1);
 828     virtual void setRegOtherThread(unsigned idx, const uint64_t &val, int tid = -1);
 829
 830     //////////////////////////////////////////////////////////////
 831     //
 832     // INSTRUCTION STATUS FLAGS (READ/SET)
 833     //
 834     //////////////////////////////////////////////////////////////
 835     /** Sets this instruction as entered on the CPU Reg Dep Map */
 836     void setRegDepEntry() { status.set(RegDepMapEntry); }
 837
 838     /** Returns whether or not the entry is on the CPU Reg Dep Map */
 839     bool isRegDepEntry() const { return status[RegDepMapEntry]; }
 840
 841     /** Sets this instruction as completed. */
 842     void setCompleted() { status.set(Completed); }
 843
 844     /** Returns whether or not this instruction is completed. */
 845     bool isCompleted() const { return status[Completed]; }
 846
 847     /** Marks the result as ready. */
 848     void setResultReady() { status.set(ResultReady); }
 849
 850     /** Returns whether or not the result is ready. */
 851     bool isResultReady() const { return status[ResultReady]; }
 852
 853     /** Sets this instruction as ready to issue. */
 854     void setCanIssue() { status.set(CanIssue); }
 855
 856     /** Returns whether or not this instruction is ready to issue. */
 857     bool readyToIssue() const { return status[CanIssue]; }
 858
 859     /** Sets this instruction as issued from the IQ. */
 860     void setIssued() { status.set(Issued); }
 861
 862     /** Returns whether or not this instruction has issued. */
 863     bool isIssued() const { return status[Issued]; }
 864
 865     /** Sets this instruction as executed. */
 866     void setExecuted() { status.set(Executed); }
 867
 868     /** Returns whether or not this instruction has executed. */
 869     bool isExecuted() const { return status[Executed]; }
 870
 871     /** Sets this instruction as ready to commit. */
 872     void setCanCommit() { status.set(CanCommit); }
 873
 874     /** Clears this instruction as being ready to commit. */
 875     void clearCanCommit() { status.reset(CanCommit); }
 876
 877     /** Returns whether or not this instruction is ready to commit. */
 878     bool readyToCommit() const { return status[CanCommit]; }
 879
 880     void setAtCommit() { status.set(AtCommit); }
 881
 882     bool isAtCommit() { return status[AtCommit]; }
 883
 884     /** Sets this instruction as committed. */
 885     void setCommitted() { status.set(Committed); }
 886
 887     /** Returns whether or not this instruction is committed. */
 888     bool isCommitted() const { return status[Committed]; }
 889
 890     /** Sets this instruction as squashed. */
 891     void setSquashed() { status.set(Squashed); }
 892
 893     /** Returns whether or not this instruction is squashed. */
 894     bool isSquashed() const { return status[Squashed]; }
 895
 896     /** Temporarily sets this instruction as a serialize before instruction. */
 897     void setSerializeBefore() { status.set(SerializeBefore); }
 898
 899     /** Clears the serializeBefore part of this instruction. */
 900     void clearSerializeBefore() { status.reset(SerializeBefore); }
 901
 902     /** Checks if this serializeBefore is only temporarily set. */
 903     bool isTempSerializeBefore() { return status[SerializeBefore]; }
 904
 905     /** Temporarily sets this instruction as a serialize after instruction. */
 906     void setSerializeAfter() { status.set(SerializeAfter); }
 907
 908     /** Clears the serializeAfter part of this instruction.*/
 909     void clearSerializeAfter() { status.reset(SerializeAfter); }
 910
 911     /** Checks if this serializeAfter is only temporarily set. */
 912     bool isTempSerializeAfter() { return status[SerializeAfter]; }
 913
 914     /** Sets the serialization part of this instruction as handled. */
 915     void setSerializeHandled() { status.set(SerializeHandled); }
 916
 917     /** Checks if the serialization part of this instruction has been
 918      *  handled.  This does not apply to the temporary serializing
 919      *  state; it only applies to this instruction's own permanent
 920      *  serializing state.
 921      */
 922     bool isSerializeHandled() { return status[SerializeHandled]; }
 923
 924   private:
 925     /** Instruction effective address.
 926      *  @todo: Consider if this is necessary or not.
 927      */
 928     Addr instEffAddr;
 929
 930     /** Whether or not the effective address calculation is completed.
 931      *  @todo: Consider if this is necessary or not.
 932      */
 933     bool eaCalcDone;
 934
 935   public:
 936     /** Whether or not the memory operation is done. */
 937     bool memOpDone;
 938
 939   public:
 940     /** Load queue index. */
 941     int16_t lqIdx;
 942
 943     /** Store queue index. */
 944     int16_t sqIdx;
 945
 946     /** Iterator pointing to this BaseDynInst in the list of all insts. */
 947     ListIt instListIt;
 948
 949     /** Returns iterator to this instruction in the list of all insts. */
 950     ListIt &getInstListIt() { return instListIt; }
 951
 952     /** Sets iterator for this instruction in the list of all insts. */
 953     void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
 954
 955     /** Count of total number of dynamic instructions. */
 956     static int instcount;
 957
 958     /** Dumps out contents of this BaseDynInst. */
 959     void dump();
 960
 961     /** Dumps out contents of this BaseDynInst into given string. */
 962     void dump(std::string &outstring);
 963
 964
 965   //inline int curCount() { return curCount(); }
 966 };
 967
 968
 969 #endif // __CPU_BASE_DYN_INST_HH__