Merge ARM into the head. ARM will compile but may not actually work.
[gem5.git] / src / cpu / inorder / inorder_trace.cc
1 /*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2001-2005 The Regents of The University of Michigan
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 */
31
32 #include <iomanip>
33
34 #include "cpu/exetrace.hh"
35 #include "cpu/inorder/inorder_trace.hh"
36 #include "cpu/static_inst.hh"
37 #include "cpu/inorder/pipeline_traits.hh"
38 #include "cpu/thread_context.hh"
39 #include "params/InOrderTrace.hh"
40
41 using namespace std;
42 using namespace TheISA;
43
44 namespace Trace {
45
46 inline void
47 Trace::InOrderTraceRecord::dumpTicks(std::ostream &outs)
48 {
49 if (!stageTrace) {
50 ccprintf(outs, "%7d: ", when);
51 } else {
52 ccprintf(outs, "");
53 for (int i=0; i < stageCycle.size(); i++) {
54 if (i < stageCycle.size() - 1)
55 outs << dec << stageCycle[i] << "-";
56 else
57 outs << dec << stageCycle[i] << ":";
58 }
59 }
60 }
61
62 InOrderTraceRecord *
63 InOrderTrace::getInstRecord(unsigned num_stages, bool stage_tracing,
64 ThreadContext *tc)
65 {
66 if (!IsOn(ExecEnable))
67 return NULL;
68
69 if (!Trace::enabled)
70 return NULL;
71
72 return new InOrderTraceRecord(num_stages, stage_tracing, tc);
73 }
74
75 InOrderTraceRecord *
76 InOrderTrace::getInstRecord(Tick when, ThreadContext *tc,
77 const StaticInstPtr staticInst, Addr pc,
78 const StaticInstPtr macroStaticInst, MicroPC upc)
79 {
80 return new InOrderTraceRecord(ThePipeline::NumStages, true, tc);
81 }
82
83 /* namespace Trace */ }
84
85 ////////////////////////////////////////////////////////////////////////
86 //
87 // ExeTracer Simulation Object
88 //
89 Trace::InOrderTrace *
90 InOrderTraceParams::create()
91 {
92 return new Trace::InOrderTrace(this);
93 };
94