includes: sort includes again
[gem5.git] / src / cpu / inorder / inorder_trace.hh
1 /*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * Copyright (c) 2001-2005 The Regents of The University of Michigan
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 */
31
32 #ifndef __CPU_INORDER_INORDER_TRACE_HH__
33 #define __CPU_INORDER_INORDER_TRACE_HH__
34
35 #include "base/trace.hh"
36 #include "base/types.hh"
37 #include "cpu/exetrace.hh"
38 #include "cpu/static_inst.hh"
39 #include "params/InOrderTrace.hh"
40 #include "sim/insttracer.hh"
41
42 class ThreadContext;
43
44 namespace Trace {
45
46 class InOrderTraceRecord : public ExeTracerRecord
47 {
48 public:
49 InOrderTraceRecord(unsigned num_stages, bool _stage_tracing,
50 ThreadContext *_thread, bool spec = false)
51 : ExeTracerRecord(0, _thread, NULL, 0, spec)
52 {
53 stageTrace = _stage_tracing;
54 stageCycle.resize(num_stages);
55 }
56
57 // Trace stage-by-stage execution of instructions.
58 bool stageTrace;
59 std::vector<Tick> stageCycle;
60
61 void dumpTicks(std::ostream &outs);
62
63 void
64 setStageCycle(int num_stage, Tick cur_cycle)
65 {
66 if (stageTrace) {
67 stageCycle[num_stage] = cur_cycle;
68 } else {
69 when = cur_cycle;
70 }
71 }
72
73 void
74 setStaticInst(const StaticInstPtr &_staticInst)
75 {
76 staticInst = _staticInst;
77 }
78 void setPC(Addr _pc) { PC = _pc; }
79 };
80
81 class InOrderTrace : public InstTracer
82 {
83 public:
84 InOrderTrace(const InOrderTraceParams *p) : InstTracer(p)
85 {}
86
87 InOrderTraceRecord *
88 getInstRecord(unsigned num_stages, bool stage_tracing, ThreadContext *tc);
89
90 virtual InOrderTraceRecord *getInstRecord(Tick when, ThreadContext *tc,
91 const StaticInstPtr staticInst, Addr pc,
92 const StaticInstPtr macroStaticInst = NULL, MicroPC upc = 0);
93 };
94
95 /* namespace Trace */ }
96
97 #endif // __CPU_INORDER_INORDER_TRACE_HH__