src/cpu/inorder/params.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  */
  30
  31 #ifndef __CPU_INORDER_PARAMS_HH__
  32 #define __CPU_INORDER_PARAMS_HH__
  33
  34 #include "cpu/base.hh"
  35
  36 //Forward declarations
  37 class FunctionalMemory;
  38 class Process;
  39 class MemObject;
  40 class MemInterface;
  41
  42 /**
  43  * This file defines the parameters that will be used for the InOrderCPU.
  44  * This must be defined externally so that the Impl can have a params class
  45  * defined that it can pass to all of the individual stages.
  46  */
  47
  48 class InOrderParams : public BaseCPU::Params
  49 {
  50   public:
  51
  52     // Workloads
  53 #if !FULL_SYSTEM
  54     std::vector<Process *> workload;
  55     Process *process;
  56 #endif // FULL_SYSTEM
  57
  58     //
  59     // Memory System/Caches
  60     //
  61     unsigned cachePorts;
  62     std::string fetchMemPort;
  63     std::string dataMemPort;
  64
  65     //
  66     // Branch predictor (BP & BTB)
  67     //
  68     std::string predType;
  69     unsigned localPredictorSize;
  70     unsigned localCtrBits;
  71     unsigned localHistoryTableSize;
  72     unsigned localHistoryBits;
  73     unsigned globalPredictorSize;
  74     unsigned globalCtrBits;
  75     unsigned globalHistoryBits;
  76     unsigned choicePredictorSize;
  77     unsigned choiceCtrBits;
  78     unsigned BTBEntries;
  79     unsigned BTBTagSize;
  80     unsigned RASSize;
  81
  82     // Pipeline Parameters
  83     unsigned stageWidth;
  84
  85     // InOrderCPU Simulation Parameters
  86     unsigned instShiftAmt;
  87     unsigned activity;
  88     unsigned deferRegistration;
  89
  90     //
  91     // Memory Parameters
  92     //
  93     unsigned memBlockSize;
  94
  95     //
  96     // Multiply Divide Unit
  97     //
  98     // @NOTE: If >1 MDU is needed and each MDU is to use varying parametesr,
  99     // then MDU must be defined as its own SimObject so that an arbitrary # can
 100     // be defined with different parameters
 101     /** Latency & Repeat Rate for Multiply Insts */
 102     unsigned multLatency;
 103     unsigned multRepeatRate;
 104
 105     /** Latency & Repeat Rate for 8-bit Divide Insts */
 106     unsigned div8Latency;
 107     unsigned div8RepeatRate;
 108
 109     /** Latency & Repeat Rate for 16-bit Divide Insts */
 110     unsigned div16Latency;
 111     unsigned div16RepeatRate;
 112
 113     /** Latency & Repeat Rate for 24-bit Divide Insts */
 114     unsigned div24Latency;
 115     unsigned div24RepeatRate;
 116
 117     /** Latency & Repeat Rate for 32-bit Divide Insts */
 118     unsigned div32Latency;
 119     unsigned div32RepeatRate;
 120
 121
 122 };
 123
 124 #endif // __CPU_O3_CPU_INORDER_PARAMS_HH__