src/cpu/inorder/params.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  */
  30
  31 #ifndef __CPU_INORDER_PARAMS_HH__
  32 #define __CPU_INORDER_PARAMS_HH__
  33
  34 #include "cpu/base.hh"
  35
  36 //Forward declarations
  37 class FunctionalMemory;
  38 class Process;
  39 class MemObject;
  40 class MemInterface;
  41
  42 /**
  43  * This file defines the parameters that will be used for the InOrderCPU.
  44  * This must be defined externally so that the Impl can have a params class
  45  * defined that it can pass to all of the individual stages.
  46  */
  47
  48 class InOrderParams : public BaseCPU::Params
  49 {
  50   public:
  51
  52     // Workloads
  53     std::vector<Process *> workload;
  54     Process *process;
  55
  56     //
  57     // Memory System/Caches
  58     //
  59     unsigned cachePorts;
  60     std::string fetchMemPort;
  61     std::string dataMemPort;
  62
  63     //
  64     // Branch predictor (BP & BTB)
  65     //
  66     std::string predType;
  67     unsigned localPredictorSize;
  68     unsigned localCtrBits;
  69     unsigned localHistoryTableSize;
  70     unsigned localHistoryBits;
  71     unsigned globalPredictorSize;
  72     unsigned globalCtrBits;
  73     unsigned globalHistoryBits;
  74     unsigned choicePredictorSize;
  75     unsigned choiceCtrBits;
  76     unsigned BTBEntries;
  77     unsigned BTBTagSize;
  78     unsigned RASSize;
  79
  80     // Pipeline Parameters
  81     unsigned stageWidth;
  82
  83     // InOrderCPU Simulation Parameters
  84     unsigned instShiftAmt;
  85     unsigned activity;
  86     unsigned deferRegistration;
  87
  88     //
  89     // Memory Parameters
  90     //
  91     unsigned memBlockSize;
  92
  93     //
  94     // Multiply Divide Unit
  95     //
  96     // @NOTE: If >1 MDU is needed and each MDU is to use varying parametesr,
  97     // then MDU must be defined as its own SimObject so that an arbitrary # can
  98     // be defined with different parameters
  99     /** Latency & Repeat Rate for Multiply Insts */
 100     unsigned multLatency;
 101     unsigned multRepeatRate;
 102
 103     /** Latency & Repeat Rate for 8-bit Divide Insts */
 104     unsigned div8Latency;
 105     unsigned div8RepeatRate;
 106
 107     /** Latency & Repeat Rate for 16-bit Divide Insts */
 108     unsigned div16Latency;
 109     unsigned div16RepeatRate;
 110
 111     /** Latency & Repeat Rate for 24-bit Divide Insts */
 112     unsigned div24Latency;
 113     unsigned div24RepeatRate;
 114
 115     /** Latency & Repeat Rate for 32-bit Divide Insts */
 116     unsigned div32Latency;
 117     unsigned div32RepeatRate;
 118
 119
 120 };
 121
 122 #endif // _CPU_INORDER_PARAMS_HH__