2 * Copyright (c) 2007 MIPS Technologies, Inc.
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6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_PIPELINE_STAGE_HH__
33 #define __CPU_INORDER_PIPELINE_STAGE_HH__
38 #include "base/statistics.hh"
39 #include "base/timebuf.hh"
40 #include "cpu/inorder/inorder_dyn_inst.hh"
41 #include "cpu/inorder/comm.hh"
42 #include "params/InOrderCPU.hh"
43 #include "cpu/inorder/pipeline_traits.hh"
50 typedef ThePipeline::Params Params;
51 typedef ThePipeline::DynInstPtr DynInstPtr;
54 /** Overall stage status. Used to determine if the CPU can
55 * deschedule itself due to a lack of activity.
62 /** Individual thread status. */
76 /** The Number of This Pipeline Stage */
79 /** The width of stage, in instructions. */
82 /** Number of Threads*/
88 /** Per-thread status. */
89 ThreadStatus stageStatus[ThePipeline::MaxThreads];
92 PipelineStage(Params *params, unsigned stage_num);
94 /** MUST use init() function if this constructor is used. */
97 virtual ~PipelineStage() { }
99 /** PipelineStage initialization. */
100 void init(Params *params);
102 /** Returns the name of stage. */
103 std::string name() const;
105 /** Registers statistics. */
108 /** Sets CPU pointer. */
109 virtual void setCPU(InOrderCPU *cpu_ptr);
111 virtual void scheduleStageStart(int delay, int tid) { }
113 /** Sets the main backwards communication time buffer pointer. */
114 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
116 /** Sets pointer to time buffer coming from fetch. */
117 void setPrevStageQueue(TimeBuffer<InterStageStruct> *prev_stage_ptr);
119 /** Sets pointer to time buffer used to communicate to the next stage. */
120 void setNextStageQueue(TimeBuffer<InterStageStruct> *next_stage_ptr);
122 /** Sets pointer to list of active threads. */
123 void setActiveThreads(std::list<unsigned> *at_ptr);
125 bool nextStageQueueValid(int stage_num);
127 bool isBlocked(unsigned tid);
129 /** Changes the status of this stage to active, and indicates this
132 //inline void switchToActive();
134 /** Changes the status of this stage to inactive, and indicates
137 //inline void switchToInactive();
139 /** Switches out the stage stage. */
142 /** Takes over from another CPU's thread. */
145 /** Ticks stage, processing all input signals and executing as many
146 * instructions as possible.
150 /** Set a resource stall in the pipeline-stage */
151 void setResStall(ResReqPtr res_req, unsigned tid);
153 /** Unset a resource stall in the pipeline-stage */
154 void unsetResStall(ResReqPtr res_req, unsigned tid);
156 /** Remove all stall signals for a particular thread; */
157 virtual void removeStalls(unsigned tid);
159 /** Is there room in the stage buffer? */
160 int stageBufferAvail();
163 /** Evaluate Stage Conditions and then process stage */
164 virtual void processStage(bool &status_change);
166 /** Determines what to do based on stage's current status.
167 * @param status_change stage() sets this variable if there was a status
168 * change (ie switching from from blocking to unblocking).
169 * @param tid Thread id to stage instructions from.
171 virtual void processThread(bool &status_change, unsigned tid);
173 /** Processes instructions from fetch and passes them on to rename.
174 * Decoding of instructions actually happens when they are created in
175 * fetch, so this function mostly checks if PC-relative branches are
178 virtual void processInsts(unsigned tid);
180 /** Process all resources on an instruction's resource schedule */
181 virtual bool processInstSchedule(DynInstPtr inst);
183 /** Is there room in the next stage buffer for this instruction? */
184 virtual bool canSendInstToStage(unsigned stage_num);
186 /** Send an instruction to the next stage buffer */
187 virtual bool sendInstToNextStage(DynInstPtr inst);
189 /** Inserts a thread's instructions into the skid buffer, to be staged
190 * once stage unblocks.
192 virtual void skidInsert(unsigned tid);
194 /** Total size of all skid buffers */
197 /** Returns if all of the skid buffers are empty. */
200 /** Updates overall stage status based on all of the threads' statuses. */
201 virtual void updateStatus();
203 /** Separates instructions from fetch into individual lists of instructions
208 /** Reads all stall signals from the backwards communication timebuffer. */
209 virtual void readStallSignals(unsigned tid);
211 /** Checks all input signals and updates stage's status appropriately. */
212 virtual bool checkSignalsAndUpdate(unsigned tid);
214 /** Checks all stall signals, and returns if any are true. */
215 virtual bool checkStall(unsigned tid) const;
217 /** Returns if there any instructions from the previous stage
220 inline bool prevStageInstsValid();
222 /** Switches stage to blocking, and signals back that stage has
224 * @return Returns true if there is a status change.
226 virtual bool block(unsigned tid);
228 void blockDueToBuffer(unsigned tid);
230 /** Switches stage to unblocking if the skid buffer is empty, and
231 * signals back that stage has unblocked.
232 * @return Returns true if there is a status change.
234 virtual bool unblock(unsigned tid);
238 /** Squashes if there is a PC-relative branch that was predicted
239 * incorrectly. Sends squash information back to fetch.
241 virtual void squashDueToBranch(DynInstPtr &inst, unsigned tid);
243 /** Squash instructions from stage buffer */
244 virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, unsigned tid);
246 /** Squashes due to commit signalling a squash. Changes status to
247 * squashing and clears block/unblock signals as needed.
249 virtual void squash(InstSeqNum squash_num, unsigned tid);
254 /** CPU interface. */
257 Trace::InOrderTrace *tracer;
259 /** List of active thread ids */
260 std::list<unsigned> *activeThreads;
262 /** Queue of all instructions coming from previous stage on this cycle. */
263 std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
265 /** Queue of instructions that are finished processing and ready to go next stage.
266 * This is used to prevent from processing an instrution more than once on any
267 * stage. NOTE: It is up to the PROGRAMMER must manage this as a queue
269 std::list<DynInstPtr> instsToNextStage;
271 /** Skid buffer between previous stage and this one. */
272 std::queue<DynInstPtr> skidBuffer[ThePipeline::MaxThreads];
274 /** Instruction used to signify that there is no *real* instruction in buffer slot */
275 DynInstPtr dummyBufferInst;
277 /** SeqNum of Squashing Branch Delay Instruction (used for MIPS) */
278 Addr bdelayDoneSeqNum[ThePipeline::MaxThreads];
280 /** Instruction used for squashing branch (used for MIPS) */
281 DynInstPtr squashInst[ThePipeline::MaxThreads];
283 /** Tells when their is a pending delay slot inst. to send
284 * to rename. If there is, then wait squash after the next
285 * instruction (used for MIPS).
287 bool squashAfterDelaySlot[ThePipeline::MaxThreads];
289 /** Maximum size of the inter-stage buffer connecting the previous stage to
290 * this stage (which we call a skid buffer) */
291 unsigned stageBufferMax;
293 /** Variable that tracks if stage has written to the time buffer this
294 * cycle. Used to tell CPU if there is activity this cycle.
296 bool wroteToTimeBuffer;
298 /** Index of instructions being sent to the next stage. */
299 unsigned toNextStageIndex;
301 /** The last stage that this particular stage should look for stalls */
302 int lastStallingStage[ThePipeline::MaxThreads];
304 /** Time buffer interface. */
305 TimeBuffer<TimeStruct> *timeBuffer;
308 /** Wire to get rename's output from backwards time buffer. */
309 TimeBuffer<TimeStruct>::wire fromNextStages;
311 /** Wire to get iew's information from backwards time buffer. */
312 TimeBuffer<TimeStruct>::wire toPrevStages;
314 /** Instruction queue linking previous stage */
315 TimeBuffer<InterStageStruct> *prevStageQueue;
317 /** Wire to get the previous stage's. */
318 TimeBuffer<InterStageStruct>::wire prevStage;
320 /** Instruction queue linking next stage */
321 TimeBuffer<InterStageStruct> *nextStageQueue;
323 /** Wire to write to the next stage */
324 TimeBuffer<InterStageStruct>::wire nextStage;
326 /** Is Previous Stage Valid? */
329 /** Is Next Stage Valid? */
332 /** Source of possible stalls. */
334 bool stage[ThePipeline::NumStages];
335 std::vector<ResReqPtr> resources;
338 /** Tracks which stages are telling decode to stall. */
339 Stalls stalls[ThePipeline::MaxThreads];
341 //@TODO: Use Stats for the pipeline stages
342 /** Stat for total number of idle cycles. */
343 //Stats::Scalar stageIdleCycles;
344 /** Stat for total number of blocked cycles. */
345 //Stats::Scalar stageBlockedCycles;
346 /** Stat for total number of normal running cycles. */
347 //Stats::Scalar stageRunCycles;
348 /** Stat for total number of unblocking cycles. */
349 //Stats::Scalar stageUnblockCycles;
350 /** Stat for total number of squashing cycles. */
351 //Stats::Scalar stageSquashCycles;
352 /** Stat for total number of staged instructions. */
353 //Stats::Scalar stageProcessedInsts;
354 /** Stat for total number of squashed instructions. */
355 //Stats::Scalar stageSquashedInsts;