src/cpu/inorder/pipeline_stage.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_PIPELINE_STAGE_HH__
  33 #define __CPU_INORDER_PIPELINE_STAGE_HH__
  34
  35 #include <queue>
  36 #include <vector>
  37
  38 #include "base/statistics.hh"
  39 #include "base/timebuf.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/comm.hh"
  42 #include "params/InOrderCPU.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44
  45 class InOrderCPU;
  46
  47 class PipelineStage
  48 {
  49   protected:
  50     typedef ThePipeline::Params Params;
  51     typedef ThePipeline::DynInstPtr DynInstPtr;
  52
  53   public:
  54     /** Overall stage status. Used to determine if the CPU can
  55      * deschedule itself due to a lack of activity.
  56      */
  57     enum StageStatus {
  58         Active,
  59         Inactive
  60     };
  61
  62     /** Individual thread status. */
  63     enum ThreadStatus {
  64         Running,
  65         Idle,
  66         StartSquash,
  67         Squashing,
  68         Blocked,
  69         Unblocking,
  70         MemWaitResponse,
  71         MemWaitRetry,
  72         MemAccessComplete
  73     };
  74
  75   protected:
  76     /** The Number of This Pipeline Stage */
  77     unsigned stageNum;
  78
  79     /** The width of stage, in instructions. */
  80     unsigned stageWidth;
  81
  82     /** Number of Threads*/
  83     ThreadID numThreads;
  84
  85     /** Stage status. */
  86     StageStatus _status;
  87
  88     /** Per-thread status. */
  89     ThreadStatus stageStatus[ThePipeline::MaxThreads];
  90
  91   public:
  92     PipelineStage(Params *params, unsigned stage_num);
  93
  94     /** MUST use init() function if this constructor is used. */
  95     PipelineStage() { }
  96
  97     virtual ~PipelineStage() { }
  98
  99     /** PipelineStage initialization. */
 100     void init(Params *params);
 101
 102     /** Returns the name of stage. */
 103     std::string name() const;
 104
 105     /** Registers statistics. */
 106     void regStats();
 107
 108     /** Sets CPU pointer. */
 109     virtual void setCPU(InOrderCPU *cpu_ptr);
 110
 111     virtual void scheduleStageStart(int delay, ThreadID tid) { }
 112
 113     /** Sets the main backwards communication time buffer pointer. */
 114     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 115
 116     /** Sets pointer to time buffer coming from fetch. */
 117     void setPrevStageQueue(TimeBuffer<InterStageStruct> *prev_stage_ptr);
 118
 119     /** Sets pointer to time buffer used to communicate to the next stage. */
 120     void setNextStageQueue(TimeBuffer<InterStageStruct> *next_stage_ptr);
 121
 122     /** Sets pointer to list of active threads. */
 123     void setActiveThreads(std::list<ThreadID> *at_ptr);
 124
 125     bool nextStageQueueValid(int stage_num);
 126
 127     bool isBlocked(ThreadID tid);
 128
 129     /** Changes the status of this stage to active, and indicates this
 130      * to the CPU.
 131      */
 132     //inline void switchToActive();
 133
 134     /** Changes the status of this stage to inactive, and indicates
 135      * this to the CPU.
 136      */
 137     //inline void switchToInactive();
 138
 139     /** Switches out the stage stage. */
 140     void switchOut();
 141
 142     /** Takes over from another CPU's thread. */
 143     void takeOverFrom();
 144
 145     /** Ticks stage, processing all input signals and executing as many
 146      *  instructions as possible.
 147      */
 148     virtual void tick();
 149
 150     /** Set a resource stall in the pipeline-stage */
 151     void setResStall(ResReqPtr res_req, ThreadID tid);
 152
 153     /** Unset a resource stall in the pipeline-stage */
 154     void unsetResStall(ResReqPtr res_req, ThreadID tid);
 155
 156     /** Remove all stall signals for a particular thread; */
 157     virtual void removeStalls(ThreadID tid);
 158
 159     /** Is there room in the stage buffer? */
 160     int stageBufferAvail();
 161
 162   protected:
 163     /** Evaluate Stage Conditions and then process stage */
 164     virtual void processStage(bool &status_change);
 165
 166     /** Determines what to do based on stage's current status.
 167      * @param status_change stage() sets this variable if there was a status
 168      * change (ie switching from from blocking to unblocking).
 169      * @param tid Thread id to stage instructions from.
 170      */
 171     virtual void processThread(bool &status_change, ThreadID tid);
 172
 173     /** Processes instructions from fetch and passes them on to rename.
 174      * Decoding of instructions actually happens when they are created in
 175      * fetch, so this function mostly checks if PC-relative branches are
 176      * correct.
 177      */
 178     virtual void processInsts(ThreadID tid);
 179
 180     /** Process all resources on an instruction's resource schedule */
 181     virtual bool processInstSchedule(DynInstPtr inst);
 182
 183     /** Is there room in the next stage buffer for this instruction? */
 184     virtual bool canSendInstToStage(unsigned stage_num);
 185
 186     /** Send an instruction to the next stage buffer */
 187     virtual bool sendInstToNextStage(DynInstPtr inst);
 188
 189     /** Inserts a thread's instructions into the skid buffer, to be staged
 190      * once stage unblocks.
 191      */
 192     virtual void skidInsert(ThreadID tid);
 193
 194     /** Total size of all skid buffers */
 195     int skidSize();
 196
 197     /** Returns if all of the skid buffers are empty. */
 198     bool skidsEmpty();
 199
 200     /** Updates overall stage status based on all of the threads' statuses. */
 201     virtual void updateStatus();
 202
 203     /** Separates instructions from fetch into individual lists of instructions
 204      * sorted by thread.
 205      */
 206     void sortInsts();
 207
 208     /** Reads all stall signals from the backwards communication timebuffer. */
 209     virtual void readStallSignals(ThreadID tid);
 210
 211     /** Checks all input signals and updates stage's status appropriately. */
 212     virtual bool checkSignalsAndUpdate(ThreadID tid);
 213
 214     /** Checks all stall signals, and returns if any are true. */
 215     virtual bool checkStall(ThreadID tid) const;
 216
 217     /** Returns if there any instructions from the previous stage
 218      * on this cycle.
 219      */
 220     inline bool prevStageInstsValid();
 221
 222     /** Switches stage to blocking, and signals back that stage has
 223      * become blocked.
 224      * @return Returns true if there is a status change.
 225      */
 226     virtual bool block(ThreadID tid);
 227
 228     void blockDueToBuffer(ThreadID tid);
 229
 230     /** Switches stage to unblocking if the skid buffer is empty, and
 231      * signals back that stage has unblocked.
 232      * @return Returns true if there is a status change.
 233      */
 234     virtual bool unblock(ThreadID tid);
 235
 236
 237   public:
 238     /** Squashes if there is a PC-relative branch that was predicted
 239      * incorrectly. Sends squash information back to fetch.
 240      */
 241     virtual void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
 242
 243     /** Squash instructions from stage buffer  */
 244     virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid);
 245
 246     /** Squashes due to commit signalling a squash. Changes status to
 247      *  squashing and clears block/unblock signals as needed.
 248      */
 249     virtual void squash(InstSeqNum squash_num, ThreadID tid);
 250
 251     void dumpInsts();
 252
 253   protected:
 254     /** CPU interface. */
 255     InOrderCPU *cpu;
 256
 257     Trace::InOrderTrace *tracer;
 258
 259     /** List of active thread ids */
 260     std::list<ThreadID> *activeThreads;
 261
 262     /** Queue of all instructions coming from previous stage on this cycle. */
 263     std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
 264
 265     /** Queue of instructions that are finished processing and ready to go next stage.
 266      *  This is used to prevent from processing an instrution more than once on any
 267      *  stage. NOTE: It is up to the PROGRAMMER must manage this as a queue
 268      */
 269     std::list<DynInstPtr> instsToNextStage;
 270
 271     /** Skid buffer between previous stage and this one. */
 272     std::queue<DynInstPtr> skidBuffer[ThePipeline::MaxThreads];
 273
 274     /** Instruction used to signify that there is no *real* instruction in buffer slot */
 275     DynInstPtr dummyBufferInst;
 276
 277     /** SeqNum of Squashing Branch Delay Instruction (used for MIPS) */
 278     Addr bdelayDoneSeqNum[ThePipeline::MaxThreads];
 279
 280     /** Instruction used for squashing branch (used for MIPS) */
 281     DynInstPtr squashInst[ThePipeline::MaxThreads];
 282
 283     /** Tells when their is a pending delay slot inst. to send
 284      *  to rename. If there is, then wait squash after the next
 285      *  instruction (used for MIPS).
 286      */
 287     bool squashAfterDelaySlot[ThePipeline::MaxThreads];
 288
 289     /** Maximum size of the inter-stage buffer connecting the previous stage to
 290      *  this stage (which we call a skid buffer) */
 291     unsigned stageBufferMax;
 292
 293     /** Variable that tracks if stage has written to the time buffer this
 294      * cycle. Used to tell CPU if there is activity this cycle.
 295      */
 296     bool wroteToTimeBuffer;
 297
 298     /** Index of instructions being sent to the next stage. */
 299     unsigned toNextStageIndex;
 300
 301     /** The last stage that this particular stage should look for stalls */
 302     int lastStallingStage[ThePipeline::MaxThreads];
 303
 304     /** Time buffer interface. */
 305     TimeBuffer<TimeStruct> *timeBuffer;
 306
 307   public:
 308     /** Wire to get rename's output from backwards time buffer. */
 309     TimeBuffer<TimeStruct>::wire fromNextStages;
 310
 311     /** Wire to get iew's information from backwards time buffer. */
 312     TimeBuffer<TimeStruct>::wire toPrevStages;
 313
 314     /** Instruction queue linking previous stage */
 315     TimeBuffer<InterStageStruct> *prevStageQueue;
 316
 317     /** Wire to get the previous stage's. */
 318     TimeBuffer<InterStageStruct>::wire prevStage;
 319
 320     /** Instruction queue linking next stage */
 321     TimeBuffer<InterStageStruct> *nextStageQueue;
 322
 323     /** Wire to write to the next stage */
 324     TimeBuffer<InterStageStruct>::wire nextStage;
 325
 326     /** Is Previous Stage Valid? */
 327     bool prevStageValid;
 328
 329     /** Is Next Stage Valid? */
 330     bool nextStageValid;
 331
 332     /** Source of possible stalls. */
 333     struct Stalls {
 334         bool stage[ThePipeline::NumStages];
 335         std::vector<ResReqPtr> resources;
 336     };
 337
 338     /** Tracks which stages are telling decode to stall. */
 339     Stalls stalls[ThePipeline::MaxThreads];
 340
 341     //@TODO: Use Stats for the pipeline stages
 342     /** Stat for total number of idle cycles. */
 343     //Stats::Scalar stageIdleCycles;
 344     /** Stat for total number of blocked cycles. */
 345     //Stats::Scalar stageBlockedCycles;
 346     /** Stat for total number of normal running cycles. */
 347     //Stats::Scalar stageRunCycles;
 348     /** Stat for total number of unblocking cycles. */
 349     //Stats::Scalar stageUnblockCycles;
 350     /** Stat for total number of squashing cycles. */
 351     //Stats::Scalar stageSquashCycles;
 352     /** Stat for total number of staged instructions. */
 353     //Stats::Scalar stageProcessedInsts;
 354     /** Stat for total number of squashed instructions. */
 355     //Stats::Scalar stageSquashedInsts;
 356 };
 357
 358 #endif