src/cpu/inorder/pipeline_stage.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_PIPELINE_STAGE_HH__
  33 #define __CPU_INORDER_PIPELINE_STAGE_HH__
  34
  35 #include <queue>
  36 #include <vector>
  37
  38 #include "base/statistics.hh"
  39 #include "cpu/timebuf.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/comm.hh"
  42 #include "params/InOrderCPU.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44
  45 class InOrderCPU;
  46
  47 class PipelineStage
  48 {
  49   protected:
  50     typedef ThePipeline::Params Params;
  51     typedef ThePipeline::DynInstPtr DynInstPtr;
  52
  53   public:
  54     /** Overall stage status. Used to determine if the CPU can
  55      * deschedule itself due to a lack of activity.
  56      */
  57     enum StageStatus {
  58         Active,
  59         Inactive
  60     };
  61
  62     /** Individual thread status. */
  63     enum ThreadStatus {
  64         Running,
  65         Idle,
  66         StartSquash,
  67         Squashing,
  68         Blocked,
  69         Unblocking,
  70         MemWaitResponse,
  71         MemWaitRetry,
  72         MemAccessComplete
  73     };
  74
  75   protected:
  76     /** The Number of This Pipeline Stage */
  77     unsigned stageNum;
  78
  79     /** The width of stage, in instructions. */
  80     unsigned stageWidth;
  81
  82     /** Number of Threads*/
  83     ThreadID numThreads;
  84
  85     /** Stage status. */
  86     StageStatus _status;
  87
  88     /** Per-thread status. */
  89     ThreadStatus stageStatus[ThePipeline::MaxThreads];
  90
  91   public:
  92     PipelineStage(Params *params, unsigned stage_num);
  93
  94     /** MUST use init() function if this constructor is used. */
  95     PipelineStage() { }
  96
  97     virtual ~PipelineStage() { }
  98
  99     /** PipelineStage initialization. */
 100     void init(Params *params);
 101
 102     /** Returns the name of stage. */
 103     std::string name() const;
 104
 105     /** Registers statistics. */
 106     void regStats();
 107
 108     /** Sets CPU pointer. */
 109     void setCPU(InOrderCPU *cpu_ptr);
 110
 111     /** Sets the main backwards communication time buffer pointer. */
 112     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 113
 114     /** Sets pointer to time buffer coming from fetch. */
 115     void setPrevStageQueue(TimeBuffer<InterStageStruct> *prev_stage_ptr);
 116
 117     /** Sets pointer to time buffer used to communicate to the next stage. */
 118     void setNextStageQueue(TimeBuffer<InterStageStruct> *next_stage_ptr);
 119
 120     /** Sets pointer to list of active threads. */
 121     void setActiveThreads(std::list<ThreadID> *at_ptr);
 122
 123     bool nextStageQueueValid(int stage_num);
 124
 125     bool isBlocked(ThreadID tid);
 126
 127     /** Changes the status of this stage to active, and indicates this
 128      * to the CPU.
 129      */
 130     //inline void switchToActive();
 131
 132     /** Changes the status of this stage to inactive, and indicates
 133      * this to the CPU.
 134      */
 135     //inline void switchToInactive();
 136
 137     /** Switches out the stage stage. */
 138     void switchOut();
 139
 140     /** Takes over from another CPU's thread. */
 141     void takeOverFrom();
 142
 143     /** Ticks stage, processing all input signals and executing as many
 144      *  instructions as possible.
 145      */
 146     void tick();
 147
 148     /** Set a resource stall in the pipeline-stage */
 149     void setResStall(ResReqPtr res_req, ThreadID tid);
 150
 151     /** Unset a resource stall in the pipeline-stage */
 152     void unsetResStall(ResReqPtr res_req, ThreadID tid);
 153
 154     /** Remove all stall signals for a particular thread; */
 155     void removeStalls(ThreadID tid);
 156
 157     /** Is there room in the stage buffer? */
 158     int stageBufferAvail();
 159
 160   protected:
 161     /** Evaluate Stage Conditions and then process stage */
 162     virtual void processStage(bool &status_change);
 163
 164     /** Determines what to do based on stage's current status.
 165      * @param status_change stage() sets this variable if there was a status
 166      * change (ie switching from from blocking to unblocking).
 167      * @param tid Thread id to stage instructions from.
 168      */
 169     void processThread(bool &status_change, ThreadID tid);
 170
 171     /** Processes instructions from fetch and passes them on to rename.
 172      * Decoding of instructions actually happens when they are created in
 173      * fetch, so this function mostly checks if PC-relative branches are
 174      * correct.
 175      */
 176     virtual void processInsts(ThreadID tid);
 177
 178     /** Process all resources on an instruction's resource schedule */
 179     bool processInstSchedule(DynInstPtr inst, int &reqs_processed);
 180
 181     /** Is there room in the next stage buffer for this instruction? */
 182     bool canSendInstToStage(unsigned stage_num);
 183
 184     /** Send an instruction to the next stage buffer */
 185     bool sendInstToNextStage(DynInstPtr inst);
 186
 187     /** Total size of all skid buffers */
 188     int skidSize();
 189
 190     /** Returns if all of the skid buffers are empty. */
 191     bool skidsEmpty();
 192
 193     /** Updates overall stage status based on all of the threads' statuses. */
 194     void updateStatus();
 195
 196     /** Separates instructions from fetch into individual lists of instructions
 197      * sorted by thread.
 198      */
 199     void sortInsts();
 200
 201     /** Reads all stall signals from the backwards communication timebuffer. */
 202     void readStallSignals(ThreadID tid);
 203
 204     /** Checks all input signals and updates stage's status appropriately. */
 205     bool checkSignalsAndUpdate(ThreadID tid);
 206
 207     /** Checks all stall signals, and returns if any are true. */
 208     bool checkStall(ThreadID tid) const;
 209
 210     /** Returns if there any instructions from the previous stage
 211      * on this cycle.
 212      */
 213     inline bool prevStageInstsValid();
 214
 215     /** Switches stage to blocking, and signals back that stage has
 216      * become blocked.
 217      * @return Returns true if there is a status change.
 218      */
 219     bool block(ThreadID tid);
 220
 221     void blockDueToBuffer(ThreadID tid);
 222
 223     /** Switches stage to unblocking if the skid buffer is empty, and
 224      * signals back that stage has unblocked.
 225      * @return Returns true if there is a status change.
 226      */
 227     bool unblock(ThreadID tid);
 228
 229
 230   public:
 231     void activateThread(ThreadID tid);
 232
 233     /** Squashes if there is a PC-relative branch that was predicted
 234      * incorrectly. Sends squash information back to fetch.
 235      */
 236     void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
 237
 238     virtual void squashDueToMemStall(InstSeqNum seq_num, ThreadID tid);
 239
 240     /** Squash instructions from stage buffer  */
 241     void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid);
 242
 243     /** Squashes due to commit signalling a squash. Changes status to
 244      *  squashing and clears block/unblock signals as needed.
 245      */
 246     virtual void squash(InstSeqNum squash_num, ThreadID tid);
 247
 248     void dumpInsts();
 249
 250   protected:
 251     /** CPU interface. */
 252     InOrderCPU *cpu;
 253
 254     Trace::InOrderTrace *tracer;
 255
 256     /** List of active thread ids */
 257     std::list<ThreadID> *activeThreads;
 258
 259     /** Buffer of instructions switched out to mem-stall.
 260      *  Only used when using SwitchOnCacheMiss threading model
 261      *  Used as 1-to-1 mapping between ThreadID and Entry.
 262      */
 263     std::vector<DynInstPtr> switchedOutBuffer;
 264     std::vector<bool> switchedOutValid;
 265
 266     /** Instructions that we've processed this tick
 267      *  NOTE: "Processed" means completed at least 1 instruction request
 268      */
 269     unsigned instsProcessed;
 270
 271     /** Queue of all instructions coming from previous stage on this cycle. */
 272     std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
 273
 274     /** Queue of instructions that are finished processing and ready to go
 275      *  next stage. This is used to prevent from processing an instrution more
 276      *  than once on any stage. NOTE: It is up to the PROGRAMMER must manage
 277      *  this as a queue
 278      */
 279     std::list<DynInstPtr> instsToNextStage;
 280
 281     /** Skid buffer between previous stage and this one. */
 282     std::list<DynInstPtr> skidBuffer[ThePipeline::MaxThreads];
 283
 284     /** Instruction used to signify that there is no *real* instruction in
 285      *  buffer slot */
 286     DynInstPtr dummyBufferInst;
 287
 288     /** SeqNum of Squashing Branch Delay Instruction (used for MIPS) */
 289     Addr bdelayDoneSeqNum[ThePipeline::MaxThreads];
 290
 291     /** Tells when their is a pending delay slot inst. to send
 292      *  to rename. If there is, then wait squash after the next
 293      *  instruction (used for MIPS).
 294      */
 295     bool squashAfterDelaySlot[ThePipeline::MaxThreads];
 296
 297     /** Instruction used for squashing branch (used for MIPS) */
 298     DynInstPtr squashInst[ThePipeline::MaxThreads];
 299
 300     /** Maximum size of the inter-stage buffer connecting the previous stage to
 301      *  this stage (which we call a skid buffer) */
 302     unsigned stageBufferMax;
 303
 304     /** Variable that tracks if stage has written to the time buffer this
 305      * cycle. Used to tell CPU if there is activity this cycle.
 306      */
 307     bool wroteToTimeBuffer;
 308
 309     /** Index of instructions being sent to the next stage. */
 310     unsigned toNextStageIndex;
 311
 312     /** The last stage that this particular stage should look for stalls */
 313     int lastStallingStage[ThePipeline::MaxThreads];
 314
 315     /** Time buffer interface. */
 316     TimeBuffer<TimeStruct> *timeBuffer;
 317
 318   public:
 319     /** Wire to get rename's output from backwards time buffer. */
 320     TimeBuffer<TimeStruct>::wire fromNextStages;
 321
 322     /** Wire to get iew's information from backwards time buffer. */
 323     TimeBuffer<TimeStruct>::wire toPrevStages;
 324
 325     /** Instruction queue linking previous stage */
 326     TimeBuffer<InterStageStruct> *prevStageQueue;
 327
 328     /** Wire to get the previous stage's. */
 329     TimeBuffer<InterStageStruct>::wire prevStage;
 330
 331     /** Instruction queue linking next stage */
 332     TimeBuffer<InterStageStruct> *nextStageQueue;
 333
 334     /** Wire to write to the next stage */
 335     TimeBuffer<InterStageStruct>::wire nextStage;
 336
 337     /** Is Previous Stage Valid? */
 338     bool prevStageValid;
 339
 340     /** Is Next Stage Valid? */
 341     bool nextStageValid;
 342
 343     bool idle;
 344
 345     /** Source of possible stalls. */
 346     struct Stalls {
 347         bool stage[ThePipeline::NumStages];
 348         std::vector<ResReqPtr> resources;
 349     };
 350
 351     /** Tracks stage/resource stalls */
 352     Stalls stalls[ThePipeline::MaxThreads];
 353
 354     /** Number of cycles 0 instruction(s) are processed. */
 355     Stats::Scalar idleCycles;
 356
 357     /** Number of cycles 1+ instructions are processed. */
 358     Stats::Scalar runCycles;
 359
 360     /** Percentage of cycles 1+ instructions are processed. */
 361     Stats::Formula utilization;
 362
 363
 364 };
 365
 366 #endif