2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #include "cpu/inorder/resources/resource_list.hh"
33 #include "cpu/inorder/inorder_dyn_inst.hh"
34 #include "cpu/inorder/pipeline_traits.hh"
38 namespace ThePipeline
{
40 //@TODO: create my own Instruction Schedule Class
41 //that operates as a Priority QUEUE
42 int getNextPriority(DynInstPtr
&inst
, int stage_num
)
47 std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
48 entryCompare>::iterator sked_it = inst->resSched.begin();
50 std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
51 entryCompare>::iterator sked_end = inst->resSched.end();
53 while (sked_it != sked_end) {
55 if (sked_it.top()->stageNum == stage_num) {
56 cur_pri = sked_it.top()->priority;
66 void createFrontEndSchedule(DynInstPtr
&inst
)
70 // Get Pointer to Instuction's Schedule
71 ResSchedule
*inst_sched
= &inst
->resSched
;
75 // ---------------------------------------
76 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, FetchSeq
, FetchSeqUnit::AssignNextPC
));
77 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, ITLB
, TLBUnit::FetchLookup
));
78 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, ICache
, CacheUnit::InitiateFetch
));
82 // ---------------------------------------
84 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, ICache
, CacheUnit::CompleteFetch
));
85 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, Decode
, DecodeUnit::DecodeInst
));
86 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, BPred
, BranchPredictor::PredictBranch
));
87 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, FetchSeq
, FetchSeqUnit::UpdateTargetPC
));
91 bool createBackEndSchedule(DynInstPtr
&inst
)
93 if (!inst
->staticInst
) {
97 int stNum
= BackEndStartStage
;
100 // Get Pointer to Instuction's Schedule
101 ResSchedule
*inst_sched
= &inst
->resSched
;
105 // ---------------------------------------
106 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
107 if (!idx
|| !inst
->isStore())
108 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, RegManager
, UseDefUnit::ReadSrcReg
, idx
));
111 if ( inst
->isNonSpeculative() ) {
112 // skip execution of non speculative insts until later
113 } else if (inst
->isMemRef()) {
114 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, AGEN
, AGENUnit::GenerateAddr
));
115 if ( inst
->isLoad() ) {
116 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, DTLB
, TLBUnit::DataLookup
));
117 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, DCache
, CacheUnit::InitiateReadData
));
120 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, ExecUnit
, ExecutionUnit::ExecuteInst
));
125 // ---------------------------------------
127 if ( inst
->isStore() ) { // for store, need src reg at this point
128 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, RegManager
, UseDefUnit::ReadSrcReg
, 1));
130 if ( inst
->isLoad() ) {
131 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, DCache
, CacheUnit::CompleteReadData
));
132 } else if ( inst
->isStore() ) {
133 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, DTLB
, TLBUnit::DataLookup
));
134 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, DCache
, CacheUnit::InitiateWriteData
));
139 // ---------------------------------------
141 if (inst
->isNonSpeculative()) {
142 if (inst
->isMemRef())
143 fatal("Schedule doesnt handle Non-Speculative Memory Instructions.\n");
145 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
146 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, MDU
, MultDivUnit::MultDiv
));
148 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, ExecUnit
, ExecutionUnit::ExecuteInst
));
152 if ( inst
->isStore() )
153 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, DCache
, CacheUnit::CompleteWriteData
));
155 // Write Back to Register File
156 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
157 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, RegManager
, UseDefUnit::WriteDestReg
, idx
));
160 // Graduate Instructions
161 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, Grad
, GraduationUnit::GraduateInst
));