src/cpu/inorder/pipeline_traits.5stage.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_PIPELINE_IMPL_HH__
  33 #define __CPU_INORDER_PIPELINE_IMPL_HH__
  34
  35 #include <list>
  36 #include <queue>
  37 #include <vector>
  38
  39 #include "arch/isa_traits.hh"
  40
  41 class InOrderDynInst;
  42
  43 /* This Namespace contains constants, typedefs, functions and
  44  * objects specific to the Pipeline Implementation.
  45  */
  46 namespace ThePipeline {
  47     // Pipeline Constants
  48     const unsigned NumStages = 5;
  49     const unsigned MaxThreads = 3;
  50     const unsigned StageWidth = 1;
  51     const unsigned BackEndStartStage = 2;
  52
  53     // Enumerated List of Resources The Pipeline Uses
  54     enum ResourceList {
  55        FetchSeq = 0,
  56        ITLB,
  57        ICache,
  58        Decode,
  59        BPred,
  60        FetchBuff,
  61        RegManager,
  62        AGEN,
  63        ExecUnit,
  64        DTLB,
  65        DCache,
  66        Grad,
  67        FetchBuff2
  68     };
  69
  70     // Expand this as necessary for your inter stage buffer sizes
  71     static const unsigned interStageBuffSize[] = {
  72         StageWidth, /* Stage 0 - 1 */
  73         StageWidth, /* Stage 1 - 2 */
  74         StageWidth, /* Stage 2 - 3 */
  75         StageWidth, /* Stage 3 - 4 */
  76         StageWidth, /* Stage 4 - 5 */
  77         StageWidth, /* Stage 5 - 6 */
  78         StageWidth, /* Stage 6 - 7 */
  79         StageWidth, /* Stage 7 - 8 */
  80         StageWidth  /* Stage 8 - 9 */
  81     };
  82
  83     typedef InOrderCPUParams Params;
  84     typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
  85
  86     //////////////////////////
  87     // RESOURCE SCHEDULING
  88     //////////////////////////
  89     struct ScheduleEntry {
  90         ScheduleEntry(int stage_num, int _priority, int res_num, int _cmd = 0,
  91                       int _idx = 0) :
  92             stageNum(stage_num), resNum(res_num), cmd(_cmd),
  93             idx(_idx), priority(_priority)
  94         { }
  95         virtual ~ScheduleEntry(){}
  96
  97         // Stage number to perform this service.
  98         int stageNum;
  99
 100         // Resource ID to access
 101         int resNum;
 102
 103         // See specific resource for meaning
 104         unsigned cmd;
 105
 106         // See specific resource for meaning
 107         unsigned idx;
 108
 109         // Some Resources May Need Priority?
 110         int priority;
 111     };
 112
 113     struct entryCompare {
 114         bool operator()(const ScheduleEntry* lhs, const ScheduleEntry* rhs) const
 115         {
 116             // Prioritize first by stage number that the resource is needed
 117             if (lhs->stageNum > rhs->stageNum) {
 118                 return true;
 119             } else if (lhs->stageNum == rhs->stageNum) {
 120                 /*if (lhs->resNum > rhs->resNum) {
 121                   return true;
 122                 } else {
 123                   return false;
 124                   }*/
 125
 126                 if (lhs->priority > rhs->priority) {
 127                   return true;
 128                 } else {
 129                   return false;
 130                 }
 131             } else {
 132                 return false;
 133             }
 134         }
 135     };
 136
 137
 138     typedef std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
 139                                          entryCompare> ResSchedule;
 140
 141     void createFrontEndSchedule(DynInstPtr &inst);
 142     bool createBackEndSchedule(DynInstPtr &inst);
 143     int getNextPriority(DynInstPtr &inst, int stage_num);
 144 };
 145 #endif