src/cpu/inorder/pipeline_traits.9stage.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "cpu/inorder/resources/resource_list.hh"
  33 #include "cpu/inorder/inorder_dyn_inst.hh"
  34 #include "cpu/inorder/pipeline_traits.hh"
  35
  36 using namespace std;
  37
  38 namespace ThePipeline {
  39
  40
  41 //@TODO: create my own Instruction Schedule Class
  42 //that operates as a Priority QUEUE
  43 int getNextPriority(DynInstPtr &inst, int stage_num)
  44 {
  45     int cur_pri = 20;
  46
  47     /*
  48     std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
  49         entryCompare>::iterator sked_it = inst->resSched.begin();
  50
  51     std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
  52         entryCompare>::iterator sked_end = inst->resSched.end();
  53
  54     while (sked_it != sked_end) {
  55
  56         if (sked_it.top()->stageNum == stage_num) {
  57             cur_pri = sked_it.top()->priority;
  58         }
  59
  60         sked_it++;
  61     }
  62     */
  63
  64     return cur_pri;
  65 }
  66
  67 void createFrontEndSchedule(DynInstPtr &inst)
  68 {
  69     int stNum = 0;
  70     int stPri = 0;
  71     // Get Pointer to Instuction's Schedule
  72     ResSchedule *inst_sched = &inst->resSched;
  73
  74     //
  75     // Stage 0
  76     // ---------------------------------------
  77     inst_sched->push(new ScheduleEntry(stNum, stPri, FetchSeq, FetchSeqUnit::AssignNextPC));
  78     stPri++;
  79
  80     inst_sched->push(new ScheduleEntry(stNum, stPri, ITLB, TLBUnit::FetchLookup));
  81     stPri++;
  82
  83     inst_sched->push(new ScheduleEntry(stNum, stPri, ICache, CacheUnit::InitiateFetch));
  84     stPri++;
  85
  86     // Reset Priority / Update Next Stage Number
  87     stNum++;
  88     stPri = 0;
  89
  90     //
  91     // Stage 1
  92     // ---------------------------------------
  93     inst_sched->push(new ScheduleEntry(stNum, stPri, ICache, CacheUnit::CompleteFetch));
  94     stPri++;
  95
  96     inst_sched->push(new ScheduleEntry(stNum, stPri, Decode, DecodeUnit::DecodeInst));
  97     stPri++;
  98
  99     inst_sched->push(new ScheduleEntry(stNum, stPri, BPred, BranchPredictor::PredictBranch));
 100     stPri++;
 101
 102     inst_sched->push(new ScheduleEntry(stNum, stPri, FetchSeq, FetchSeqUnit::UpdateTargetPC));
 103     stPri++;
 104
 105     if (inst->readTid() == 0)
 106         inst_sched->push(new ScheduleEntry(stNum, stPri, FetchBuff, InstBuffer::ScheduleOrBypass));
 107     else //if (inst->readTid() == 1)
 108         inst_sched->push(new ScheduleEntry(stNum, stPri, FetchBuff2, InstBuffer::ScheduleOrBypass));
 109     stPri++;
 110
 111     // Reset Priority / Update Next Stage Number
 112     stNum++;
 113     stPri = 0;
 114
 115     //
 116     // Stage 2
 117     // ---------------------------------------
 118     // Reset Priority / Update Next Stage Number
 119     stNum++;
 120     stPri = 0;
 121 }
 122
 123 bool createBackEndSchedule(DynInstPtr &inst)
 124 {
 125     if (!inst->staticInst) {
 126         return false;
 127     }
 128
 129     std::string name = inst->staticInst->getName();
 130
 131     int stNum = BackEndStartStage;
 132     int stPri = 0;
 133
 134     // Get Pointer to Instuction's Schedule
 135     ResSchedule *inst_sched = &inst->resSched;
 136
 137     //
 138     // Stage 3
 139     // ---------------------------------------
 140     // Set When Source Registers Should be read - Stage 4
 141     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 142         inst_sched->push(new ScheduleEntry(stNum, stPri, RegManager, UseDefUnit::ReadSrcReg, idx));
 143     }
 144     stPri++;
 145
 146     // Reset Priority / Update Next Stage Number
 147     stPri = 0;
 148     stNum++;
 149
 150     //
 151     // Stage 4
 152     // ---------------------------------------
 153     if (inst->isMemRef()) {
 154         inst_sched->push(new ScheduleEntry(stNum, stPri, AGEN, AGENUnit::GenerateAddr));
 155     }
 156
 157     // Reset Priority / Update Next Stage Number
 158     stPri = 0;
 159     stNum++;
 160
 161     //
 162     // Stage 5
 163     // ---------------------------------------
 164     // Execution Unit
 165     if (!inst->isNonSpeculative() && !inst->isMemRef()) {
 166         if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 167             inst_sched->push(new ScheduleEntry(stNum, stPri++, MDU, MultDivUnit::MultDiv));
 168         } else {
 169             inst_sched->push(new ScheduleEntry(stNum, stPri, ExecUnit, ExecutionUnit::ExecuteInst));
 170         }
 171     }
 172     stPri++;
 173
 174     // DCache Initiate Access
 175     if (inst->isMemRef()) {
 176         inst_sched->push(new ScheduleEntry(stNum, stPri, DTLB, TLBUnit::DataLookup));
 177         stPri++;
 178
 179         if (inst->isLoad()) {
 180             inst_sched->push(new ScheduleEntry(stNum, stPri, DCache, CacheUnit::InitiateReadData));
 181         } else if (inst->isStore()) {
 182             inst_sched->push(new ScheduleEntry(stNum, stPri, DCache, CacheUnit::InitiateWriteData));
 183         }
 184     }
 185
 186     // Reset Priority / Update Next Stage Number
 187     stPri = 0;
 188     stNum++;
 189
 190     //
 191     // Stage 6
 192     // ---------------------------------------
 193     // DCache Complete Access
 194     if (inst->isMemRef()) {
 195         if (inst->isLoad()) {
 196             inst_sched->push(new ScheduleEntry(stNum, stPri, DCache, CacheUnit::CompleteReadData));
 197         } else if (inst->isStore()) {
 198             inst_sched->push(new ScheduleEntry(stNum, stPri, DCache, CacheUnit::CompleteWriteData));
 199         }
 200     }
 201
 202     // Reset Priority / Update Next Stage Number
 203     stPri = 0;
 204     stNum++;
 205
 206     //
 207     // Stage 7
 208     // ---------------------------------------
 209     // Reset Priority / Update Next Stage Number
 210     stPri = 0;
 211     stNum++;
 212
 213     //
 214     // Stage 8
 215     // ---------------------------------------
 216     // NonSpeculative Execution
 217     if (inst->isNonSpeculative() ) {
 218         if (inst->isMemRef())
 219             fatal("Schedule doesnt handle Non-Speculative Memory Instructions.\n");
 220
 221         inst_sched->push(new ScheduleEntry(stNum, stPri, ExecUnit, ExecutionUnit::ExecuteInst));
 222         stPri++;
 223     }
 224
 225     // Write Back to Register File
 226     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 227         inst_sched->push(new ScheduleEntry(stNum, stPri, RegManager, UseDefUnit::WriteDestReg, idx));
 228         stPri++;
 229     }
 230
 231     // Graduate Instructions
 232     inst_sched->push(new ScheduleEntry(stNum, stPri, Grad, GraduationUnit::GraduateInst));
 233     stPri++;
 234
 235     // Reset Priority / Update Next Stage Number
 236     stPri = 0;
 237     stNum++;
 238
 239     return true;
 240 }
 241
 242 };