2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #include "cpu/inorder/resources/resource_list.hh"
33 #include "cpu/inorder/inorder_dyn_inst.hh"
34 #include "cpu/inorder/pipeline_traits.hh"
38 namespace ThePipeline
{
41 //@TODO: create my own Instruction Schedule Class
42 //that operates as a Priority QUEUE
43 int getNextPriority(DynInstPtr
&inst
, int stage_num
)
48 std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
49 entryCompare>::iterator sked_it = inst->resSched.begin();
51 std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
52 entryCompare>::iterator sked_end = inst->resSched.end();
54 while (sked_it != sked_end) {
56 if (sked_it.top()->stageNum == stage_num) {
57 cur_pri = sked_it.top()->priority;
67 void createFrontEndSchedule(DynInstPtr
&inst
)
71 // Get Pointer to Instuction's Schedule
72 ResSchedule
*inst_sched
= &inst
->resSched
;
76 // ---------------------------------------
77 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, FetchSeq
, FetchSeqUnit::AssignNextPC
));
80 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, ITLB
, TLBUnit::FetchLookup
));
83 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, ICache
, CacheUnit::InitiateFetch
));
86 // Reset Priority / Update Next Stage Number
92 // ---------------------------------------
93 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, ICache
, CacheUnit::CompleteFetch
));
96 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, Decode
, DecodeUnit::DecodeInst
));
99 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, BPred
, BranchPredictor::PredictBranch
));
102 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, FetchSeq
, FetchSeqUnit::UpdateTargetPC
));
105 if (inst
->readTid() == 0)
106 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, FetchBuff
, InstBuffer::ScheduleOrBypass
));
107 else //if (inst->readTid() == 1)
108 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, FetchBuff2
, InstBuffer::ScheduleOrBypass
));
111 // Reset Priority / Update Next Stage Number
117 // ---------------------------------------
118 // Reset Priority / Update Next Stage Number
123 bool createBackEndSchedule(DynInstPtr
&inst
)
125 if (!inst
->staticInst
) {
129 std::string name
= inst
->staticInst
->getName();
131 int stNum
= BackEndStartStage
;
134 // Get Pointer to Instuction's Schedule
135 ResSchedule
*inst_sched
= &inst
->resSched
;
139 // ---------------------------------------
140 // Set When Source Registers Should be read - Stage 4
141 for (int idx
=0; idx
< inst
->numSrcRegs(); idx
++) {
142 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, RegManager
, UseDefUnit::ReadSrcReg
, idx
));
146 // Reset Priority / Update Next Stage Number
152 // ---------------------------------------
153 if (inst
->isMemRef()) {
154 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, AGEN
, AGENUnit::GenerateAddr
));
157 // Reset Priority / Update Next Stage Number
163 // ---------------------------------------
165 if (!inst
->isNonSpeculative() && !inst
->isMemRef()) {
166 if (inst
->opClass() == IntMultOp
|| inst
->opClass() == IntDivOp
) {
167 inst_sched
->push(new ScheduleEntry(stNum
, stPri
++, MDU
, MultDivUnit::MultDiv
));
169 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, ExecUnit
, ExecutionUnit::ExecuteInst
));
174 // DCache Initiate Access
175 if (inst
->isMemRef()) {
176 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, DTLB
, TLBUnit::DataLookup
));
179 if (inst
->isLoad()) {
180 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, DCache
, CacheUnit::InitiateReadData
));
181 } else if (inst
->isStore()) {
182 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, DCache
, CacheUnit::InitiateWriteData
));
186 // Reset Priority / Update Next Stage Number
192 // ---------------------------------------
193 // DCache Complete Access
194 if (inst
->isMemRef()) {
195 if (inst
->isLoad()) {
196 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, DCache
, CacheUnit::CompleteReadData
));
197 } else if (inst
->isStore()) {
198 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, DCache
, CacheUnit::CompleteWriteData
));
202 // Reset Priority / Update Next Stage Number
208 // ---------------------------------------
209 // Reset Priority / Update Next Stage Number
215 // ---------------------------------------
216 // NonSpeculative Execution
217 if (inst
->isNonSpeculative() ) {
218 if (inst
->isMemRef())
219 fatal("Schedule doesnt handle Non-Speculative Memory Instructions.\n");
221 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, ExecUnit
, ExecutionUnit::ExecuteInst
));
225 // Write Back to Register File
226 for (int idx
=0; idx
< inst
->numDestRegs(); idx
++) {
227 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, RegManager
, UseDefUnit::WriteDestReg
, idx
));
231 // Graduate Instructions
232 inst_sched
->push(new ScheduleEntry(stNum
, stPri
, Grad
, GraduationUnit::GraduateInst
));
235 // Reset Priority / Update Next Stage Number