src/cpu/inorder/pipeline_traits.9stage.smt2.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "cpu/inorder/resources/resource_list.hh"
  33 #include "cpu/inorder/inorder_dyn_inst.hh"
  34 #include "cpu/inorder/pipeline_traits.hh"
  35
  36 using namespace std;
  37
  38 namespace ThePipeline {
  39
  40
  41 //@TODO: create my own Instruction Schedule Class
  42 //that operates as a Priority QUEUE
  43 int getNextPriority(DynInstPtr &inst, int stage_num)
  44 {
  45     int cur_pri = 20;
  46
  47     /*
  48     std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
  49         entryCompare>::iterator sked_it = inst->resSched.begin();
  50
  51     std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
  52         entryCompare>::iterator sked_end = inst->resSched.end();
  53
  54     while (sked_it != sked_end) {
  55
  56         if (sked_it.top()->stageNum == stage_num) {
  57             cur_pri = sked_it.top()->priority;
  58         }
  59
  60         sked_it++;
  61     }
  62     */
  63
  64     return cur_pri;
  65 }
  66
  67 void createFrontEndSchedule(DynInstPtr &inst)
  68 {
  69     int stNum = 0;
  70     int stPri = 0;
  71     // Get Pointer to Instuction's Schedule
  72     ResSchedule *inst_sched = &inst->resSched;
  73
  74     //
  75     // Stage 0
  76     // ---------------------------------------
  77     inst_sched->push(new ScheduleEntry(stNum, stPri, FetchSeq, FetchSeqUnit::AssignNextPC));
  78     stPri++;
  79
  80     inst_sched->push(new ScheduleEntry(stNum, stPri, ITLB, TLBUnit::FetchLookup));
  81     stPri++;
  82
  83     inst_sched->push(new ScheduleEntry(stNum, stPri, ICache, CacheUnit::InitiateFetch));
  84     stPri++;
  85
  86     // Reset Priority / Update Next Stage Number
  87     stNum++;
  88     stPri = 0;
  89
  90     //
  91     // Stage 1
  92     // ---------------------------------------
  93     inst_sched->push(new ScheduleEntry(stNum, stPri, ICache, CacheUnit::CompleteFetch));
  94     stPri++;
  95
  96     inst_sched->push(new ScheduleEntry(stNum, stPri, Decode, DecodeUnit::DecodeInst));
  97     stPri++;
  98
  99     inst_sched->push(new ScheduleEntry(stNum, stPri, BPred, BranchPredictor::PredictBranch));
 100     stPri++;
 101
 102     inst_sched->push(new ScheduleEntry(stNum, stPri, FetchSeq, FetchSeqUnit::UpdateTargetPC));
 103     stPri++;
 104
 105     int fetch_buff_num = FetchBuff + inst->readTid();
 106
 107     inst_sched->push(new ScheduleEntry(stNum, stPri, fetch_buff_num, InstBuffer::ScheduleOrBypass));
 108
 109     // Reset Priority / Update Next Stage Number
 110     stNum++;
 111     stPri = 0;
 112
 113     //
 114     // Stage 2
 115     // ---------------------------------------
 116     // Reset Priority / Update Next Stage Number
 117     stNum++;
 118     stPri = 0;
 119 }
 120
 121 bool createBackEndSchedule(DynInstPtr &inst)
 122 {
 123     if (!inst->staticInst) {
 124         return false;
 125     }
 126
 127     std::string name = inst->staticInst->getName();
 128
 129     int stNum = BackEndStartStage;
 130     int stPri = 0;
 131
 132     // Get Pointer to Instuction's Schedule
 133     ResSchedule *inst_sched = &inst->resSched;
 134
 135     //
 136     // Stage 3
 137     // ---------------------------------------
 138     // Set When Source Registers Should be read - Stage 4
 139     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
 140         inst_sched->push(new ScheduleEntry(stNum, stPri, RegManager, UseDefUnit::ReadSrcReg, idx));
 141     }
 142     stPri++;
 143
 144     // Reset Priority / Update Next Stage Number
 145     stPri = 0;
 146     stNum++;
 147
 148     //
 149     // Stage 4
 150     // ---------------------------------------
 151     if (inst->isMemRef()) {
 152         inst_sched->push(new ScheduleEntry(stNum, stPri, AGEN, AGENUnit::GenerateAddr));
 153     }
 154
 155     // Reset Priority / Update Next Stage Number
 156     stPri = 0;
 157     stNum++;
 158
 159     //
 160     // Stage 5
 161     // ---------------------------------------
 162     // Execution Unit
 163     if (!inst->isNonSpeculative() && !inst->isMemRef()) {
 164         //if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 165             //inst_sched->push(new ScheduleEntry(stNum, stPri++, MDU, MultDivUnit::MultDiv));
 166             //} else {
 167             inst_sched->push(new ScheduleEntry(stNum, stPri, ExecUnit, ExecutionUnit::ExecuteInst));
 168             //}
 169     }
 170     stPri++;
 171
 172     // DCache Initiate Access
 173     if (inst->isMemRef()) {
 174         inst_sched->push(new ScheduleEntry(stNum, stPri, DTLB, TLBUnit::DataLookup));
 175         stPri++;
 176
 177         if (inst->isLoad()) {
 178             inst_sched->push(new ScheduleEntry(stNum, stPri, DCache, CacheUnit::InitiateReadData));
 179         } else if (inst->isStore()) {
 180             inst_sched->push(new ScheduleEntry(stNum, stPri, DCache, CacheUnit::InitiateWriteData));
 181         }
 182     }
 183
 184     // Reset Priority / Update Next Stage Number
 185     stPri = 0;
 186     stNum++;
 187
 188     //
 189     // Stage 6
 190     // ---------------------------------------
 191     // DCache Complete Access
 192     if (inst->isMemRef()) {
 193         if (inst->isLoad()) {
 194             inst_sched->push(new ScheduleEntry(stNum, stPri, DCache, CacheUnit::CompleteReadData));
 195         } else if (inst->isStore()) {
 196             inst_sched->push(new ScheduleEntry(stNum, stPri, DCache, CacheUnit::CompleteWriteData));
 197         }
 198     }
 199
 200     // Reset Priority / Update Next Stage Number
 201     stPri = 0;
 202     stNum++;
 203
 204     //
 205     // Stage 7
 206     // ---------------------------------------
 207     // Reset Priority / Update Next Stage Number
 208     stPri = 0;
 209     stNum++;
 210
 211     //
 212     // Stage 8
 213     // ---------------------------------------
 214     // NonSpeculative Execution
 215     if (inst->isNonSpeculative() ) {
 216         if (inst->isMemRef())
 217             fatal("Schedule doesnt handle Non-Speculative Memory Instructions.\n");
 218
 219         inst_sched->push(new ScheduleEntry(stNum, stPri, ExecUnit, ExecutionUnit::ExecuteInst));
 220         stPri++;
 221     }
 222
 223     // Write Back to Register File
 224     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 225         inst_sched->push(new ScheduleEntry(stNum, stPri, RegManager, UseDefUnit::WriteDestReg, idx));
 226         stPri++;
 227     }
 228
 229     // Graduate Instructions
 230     inst_sched->push(new ScheduleEntry(stNum, stPri, Grad, GraduationUnit::GraduateInst));
 231     stPri++;
 232
 233     // Reset Priority / Update Next Stage Number
 234     stPri = 0;
 235     stNum++;
 236
 237     return true;
 238 }
 239
 240 };