2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_PIPELINE_IMPL_HH__
33 #define __CPU_INORDER_PIPELINE_IMPL_HH__
40 #include "arch/isa_traits.hh"
41 #include "cpu/inorder/params.hh"
45 /* This Namespace contains constants, typedefs, functions and
46 * objects specific to the Pipeline Implementation.
48 namespace ThePipeline {
50 const unsigned NumStages = 9;
51 const unsigned MaxThreads = 2;
52 const unsigned StageWidth = 1;
53 const unsigned BackEndStartStage = 3;
55 // Use this to over-ride default stage widths
56 static std::map<unsigned, unsigned> stageBufferSizes;
58 //static unsigned interStageBuffSize[NumStages];
60 static const unsigned interStageBuffSize[NumStages] = {
61 StageWidth, /* Stage 0 - 1 */
62 StageWidth, /* Stage 1 - 2 */
63 MaxThreads * 4, /* Stage 2 - 3 */
64 StageWidth, /* Stage 3 - 4 */
65 MaxThreads * 4, /* Stage 4 - 5 */
66 StageWidth, /* Stage 5 - 6 */
67 StageWidth, /* Stage 6 - 7 */
68 StageWidth, /* Stage 7 - 8 */
69 MaxThreads /* Stage 8 - 9 */
73 // Enumerated List of Resources The Pipeline Uses
90 typedef InOrderCPUParams Params;
91 typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
93 //void initPipelineTraits();
95 //////////////////////////
96 // RESOURCE SCHEDULING
97 //////////////////////////
98 struct ScheduleEntry {
99 ScheduleEntry(int stage_num, int _priority, int res_num, int _cmd = 0,
101 stageNum(stage_num), resNum(res_num), cmd(_cmd),
102 idx(_idx), priority(_priority)
104 virtual ~ScheduleEntry(){}
106 // Stage number to perform this service.
109 // Resource ID to access
112 // See specific resource for meaning
115 // See specific resource for meaning
118 // Some Resources May Need Priority?
122 struct entryCompare {
123 bool operator()(const ScheduleEntry* lhs, const ScheduleEntry* rhs) const
125 // Prioritize first by stage number that the resource is needed
126 if (lhs->stageNum > rhs->stageNum) {
128 } else if (lhs->stageNum == rhs->stageNum) {
129 /*if (lhs->resNum > rhs->resNum) {
135 if (lhs->priority > rhs->priority) {
147 typedef std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
148 entryCompare> ResSchedule;
150 void createFrontEndSchedule(DynInstPtr &inst);
151 bool createBackEndSchedule(DynInstPtr &inst);
152 int getNextPriority(DynInstPtr &inst, int stage_num);