src/cpu/inorder/pipeline_traits.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "cpu/inorder/pipeline_traits.hh"
  33 #include "cpu/inorder/inorder_dyn_inst.hh"
  34 #include "cpu/inorder/resources/resource_list.hh"
  35
  36 using namespace std;
  37
  38 namespace ThePipeline {
  39
  40 //@TODO: create my own Instruction Schedule Class
  41 //that operates as a Priority QUEUE
  42 int getNextPriority(DynInstPtr &inst, int stage_num)
  43 {
  44     int cur_pri = 20;
  45
  46     /*
  47     std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
  48         entryCompare>::iterator sked_it = inst->resSched.begin();
  49
  50     std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>,
  51         entryCompare>::iterator sked_end = inst->resSched.end();
  52
  53     while (sked_it != sked_end) {
  54
  55         if (sked_it.top()->stageNum == stage_num) {
  56             cur_pri = sked_it.top()->priority;
  57         }
  58
  59         sked_it++;
  60     }
  61     */
  62
  63     return cur_pri;
  64 }
  65
  66 void createFrontEndSchedule(DynInstPtr &inst)
  67 {
  68     InstStage *I = inst->addStage();
  69     InstStage *E = inst->addStage();
  70
  71     I->needs(FetchSeq, FetchSeqUnit::AssignNextPC);
  72     I->needs(ITLB, TLBUnit::FetchLookup);
  73     I->needs(ICache, CacheUnit::InitiateFetch);
  74
  75     E->needs(ICache, CacheUnit::CompleteFetch);
  76     E->needs(Decode, DecodeUnit::DecodeInst);
  77     E->needs(BPred, BranchPredictor::PredictBranch);
  78     E->needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
  79 }
  80
  81 bool createBackEndSchedule(DynInstPtr &inst)
  82 {
  83     if (!inst->staticInst) {
  84         return false;
  85     }
  86
  87     InstStage *E = inst->currentStage();
  88     InstStage *M = inst->addStage();
  89     InstStage *A = inst->addStage();
  90     InstStage *W = inst->addStage();
  91
  92     for (int idx=0; idx < inst->numSrcRegs(); idx++) {
  93         if (!idx || !inst->isStore()) {
  94             E->needs(RegManager, UseDefUnit::ReadSrcReg, idx);
  95         }
  96     }
  97
  98
  99     if ( inst->isNonSpeculative() ) {
 100         // skip execution of non speculative insts until later
 101     } else if ( inst->isMemRef() ) {
 102         if ( inst->isLoad() ) {
 103             E->needs(AGEN, AGENUnit::GenerateAddr);
 104             E->needs(DTLB, TLBUnit::DataLookup);
 105             E->needs(DCache, CacheUnit::InitiateReadData);
 106         }
 107     } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 108         E->needs(MDU, MultDivUnit::StartMultDiv);
 109
 110         // ZERO-LATENCY Multiply:
 111         // E->needs(MDU, MultDivUnit::MultDiv);
 112     } else {
 113         E->needs(ExecUnit, ExecutionUnit::ExecuteInst);
 114     }
 115
 116     if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
 117         M->needs(MDU, MultDivUnit::EndMultDiv);
 118     }
 119
 120     if ( inst->isLoad() ) {
 121         M->needs(DCache, CacheUnit::CompleteReadData);
 122     } else if ( inst->isStore() ) {
 123         M->needs(RegManager, UseDefUnit::ReadSrcReg, 1);
 124         M->needs(AGEN, AGENUnit::GenerateAddr);
 125         M->needs(DTLB, TLBUnit::DataLookup);
 126         M->needs(DCache, CacheUnit::InitiateWriteData);
 127     }
 128
 129     if ( inst->isStore() ) {
 130         A->needs(DCache, CacheUnit::CompleteWriteData);
 131     }
 132
 133     if ( inst->isNonSpeculative() ) {
 134         if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
 135         W->needs(ExecUnit, ExecutionUnit::ExecuteInst);
 136     }
 137
 138     for (int idx=0; idx < inst->numDestRegs(); idx++) {
 139         W->needs(RegManager, UseDefUnit::WriteDestReg, idx);
 140     }
 141
 142     W->needs(Grad, GraduationUnit::GraduateInst);
 143
 144     return true;
 145 }
 146
 147 InstStage::InstStage(DynInstPtr inst, int stage_num)
 148 {
 149     stageNum = stage_num;
 150     nextTaskPriority = 0;
 151     instSched = &inst->resSched;
 152 }
 153
 154 };