src/cpu/inorder/resource.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_RESOURCE_HH__
  33 #define __CPU_INORDER_RESOURCE_HH__
  34
  35 #include <list>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "base/types.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/pipeline_traits.hh"
  42 #include "cpu/inst_seq.hh"
  43 #include "sim/eventq.hh"
  44 #include "sim/sim_object.hh"
  45
  46 class Event;
  47 class InOrderCPU;
  48 class ResourceEvent;
  49 class ResourceRequest;
  50
  51 typedef ResourceRequest ResReq;
  52 typedef ResourceRequest* ResReqPtr;
  53
  54 class Resource {
  55   public:
  56     typedef ThePipeline::DynInstPtr DynInstPtr;
  57
  58     friend class ResourceEvent;
  59     friend class ResourceRequest;
  60
  61   public:
  62     Resource(std::string res_name, int res_id, int res_width,
  63              int res_latency, InOrderCPU *_cpu);
  64     virtual ~Resource();
  65
  66
  67     /** Return name of this resource */
  68     virtual std::string name();
  69
  70     /** Define this function if resource, has a port to connect to an outside
  71      *  simulation object.
  72      */
  73     virtual Port* getPort(const std::string &if_name, int idx)
  74     { return NULL; }
  75
  76     /** Return ID for this resource */
  77     int getId() { return id; }
  78
  79     /** Any extra initiliazation stuff can be set up using this function that
  80      * should get called before the simulation starts (tick 0)
  81      */
  82     virtual void init();
  83     virtual void initSlots();
  84
  85     /** Register Stats for this resource */
  86     virtual void regStats() { }
  87
  88     /** Resources that care about thread activation override this. */
  89     virtual void activateThread(ThreadID tid) { }
  90
  91     /** Deactivate Thread. Default action is to squash all instructions
  92      *  from deactivated thread.
  93      */
  94     virtual void deactivateThread(ThreadID tid);
  95
  96     /** Resources that care about thread activation override this. */
  97     virtual void suspendThread(ThreadID tid) { }
  98
  99     /** Will be called the cycle before a context switch. Any bookkeeping
 100      *  that needs to be kept for that, can be done here
 101      */
 102     virtual void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid) { }
 103
 104     /** Resources that care when an instruction has been graduated
 105      *  can override this
 106      */
 107     virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
 108
 109     /** Request usage of this resource. Returns a ResourceRequest object
 110      *  with all the necessary resource information
 111      */
 112     virtual ResourceRequest* request(DynInstPtr inst);
 113
 114     /** Get the next available slot in this resource. Instruction is passed
 115      *  so that resources can check the instruction before allocating a slot
 116      *  if necessary.
 117      */
 118     virtual int getSlot(DynInstPtr inst);
 119
 120     /** Find the slot that this instruction is using in a resource */
 121     virtual int findSlot(DynInstPtr inst);
 122
 123     /** Free a resource slot */
 124     virtual void freeSlot(int slot_idx);
 125
 126     /** Request usage of a resource for this instruction. If this instruction
 127      *  already has made this request to this resource, and that request is
 128      *  uncompleted this function will just return that request
 129      */
 130     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 131                                         int res_idx, int slot_num,
 132                                         unsigned cmd);
 133
 134     /** Schedule Execution of This Resource For A Given Slot*/
 135     void scheduleExecution(int slot_idx);
 136
 137     /** Execute the function of this resource. The Default is action
 138      *  is to do nothing. More specific models will derive from this
 139      *  class and define their own execute function.
 140      */
 141     virtual void execute(int slot_idx);
 142
 143     /** Fetch on behalf of an instruction. Will check to see
 144      *  if instruction is actually in resource before
 145      *  trying to fetch. Needs to be defined for derived units.
 146      */
 147     virtual Fault doFetchAccess(DynInstPtr inst)
 148     { panic("doFetchAccess undefined for %s", name()); return NoFault; }
 149
 150     /** Read/Write on behalf of an instruction. Will check to see
 151      *  if instruction is actually in resource before
 152      *  trying to do access.Needs to be defined for derived units.
 153      */
 154     virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL)
 155     { panic("doCacheAccess undefined for %s", name()); return NoFault; }
 156
 157     /** Squash All Requests After This Seq Num */
 158     virtual void squash(DynInstPtr inst, int stage_num,
 159                         InstSeqNum squash_seq_num, ThreadID tid);
 160
 161     virtual void squashDueToMemStall(DynInstPtr inst, int stage_num,
 162                                      InstSeqNum squash_seq_num, ThreadID tid);
 163
 164     /** The number of instructions available that this resource can
 165      *  can still process
 166      */
 167     int slotsAvail();
 168
 169     /** The number of instructions using this resource */
 170     int slotsInUse();
 171
 172     /** Schedule resource event, regardless of its current state. */
 173     void scheduleEvent(int slot_idx, int delay);
 174
 175     /** Find instruction in list, Schedule resource event, regardless of its
 176      *  current state. */
 177     bool scheduleEvent(DynInstPtr inst, int delay);
 178
 179     /** Unschedule resource event, regardless of its current state. */
 180     void unscheduleEvent(int slot_idx);
 181
 182     /** Unschedule resource event, regardless of its current state. */
 183     bool unscheduleEvent(DynInstPtr inst);
 184
 185     /** Return the number of cycles in 'Tick' format */
 186     Tick ticks(int numCycles);
 187
 188     /** Find the request that corresponds to this instruction */
 189     virtual ResReqPtr findRequest(DynInstPtr inst);
 190
 191     /** */
 192     void rejectRequest(DynInstPtr inst);
 193
 194     /** Request a Resource again. Some resources have to special process this
 195      *  in subsequent accesses.
 196      */
 197     virtual void requestAgain(DynInstPtr inst, bool &try_request);
 198
 199     /** Return Latency of Resource */
 200     /*  Can be overridden for complex cases */
 201     virtual int getLatency(int slot_num) { return latency; }
 202
 203   protected:
 204     /** The name of this resource */
 205     std::string resName;
 206
 207     /** ID of the resource. The Resource Pool uses this # to identify this
 208      *  resource.
 209      */
 210     int id;
 211
 212     /** The number of instructions the resource can simultaneously
 213      *  process.
 214      */
 215     int width;
 216
 217     /** Constant latency for this resource.
 218      *  Note: Dynamic latency resources set this to 0 and
 219      *  manage the latency themselves
 220      */
 221     const int latency;
 222
 223   public:
 224     /** List of all Requests the Resource is Servicing. Each request
 225         represents part of the resource's bandwidth
 226     */
 227     std::vector<ResReqPtr> reqs;
 228
 229     /** A list of all the available execution slots for this resource.
 230      *  This correlates with the actual resource event idx.
 231      */
 232     std::vector<int> availSlots;
 233
 234     /** The CPU(s) that this resource interacts with */
 235     InOrderCPU *cpu;
 236
 237   protected:
 238     /** The resource event used for scheduling resource slots on the
 239      *  event queue
 240      */
 241     ResourceEvent *resourceEvent;
 242
 243     /** Default denied resource request pointer*/
 244     ResReqPtr deniedReq;
 245 };
 246
 247 class ResourceEvent : public Event
 248 {
 249   public:
 250     /** Pointer to the Resource this is an event for */
 251     Resource *resource;
 252
 253
 254     /// Resource events that come before other associated CPU events
 255     /// (for InOrderCPU model).
 256     /// check src/sim/eventq.hh for more event priorities.
 257     enum InOrderPriority {
 258         Resource_Event_Pri = 45,
 259     };
 260
 261     /** The Resource Slot that this event is servicing */
 262     int slotIdx;
 263
 264     /** Constructs a resource event. */
 265     ResourceEvent();
 266     ResourceEvent(Resource *res, int slot_idx);
 267     virtual ~ResourceEvent() { }
 268
 269     /** Initialize data for this resource event. */
 270     virtual void init(Resource *res, int slot_idx);
 271
 272     /** Processes a resource event. */
 273     virtual void process();
 274
 275     /** Returns the description of the resource event. */
 276     const char *description();
 277
 278     /** Set slot idx for event */
 279     void setSlot(int slot) { slotIdx = slot; }
 280
 281     /** Schedule resource event, regardless of its current state. */
 282     void scheduleEvent(int delay);
 283
 284     /** Unschedule resource event, regardless of its current state. */
 285     void unscheduleEvent()
 286     {
 287         if (scheduled())
 288             squash();
 289     }
 290
 291 };
 292
 293 class ResourceRequest
 294 {
 295   public:
 296     typedef ThePipeline::DynInstPtr DynInstPtr;
 297
 298     static int resReqID;
 299
 300     static int maxReqCount;
 301
 302     friend class Resource;
 303
 304   public:
 305     ResourceRequest(Resource *_res);
 306
 307     virtual ~ResourceRequest();
 308
 309     std::string name();
 310
 311     int reqID;
 312
 313     virtual void setRequest(DynInstPtr _inst, int stage_num,
 314                     int res_idx, int slot_num, unsigned _cmd);
 315
 316     virtual void clearRequest();
 317
 318     /** Acknowledge that this is a request is done and remove
 319      *  from resource.
 320      */
 321     void done(bool completed = true);
 322
 323     void freeSlot();
 324
 325     /////////////////////////////////////////////
 326     //
 327     // GET RESOURCE REQUEST IDENTIFICATION / INFO
 328     //
 329     /////////////////////////////////////////////
 330     /** Get Resource Index */
 331     int getResIdx() { return resIdx; }
 332
 333     /** Get Slot Number */
 334     int getSlot() { return slotNum; }
 335     bool hasSlot()  { return slotNum >= 0; }
 336
 337     /** Get Stage Number */
 338     int getStageNum() { return stageNum; }
 339
 340     /** Set/Get Thread Ids */
 341     void setTid(ThreadID _tid) { tid = _tid; }
 342     ThreadID getTid() { return tid; }
 343
 344     /** Instruction this request is for */
 345     DynInstPtr getInst() { return inst; }
 346
 347     /** Data from this request. Overridden by Resource-Specific Request
 348      *  Objects
 349      */
 350     virtual PacketDataPtr getData() { return NULL; }
 351
 352     /** Pointer to Resource that is being used */
 353     Resource *res;
 354
 355     /** Instruction being used */
 356     DynInstPtr inst;
 357
 358     /** Not guaranteed to be set, used for debugging */
 359     InstSeqNum seqNum;
 360
 361     /** Command For This Resource */
 362     unsigned cmd;
 363
 364     short stagePasses;
 365
 366     bool valid;
 367
 368     bool doneInResource;
 369
 370     ////////////////////////////////////////
 371     //
 372     // GET RESOURCE REQUEST STATUS FROM VARIABLES
 373     //
 374     ////////////////////////////////////////
 375     /** Get/Set Completed variables */
 376     bool isCompleted() { return completed; }
 377     void setCompleted(bool cond = true) { completed = cond; }
 378
 379     /** Get/Set Squashed variables */
 380     bool isSquashed() { return squashed; }
 381     void setSquashed() { squashed = true; }
 382
 383     /** Get/Set IsProcessing variables */
 384     bool isProcessing() { return processing; }
 385     void setProcessing() { processing = true; }
 386
 387     /** Get/Set IsWaiting variables */
 388     bool isMemStall() { return memStall; }
 389     void setMemStall(bool stall = true) { memStall = stall; }
 390
 391   protected:
 392     /** Resource Identification */
 393     ThreadID tid;
 394     int stageNum;
 395     int resIdx;
 396     int slotNum;
 397
 398     /** Resource Request Status */
 399     bool completed;
 400     bool squashed;
 401     bool processing;
 402
 403     bool memStall;
 404 };
 405
 406 #endif //__CPU_INORDER_RESOURCE_HH__