src/cpu/inorder/resource.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_RESOURCE_HH__
  33 #define __CPU_INORDER_RESOURCE_HH__
  34
  35 #include <list>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "base/types.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/pipeline_traits.hh"
  42 #include "cpu/inst_seq.hh"
  43 #include "sim/eventq.hh"
  44 #include "sim/sim_object.hh"
  45
  46 class Event;
  47 class InOrderCPU;
  48 class ResourceEvent;
  49 class ResourceRequest;
  50
  51 typedef ResourceRequest ResReq;
  52 typedef ResourceRequest* ResReqPtr;
  53
  54 class CacheRequest;
  55 typedef CacheRequest* CacheReqPtr;
  56
  57 class Resource {
  58   public:
  59     typedef ThePipeline::DynInstPtr DynInstPtr;
  60
  61     friend class ResourceEvent;
  62     friend class ResourceRequest;
  63
  64   public:
  65     Resource(std::string res_name, int res_id, int res_width,
  66              Cycles res_latency, InOrderCPU *_cpu);
  67     virtual ~Resource();
  68
  69
  70     /** Return name of this resource */
  71     virtual std::string name();
  72
  73     /** Return ID for this resource */
  74     int getId() { return id; }
  75
  76     /** Any extra initiliazation stuff can be set up using this function that
  77      * should get called before the simulation starts (tick 0)
  78      */
  79     virtual void init();
  80     virtual void initSlots();
  81
  82     /** Register Stats for this resource */
  83     virtual void regStats() { }
  84
  85     /** Resources that care about thread activation override this. */
  86     virtual void activateThread(ThreadID tid) { }
  87
  88     /** Deactivate Thread. Default action is to squash all instructions
  89      *  from deactivated thread.
  90      */
  91     virtual void deactivateThread(ThreadID tid);
  92
  93     /** Resources that care about thread activation override this. */
  94     virtual void suspendThread(ThreadID tid) { }
  95
  96     /** Will be called the cycle before a context switch. Any bookkeeping
  97      *  that needs to be kept for that, can be done here
  98      */
  99     virtual void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid) { }
 100
 101     /** Resources that care when an instruction has been graduated
 102      *  can override this
 103      */
 104     virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
 105
 106     /** Post-processsing for Trap Generated from this instruction */
 107     virtual void trap(Fault fault, ThreadID tid, DynInstPtr inst) { }
 108
 109     /** Request usage of this resource. Returns a ResourceRequest object
 110      *  with all the necessary resource information
 111      */
 112     virtual ResourceRequest* request(DynInstPtr inst);
 113
 114     /** Get the next available slot in this resource. Instruction is passed
 115      *  so that resources can check the instruction before allocating a slot
 116      *  if necessary.
 117      */
 118     virtual int getSlot(DynInstPtr inst);
 119
 120     /** Find the slot that this instruction is using in a resource */
 121     virtual int findSlot(DynInstPtr inst);
 122
 123     /** Free a resource slot */
 124     virtual void freeSlot(int slot_idx);
 125
 126     /** Request usage of a resource for this instruction. If this instruction
 127      *  already has made this request to this resource, and that request is
 128      *  uncompleted this function will just return that request
 129      */
 130     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
 131                                         int res_idx, int slot_num,
 132                                         unsigned cmd);
 133
 134     /** Schedule Execution of This Resource For A Given Slot*/
 135     void scheduleExecution(int slot_idx);
 136
 137     /** Execute the function of this resource. The Default is action
 138      *  is to do nothing. More specific models will derive from this
 139      *  class and define their own execute function.
 140      */
 141     virtual void execute(int slot_idx);
 142
 143     /** Fetch on behalf of an instruction. Will check to see
 144      *  if instruction is actually in resource before
 145      *  trying to fetch. Needs to be defined for derived units.
 146      */
 147     virtual Fault doFetchAccess(DynInstPtr inst)
 148     { panic("doFetchAccess undefined for %s", name()); return NoFault; }
 149
 150     /** Read/Write on behalf of an instruction. Will check to see
 151      *  if instruction is actually in resource before
 152      *  trying to do access.Needs to be defined for derived units.
 153      */
 154     virtual void doCacheAccess(DynInstPtr inst, uint64_t *write_result = NULL,
 155                                CacheReqPtr split_req = NULL)
 156     { panic("doCacheAccess undefined for %s", name()); }
 157
 158     /** Setup Squash to be sent out to pipeline and resource pool */
 159     void setupSquash(DynInstPtr inst, int stage_num, ThreadID tid);
 160
 161     /** Squash All Requests After This Seq Num */
 162     virtual void squash(DynInstPtr inst, int stage_num,
 163                         InstSeqNum squash_seq_num, ThreadID tid);
 164
 165     /** Squash Requests Due to a Memory Stall (By Default, same as "squash" */
 166     virtual void squashDueToMemStall(DynInstPtr inst, int stage_num,
 167                                      InstSeqNum squash_seq_num, ThreadID tid);
 168
 169     /** Handle Squash & Trap that occured from an instruction in a resource */
 170     void squashThenTrap(int stage_num, DynInstPtr inst);
 171
 172     /** The number of instructions available that this resource can
 173      *  can still process
 174      */
 175     int slotsAvail();
 176
 177     /** The number of instructions using this resource */
 178     int slotsInUse();
 179
 180     /** Schedule resource event, regardless of its current state. */
 181     void scheduleEvent(int slot_idx, Cycles delay);
 182
 183     /** Find instruction in list, Schedule resource event, regardless of its
 184      *  current state. */
 185     bool scheduleEvent(DynInstPtr inst, Cycles delay);
 186
 187     /** Unschedule resource event, regardless of its current state. */
 188     void unscheduleEvent(int slot_idx);
 189
 190     /** Unschedule resource event, regardless of its current state. */
 191     bool unscheduleEvent(DynInstPtr inst);
 192
 193     /** Find the request that corresponds to this instruction */
 194     virtual ResReqPtr findRequest(DynInstPtr inst);
 195
 196     /** */
 197     void rejectRequest(DynInstPtr inst);
 198
 199     /** Request a Resource again. Some resources have to special process this
 200      *  in subsequent accesses.
 201      */
 202     virtual void requestAgain(DynInstPtr inst, bool &try_request);
 203
 204     /** Return Latency of Resource */
 205     /*  Can be overridden for complex cases */
 206     virtual Cycles getLatency(int slot_num) { return latency; }
 207
 208   protected:
 209     /** The name of this resource */
 210     std::string resName;
 211
 212     /** ID of the resource. The Resource Pool uses this # to identify this
 213      *  resource.
 214      */
 215     int id;
 216
 217     /** The number of instructions the resource can simultaneously
 218      *  process.
 219      */
 220     int width;
 221
 222     /** Constant latency for this resource.
 223      *  Note: Dynamic latency resources set this to 0 and
 224      *  manage the latency themselves
 225      */
 226     const Cycles latency;
 227
 228   public:
 229     /** List of all Requests the Resource is Servicing. Each request
 230         represents part of the resource's bandwidth
 231     */
 232     std::vector<ResReqPtr> reqs;
 233
 234     /** A list of all the available execution slots for this resource.
 235      *  This correlates with the actual resource event idx.
 236      */
 237     std::vector<int> availSlots;
 238
 239     /** The CPU(s) that this resource interacts with */
 240     InOrderCPU *cpu;
 241
 242   protected:
 243     /** The resource event used for scheduling resource slots on the
 244      *  event queue
 245      */
 246     ResourceEvent *resourceEvent;
 247
 248     /** Default denied resource request pointer*/
 249     ResReqPtr deniedReq;
 250 };
 251
 252 class ResourceEvent : public Event
 253 {
 254   public:
 255     /** Pointer to the Resource this is an event for */
 256     Resource *resource;
 257
 258
 259     /// Resource events that come before other associated CPU events
 260     /// (for InOrderCPU model).
 261     /// check src/sim/eventq.hh for more event priorities.
 262     enum InOrderPriority {
 263         Resource_Event_Pri = 45
 264     };
 265
 266     /** The Resource Slot that this event is servicing */
 267     int slotIdx;
 268
 269     /** Constructs a resource event. */
 270     ResourceEvent();
 271     ResourceEvent(Resource *res, int slot_idx);
 272     virtual ~ResourceEvent() { }
 273
 274     /** Initialize data for this resource event. */
 275     virtual void init(Resource *res, int slot_idx);
 276
 277     /** Processes a resource event. */
 278     virtual void process();
 279
 280     /** Returns the description of the resource event. */
 281     const char *description() const;
 282
 283     /** Set slot idx for event */
 284     void setSlot(int slot) { slotIdx = slot; }
 285
 286     /** Schedule resource event, regardless of its current state. */
 287     void scheduleEvent(Cycles delay);
 288
 289     /** Unschedule resource event, regardless of its current state. */
 290     void unscheduleEvent()
 291     {
 292         if (scheduled())
 293             squash();
 294     }
 295
 296 };
 297
 298 class ResourceRequest
 299 {
 300   public:
 301     typedef ThePipeline::DynInstPtr DynInstPtr;
 302
 303     static int resReqID;
 304
 305     static int maxReqCount;
 306
 307     friend class Resource;
 308
 309   public:
 310     ResourceRequest(Resource *_res);
 311
 312     virtual ~ResourceRequest();
 313
 314     std::string name();
 315
 316     int reqID;
 317
 318     void setRequest(DynInstPtr _inst, int stage_num,
 319                     int res_idx, int slot_num, unsigned _cmd);
 320
 321     virtual void clearRequest();
 322
 323     /** Acknowledge that this is a request is done and remove
 324      *  from resource.
 325      */
 326     void done(bool completed = true);
 327
 328     void freeSlot();
 329
 330     /////////////////////////////////////////////
 331     //
 332     // GET RESOURCE REQUEST IDENTIFICATION / INFO
 333     //
 334     /////////////////////////////////////////////
 335     /** Get Resource Index */
 336     int getResIdx() { return resIdx; }
 337
 338     /** Get Slot Number */
 339     int getSlot() { return slotNum; }
 340     bool hasSlot()  { return slotNum >= 0; }
 341
 342     /** Get Stage Number */
 343     int getStageNum() { return stageNum; }
 344
 345     /** Set/Get Thread Ids */
 346     void setTid(ThreadID _tid) { tid = _tid; }
 347     ThreadID getTid() { return tid; }
 348
 349     /** Instruction this request is for */
 350     DynInstPtr getInst() { return inst; }
 351
 352     /** Data from this request. Overridden by Resource-Specific Request
 353      *  Objects
 354      */
 355     virtual PacketDataPtr getData() { return NULL; }
 356
 357     /** Pointer to Resource that is being used */
 358     Resource *res;
 359
 360     /** Instruction being used */
 361     DynInstPtr inst;
 362
 363     /** Not guaranteed to be set, used for debugging */
 364     InstSeqNum seqNum;
 365
 366     /** Command For This Resource */
 367     unsigned cmd;
 368
 369     short stagePasses;
 370
 371     bool valid;
 372
 373     bool doneInResource;
 374
 375     ////////////////////////////////////////
 376     //
 377     // GET RESOURCE REQUEST STATUS FROM VARIABLES
 378     //
 379     ////////////////////////////////////////
 380     /** Get/Set Completed variables */
 381     bool isCompleted() { return completed; }
 382     void setCompleted(bool cond = true) { completed = cond; }
 383
 384     /** Get/Set Squashed variables */
 385     bool isSquashed() { return squashed; }
 386     void setSquashed() { squashed = true; }
 387
 388     /** Get/Set IsProcessing variables */
 389     bool isProcessing() { return processing; }
 390     void setProcessing(bool cond = true) { processing = cond; }
 391
 392     /** Get/Set IsWaiting variables */
 393     bool isMemStall() { return memStall; }
 394     void setMemStall(bool stall = true) { memStall = stall; }
 395
 396   protected:
 397     /** Resource Identification */
 398     ThreadID tid;
 399     int stageNum;
 400     int resIdx;
 401     int slotNum;
 402
 403     /** Resource Request Status */
 404     bool completed;
 405     bool squashed;
 406     bool processing;
 407
 408     bool memStall;
 409 };
 410
 411 #endif //__CPU_INORDER_RESOURCE_HH__